WO2006003707A1 - Dispositif semi-conducteur et son processus de fabrication - Google Patents

Dispositif semi-conducteur et son processus de fabrication Download PDF

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Publication number
WO2006003707A1
WO2006003707A1 PCT/JP2004/009429 JP2004009429W WO2006003707A1 WO 2006003707 A1 WO2006003707 A1 WO 2006003707A1 JP 2004009429 W JP2004009429 W JP 2004009429W WO 2006003707 A1 WO2006003707 A1 WO 2006003707A1
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WO
WIPO (PCT)
Prior art keywords
film
semiconductor device
insulating film
barrier
wiring
Prior art date
Application number
PCT/JP2004/009429
Other languages
English (en)
Japanese (ja)
Inventor
Kouichi Nagai
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to PCT/JP2004/009429 priority Critical patent/WO2006003707A1/fr
Priority to PCT/JP2005/011955 priority patent/WO2006003940A1/fr
Priority to JP2006528750A priority patent/JP5202846B2/ja
Priority to CN2005800266413A priority patent/CN1993828B/zh
Priority to KR1020067027308A priority patent/KR100985793B1/ko
Publication of WO2006003707A1 publication Critical patent/WO2006003707A1/fr
Priority to US11/647,198 priority patent/US8552484B2/en

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
    • H10B53/40—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the peripheral circuit region

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a ferroelectric capacitor and a manufacturing method thereof.
  • Ferroelectric Random Access Memory using such a ferroelectric capacitor is capable of high-speed operation, low power consumption, and excellent write / read durability. It is a non-volatile memory with features, and further development is expected in the future.
  • the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside.
  • a standard FeRAM ferroelectric capacitor in which a lower electrode made of a Pt film, a ferroelectric film made of a PZT film, and an upper electrode made of a Pt film are sequentially stacked,
  • the substrate is heated to a temperature of about 200 ° C in an atmosphere with a partial pressure of 40 Pa (0.3 Torr)
  • the ferroelectricity of the PbZr Ti O film PZT film
  • a film forming process by the Deposition method or the like is selected.
  • Patent Document 1 JP 2003-197878 A
  • Patent Document 2 JP 2001-68639 A
  • Patent Document 3 Japanese Patent Laid-Open No. 2003-174145
  • Patent Document 4 Japanese Patent Laid-Open No. 2002-176149
  • Patent Document 5 Japanese Patent Laid-Open No. 2003-100994
  • the ferroelectric capacitor has a property that its characteristics are easily deteriorated by hydrogen gas or moisture from the outside. For this reason, it has been difficult for conventional FeRAMs to obtain good test results for the PTHS (Pressure Temperature Humidity Stress) test, which is one of the accelerated life tests.
  • PTHS Pressure Temperature Humidity Stress
  • the PTHS test is performed under conditions of, for example, a temperature of 135 ° C and a humidity of 85% based on the JEDEC (Joint Electron Device Engineering Council) standard. PTH like this
  • An object of the present invention is to provide a semiconductor device that is excellent in resistance to hydrogen gas and moisture resistance, sufficiently suppresses deterioration of characteristics of a ferroelectric capacitor, and can improve PTHS characteristics, and a method for manufacturing the same. is there.
  • a ferroelectric capacitor comprising: a first insulating film formed on the semiconductor substrate and on the ferroelectric capacitor and having a planarized surface; and formed on the first insulating film; Is formed on the flat first barrier film for preventing the diffusion of moisture, the second barrier film having a planarized surface, and the second insulating film formed on the first barrier film.
  • a semiconductor device having a flat second barrier film that prevents diffusion of hydrogen or moisture.
  • a lower electrode, a ferroelectric film formed on the lower electrode, and an upper electrode formed on the ferroelectric film on a semiconductor substrate Forming a ferroelectric capacitor having: a step of forming a first insulating film on the semiconductor substrate and on the ferroelectric capacitor; and planarizing a surface of the first insulating film. Forming a flat first barrier film for preventing diffusion of hydrogen or moisture on the first insulating film; and forming a second insulating film on the first barrier film. A step of planarizing the surface of the second insulating film, and a step of forming a flat second barrier film for preventing diffusion of hydrogen or water on the second insulating film. A method for manufacturing a semiconductor device is provided.
  • a semiconductor device having a body capacitor a first insulating film formed on a semiconductor substrate and a ferroelectric capacitor and having a flattened surface and a first insulating film are formed.
  • a flat second barrier film that prevents the diffusion of hydrogen is formed, so that hydrogen and moisture are securely blocked, and hydrogen and moisture are prevented from reaching the ferroelectric film of the ferroelectric capacitor. can do.
  • deterioration of the electrical characteristics of the ferroelectric capacitor due to hydrogen and moisture can be reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
  • FIG. 1 is a cross-sectional view showing a structure of a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a diagram (part 1) for explaining an effect of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a view (No. 2) for explaining the effect of the semiconductor device according to the first embodiment of the invention.
  • FIG. 4 is a process cross-sectional view (part 1) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 5 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 6 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 7 is a process cross-sectional view (part 4) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 8 is a process cross-sectional view (part 5) illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention
  • FIG. 9 is a process cross-sectional view (No. 6) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 10 is a process sectional view (No. 7) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 11 is a process cross-sectional view (No. 8) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 12 is a process cross-sectional view (No. 9) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 13 is a process cross-sectional view (No. 10) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 14 is a process cross-sectional view (No. 11) showing the method for manufacturing a semiconductor device according to the first embodiment of the invention.
  • FIG. 15 is a process sectional view (No. 12) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 16 is a process cross-sectional view (No. 13) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 17 is a process sectional view (No. 14) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.
  • FIG. 18 is a cross-sectional view showing the structure of the semiconductor device according to the second embodiment of the present invention.
  • FIG. 19 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the second embodiment of the present invention.
  • FIG. 20 is a process cross-sectional view (part 2) illustrating the method for manufacturing a semiconductor device according to the second embodiment of the present invention
  • FIG. 21 is a process cross-sectional view (part 3) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.
  • FIG. 22 is a cross-sectional view showing the structure of the semiconductor device according to the third embodiment of the present invention.
  • FIG. 23 is a process cross-sectional view (part 1) showing the method for manufacturing a semiconductor device according to the third embodiment of the present invention.
  • FIG. 24 is a process cross-sectional view (part 2) illustrating the method for manufacturing the semiconductor device according to the third embodiment of the present invention.
  • FIG. 25 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having stacked cells to which the present invention is applied.
  • FIG. 1 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment
  • FIGS. 2 and 3 are views for explaining the effects of the semiconductor device according to the present embodiment
  • FIGS. 4 to 17 are methods for manufacturing the semiconductor device according to the present embodiment. It is process sectional drawing which shows these.
  • an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon.
  • Semiconductor substrate on which element isolation region 12 is formed In FIG. 10, there are formed Uenoles 14a and 14b.
  • a gate electrode (gate wiring) 18 is formed via a gate insulating film 16 on the semiconductor substrate 10 on which the wells 14a and 14b are formed.
  • the gate electrode 18 has, for example, a polycide structure in which a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film.
  • a metal silicide film such as a tungsten silicide film is stacked on a polysilicon film.
  • an insulating film 19 made of a silicon oxide film is formed on the gate electrode 18.
  • Sidewall insulating films 20 are formed on the side walls of the gate electrode 18 and the insulating film 19.
  • a source Z drain diffusion layer 22 is formed on both sides of the gate electrode 18 on which the sidewall insulating film 20 is formed.
  • the transistor 24 having the gate electrode 18 and the source Z drain diffusion layer 22 is formed.
  • the gate length of the transistor 24 is set to 0.35 zm, for example, or 0.11 to 0.18 xm, for example.
  • a SiON film 25 having a thickness of, for example, 200 nm and a silicon oxide film 26 having a thickness of, for example, 600 nm are sequentially stacked.
  • an interlayer insulating film 27 formed by sequentially laminating the Si ON film 25 and the silicon oxide film 26 is formed.
  • the surface of the interlayer insulating film 27 is flat.
  • a silicon oxide film 34 having a film thickness of lOOnm is formed on the interlayer insulating film 27, for example. Since the silicon oxide film 34 is formed on the flattened interlayer insulating film 27, the silicon oxide film 34 is flat.
  • a lower electrode 36 of the ferroelectric capacitor 42 is formed on the silicon oxide film 34.
  • the lower electrode 36 is composed of, for example, a laminated film in which an oxide aluminum film 36a having a thickness of 20 to 50 nm and a Pt film 36b having a thickness of 100 to 200 nm are sequentially laminated.
  • the film thickness of the Pt film 36b is set to 165 nm.
  • a ferroelectric film 38 of the ferroelectric capacitor 42 is formed on the lower electrode 36.
  • ferroelectric film 38 for example, a PbZr TiO film (PZT film) having a film thickness of 100 250 nm is used.
  • ferroelectric film 38 a 150 nm thick film is used for the ferroelectric film 38.
  • An upper electrode 40 of the ferroelectric capacitor 42 is formed on the ferroelectric film 38.
  • the upper electrode 40 includes an IrO film 40a having a thickness of 25 to 75 nm and an IrO film having a thickness of 150 to 250 nm. It is composed of a laminated film obtained by sequentially laminating the film 40b.
  • Ir ⁇ film 40a IrO film 40a having a thickness of 25 to 75 nm and an IrO film having a thickness of 150 to 250 nm. It is composed of a laminated film obtained by sequentially laminating the film 40b.
  • the film thickness is set to 50 nm, and the film thickness of the IrO film 40b is set to 200 nm.
  • the oxygen composition ratio Y of the O film 40b is set higher than the oxygen composition ratio X of the IrO film 40a.
  • the ferroelectric capacitor 42 including the lower electrode 36, the ferroelectric film 38, and the upper electrode 40 is configured.
  • a barrier film 44 is formed on the ferroelectric film 38 and the upper electrode 40 so as to cover the upper and side surfaces of the ferroelectric film 38 and the upper electrode 40.
  • a 20-lOOnm aluminum oxide (Al 2 O 3) film is used as the noria film 44.
  • the barrier film 44 is a film having a function of preventing diffusion of hydrogen and moisture.
  • the metal oxide constituting the ferroelectric film 38 is reduced by hydrogen or moisture, and the electrical characteristics of the ferroelectric capacitor 42 are reduced. Will deteriorate.
  • the barrier film 44 By forming the barrier film 44 so as to cover the upper surface and the side surfaces of the ferroelectric film 38 and the upper electrode 40, it is possible to suppress hydrogen and moisture from reaching the ferroelectric film 38. It is possible to suppress the deterioration of the electrical characteristics of the.
  • a barrier film 46 is formed on the ferroelectric capacitor 42 and the silicon oxide film 34 covered with the barrier film 44.
  • the barrier film 46 for example, an aluminum oxide film having a thickness of 20-lOOnm is used.
  • the barrier film 46 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier film 44.
  • an interlayer insulating film 48 made of, for example, a silicon oxide film having a thickness of 1500 nm is formed on the barrier film 46.
  • the surface of the interlayer insulating film 48 is planarized.
  • contact holes 50a and 50b reaching the source / drain diffusion layer 22 are formed, respectively. Further, in the interlayer insulating film 48, the barrier film 46, and the barrier film 44, a contact hole 52a reaching the upper electrode 40 is formed. A contact hole 52b reaching the lower electrode 36 is formed in the interlayer insulating film 48, the barrier film 46, and the barrier film 44.
  • a barrier metal film (not shown) is formed by sequentially laminating TiN films.
  • the Ti film is formed to reduce contact resistance, and the TiN film is formed to prevent diffusion of tungsten, which is a conductor plug material.
  • the barrier metal film formed on each contact hole to be described later is also formed for the same purpose.
  • Conductor plugs 54a and 54b made of tungsten are respectively carried in the contact holes 50a and 50b in which the barrier metal film is formed.
  • a wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed on the interlayer insulating film 48 and in the contact hole 52a.
  • a wiring 56b electrically connected to the lower electrode 36 is formed on the interlayer insulating film 48 and in the contact hole 52b.
  • a wiring 56c electrically connected to the conductor plug 54b is formed on the interlayer insulating film 48.
  • a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially formed. It is comprised by the laminated film formed by laminating
  • the source / drain diffusion layer 22 of the transistor 24 and the upper electrode 40 of the ferroelectric capacitor 42 are electrically connected via the conductor plug 54a and the wiring 56a, so that one transistor 24 and 1 A FeRAM 1T1C type memory cell having two ferroelectric capacitors 42 is formed.
  • multiple memory cells are arranged in the memory cell area of the FeRAM chip.
  • a barrier film 58 is formed on the interlayer insulating film 48 on which the wirings 56a, 56b, 56c are formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, 56c.
  • a 20 nm aluminum oxide film is used as the barrier film 58.
  • the barrier film 58 is a film having a function of preventing the diffusion of hydrogen and moisture similarly to the barrier films 44 and 46.
  • the barrier film 58 is also used to suppress damage caused by plasma.
  • a silicon oxide film 60 having a thickness of 2600 nm is formed on the barrier film 58.
  • the surface of the silicon oxide film 60 is planarized.
  • the planarized silicon oxide film 60 is left and deposited on the self-spring 56a, 56b, 56c with a film thickness of, for example, lOOOnm.
  • a silicon oxide film 61 having a film thickness of lOOnm is formed on the silicon oxide film 60. Since the silicon oxide film 61 is formed on the flattened silicon oxide film 60, the silicon oxide film 61 is flat.
  • a noor film 62 is formed on the silicon oxide film 61.
  • the barrier film 62 for example, an aluminum oxide film having a thickness of 20 to 70 nm is used.
  • an aluminum oxide film having a thickness of 50 nm is used as the noria film 62. Since the NORA film 62 is formed on the flat silicon oxide film 61, the barrier film 62 is flat.
  • the barrier film 62 is a film having a function of preventing the diffusion of hydrogen and moisture, like the barrier films 44, 46, and 58. Further, the barrier film 62 is flat because it is formed on the flat silicon oxide film 61, and is formed with extremely good coverage as compared with the barrier films 44, 46, and 58. Therefore, such a flat barrier film 62 can more reliably prevent hydrogen and moisture from diffusing. In practice, the barrier film 62 is formed not only on the memory cell region of the FeRAM chip on which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also on the entire surface of the FeRAM chip including the peripheral circuit region. ing.
  • a silicon oxide film 64 having a film thickness of 50-lOOnm is formed on the barrier film 62.
  • the thickness of the silicon oxide film 64 is set to lOOnm.
  • the interlayer insulating film 66 is constituted by the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64.
  • a contact hole 68 reaching the wiring 56c is formed.
  • a barrier metal film (not shown) is formed by sequentially stacking, for example, a Ti film having a thickness of 20 nm and a TiN film having a thickness of 50 nm, for example.
  • a barrier metal film made of a TiN film may be formed without forming a Ti film.
  • a conductor plug 70 made of tungsten is carried in the contact hole 68 in which the barrier metal film is formed.
  • a wiring 72 a is formed on the interlayer insulating film 66. On the interlayer insulating film 66, a wiring 72b electrically connected to the conductor plug 70 is formed. Wiring 72a, 72b (first
  • the metal wiring layer 72 includes, for example, a TiN film with a thickness of 50 nm, an AlCu alloy film with a thickness of 500 nm, It consists of a laminated film consisting of a 5nm thick Ti film and a 150nm thick TiN film.
  • a silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the interlayer insulating film 66 and on the wirings 72a and 72b.
  • the surface of the silicon oxide film 74 is planarized.
  • a silicon oxide film 76 having a film thickness of lOOnm is formed on the silicon oxide film 74. Since the silicon oxide film 76 is formed on the flattened silicon oxide film 74, the silicon oxide film 76 is flat.
  • a noria film 78 is formed on the silicon oxide film 76.
  • the barrier film 78 for example, an aluminum oxide film having a film thickness of 20-lOOnm is used.
  • the barrier film 78 an aluminum oxide film having a thickness of 50 nm is used. Since the NORA film 78 is formed on the flat silicon oxide film 76, the barrier film 78 is flat.
  • the barrier film 78 is a film having a function of preventing diffusion of hydrogen and moisture. Further, since the barrier film 78 is formed on the flat silicon oxide film 61, it is flat. Like the barrier film 62, the barrier film 78 has an extremely good coverage as compared with the barrier films 44, 46, and 58. It is formed with. Therefore, diffusion of hydrogen and moisture can be prevented more reliably by using such a flat NOR film 62. Actually, the barrier film 78 includes not only the memory cell region of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the peripheral circuit region and the like, like the barrier film 62. It is formed over the entire surface of the FeRAM chip.
  • a silicon oxide film 80 having a film thickness of lOOnm is formed on the barrier film 78.
  • the interlayer insulating film 82 is configured by the silicon oxide film 74, the silicon oxide film 76, the barrier film 78, and the silicon oxide film 80.
  • contact holes 84a and 84b reaching the wirings 72a and 72b are formed, respectively.
  • a barrier metal film (not shown) is formed by sequentially laminating, for example, a 20 nm thick Ti film and a 50 nm thick TiN film, for example.
  • a barrier metal film made of a TiN film may be formed without forming a Ti film.
  • the contact holes 84a and 84b in which the barrier metal film is formed are made of tungsten. Conductor plugs 86a and 86b are respectively carried.
  • the wiring 88a electrically connected to the conductor plug 86a and the wiring electrically connected to the conductor plug 86b (bon Ding pad) 88b is formed on the interlayer insulating film 82 in which the conductor plugs 86a and 86b are carried.
  • the wirings 88a and 88b (third metal wiring layer 88) are composed of, for example, a laminated film in which a 50 nm thick TiN film, a 500 nm thick AlCu alloy film, and a 150 nm thick TiN film are sequentially laminated. ing.
  • a silicon oxide film 90 having a thickness of 100 to 300 nm is formed on the interlayer insulating film 82 and the wirings 88a and 88b.
  • the thickness of the silicon oxide film 90 is set to lOOnm.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed on the silicon oxide film 90.
  • a polyimide resin film 94 with a film thickness of 26 ⁇ m is formed on the silicon nitride film 92.
  • an opening 96 reaching the wiring (bonding pad) 88b is formed in the polyimide resin film 94, the silicon nitride film 92, and the silicon oxide film 90. That is, in the silicon nitride film 92 and the silicon oxide film 90, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92 and the silicon oxide film 90.
  • An external circuit (not shown) is electrically connected to the wiring (bonding pad) 88b through the opening 96.
  • the semiconductor device according to the present embodiment is configured.
  • the main feature is that it has a flat barrier film 78 formed between the third metal wiring layer 88 (wirings 88a and 88b).
  • a ferroelectric key caused by hydrogen or moisture is used.
  • a barrier film made of aluminum oxide or the like for preventing diffusion of hydrogen or moisture is formed above the ferroelectric capacitor.
  • the barrier film when a barrier film is formed on an interlayer insulating film or the like having a step on the surface, the barrier film is not so well covered, so that diffusion of hydrogen and moisture in the barrier film is difficult. Cannot be sufficiently prevented.
  • hydrogen or moisture reaches the ferroelectric film of the ferroelectric capacitor, the ferroelectric properties of the ferroelectric film are reduced or lost by hydrogen or moisture, and the electrical characteristics of the ferroelectric capacitor are deteriorated. It becomes.
  • FIG. 2 is a cross-sectional view showing a defect portion generated in a flat barrier film formed in a semiconductor device having a ferroelectric capacitor.
  • the semiconductor device shown in FIG. 2 unlike the semiconductor device according to the present embodiment, only the single-layer film 78 is formed as a flat barrier film, and the barrier film 62 is not formed.
  • the barrier film 62 is not formed.
  • FIG. 2 even in the flat knitted rear film 78, a defective portion 110 having a poor coverage is formed due to a step caused by micro scratches generated on the surface of the insulating film underneath. It is thought that it occurs.
  • two flat barrier films that is, the first metal wiring layer 56 and the second metal wiring layer 72 formed above the ferroelectric capacitor 42, A flat barrier film 62 formed between the second metal wiring layer 72 and a flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 is formed.
  • FIG. 3A is a plan view showing the structure of the semiconductor device according to the present embodiment
  • FIG. 3B is a cross-sectional view of the semiconductor device according to the present embodiment corresponding to FIG. FIG. 2 schematically shows a defect portion 110 generated in two flat barrier films 62 and 78.
  • FIG. 3A is a plan view showing the structure of the semiconductor device according to the present embodiment
  • FIG. 3B is a cross-sectional view of the semiconductor device according to the present embodiment corresponding to FIG.
  • FIG. 2 schematically shows a defect portion 110 generated in two flat barrier films 62 and 78.
  • the probability that the defective portion 110 is generated at substantially the same plane position is very small. Therefore, in the semiconductor device according to the present embodiment, even if hydrogen or moisture enters the inside of the semiconductor device through the defect portion 110 generated in the flat barrier film 78 located in the upper layer, the flat device located in the lower layer is used.
  • the barrier film 62 can reliably block the intruding hydrogen and moisture from reaching the ferroelectric capacitor 42.
  • film 62 and a flat barrier film 78 formed between the second metal wiring layer 72 and the third metal wiring layer 88 are formed, so that hydrogen and moisture are securely barriered, and hydrogen and moisture are strong.
  • Reaching the ferroelectric film 38 of the dielectric capacitor 42 can be reliably prevented.
  • an element isolation region 12 that defines an element region is formed on a semiconductor substrate 10 made of, for example, silicon by, for example, a LOCOS (LOCal Oxidation of Silicon) method.
  • LOCOS LOCal Oxidation of Silicon
  • the dopants 14a and 14b are formed by introducing dopant impurities by ion implantation.
  • a transistor 24 having a gate electrode (gate wiring) 18 and a source / drain diffusion layer 22 is formed in the element region by using a normal transistor formation method (see FIG. 4A). .
  • an SiON film 25 of, eg, a 200 nm-thickness is formed on the entire surface by, eg, plasma CVD (Chemical Vapor Deposition).
  • a silicon oxide film 26 of, eg, a 600 nm-thickness is formed on the entire surface by a plasma TEOSCVD method (see FIG. 4B).
  • the interlayer insulating film 27 is constituted by the SiON film 25 and the silicon oxide film 26.
  • the surface of the interlayer insulating film 27 is flattened by, eg, CMP (see FIG. 4C).
  • the heat treatment is performed.
  • a silicon oxide film 34 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 5A).
  • heat treatment is performed in an oxygen atmosphere by, eg, RTA (Rapid Thermal Annealing).
  • the heat treatment temperature is, for example, 650 ° C
  • the heat treatment time is, for example, 1-12 minutes.
  • a laminated film 36 composed of the aluminum oxide film 36a and the Pt film 36b is formed.
  • the multilayer film 36 becomes a lower electrode of the ferroelectric capacitor 42.
  • ferroelectric film 38 is formed on the entire surface by, eg, sputtering.
  • a PZT film having a thickness of 100 to 250 nm is formed.
  • the ferroelectric film 38 is formed by the sputtering method has been described as an example, but the method of forming the ferroelectric film is not limited to the sputtering method.
  • the ferroelectric film may be formed by a sol-gel method, a MOD (Metal Organic Deposition) method, a MOCVD method, or the like.
  • heat treatment is performed in an oxygen atmosphere by, for example, the RTA method.
  • the heat treatment temperature is, for example, 550-600 ° C
  • the heat treatment time is, for example, 60-120 seconds.
  • IrO having a film thickness of, for example, 25 to 75 nm is formed by, for example, sputtering or MOCVD.
  • a film 40a is formed.
  • heat treatment is performed, for example, at 600 to 800 ° C for 10 to 100 seconds in an argon and oxygen atmosphere.
  • the IrO film 40b is formed so as to be higher than the composition ratio X.
  • a laminated film 40 composed of the IrO film 40a and the IrO film 40b is formed (see FIG. 5B).
  • the laminated film 40 becomes an upper electrode of the ferroelectric capacitor 42.
  • a photoresist film 98 is formed on the entire surface by, eg, spin coating.
  • a photoresist film 98 is formed on the ferroelectric capacitor 42 by photolithography. Pattern in the planar shape of the upper electrode 40.
  • the laminated film 40 is etched using the photoresist film 98 as a mask.
  • Ar gas and C1 gas are used as the etching gas.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 700 ° C for 30 to 120 minutes. This heat treatment is intended to prevent the surface of the upper electrode 40 from becoming abnormal.
  • a photoresist film 100 is formed on the entire surface by, eg, spin coating.
  • the photoresist film 100 is patterned into a planar shape of the ferroelectric film 38 of the ferroelectric capacitor 42 by photolithography.
  • the ferroelectric film 38 is etched using the photoresist film 100 as a mask (see FIG. 6A). Thereafter, the photoresist film 100 is peeled off.
  • heat treatment is performed in an oxygen atmosphere, for example, at 300 to 400 ° C for 30 to 120 minutes.
  • a barrier film 44 is formed by, eg, sputtering or CVD (see FIG. 6B).
  • the barrier film 44 for example, an aluminum oxide film having a thickness of 20 to 50 nm is formed.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
  • a photoresist film 102 is formed on the entire surface by, eg, spin coating.
  • the photoresist film 102 is patterned into the planar shape of the lower electrode 36 of the ferroelectric capacitor 42 by photolithography.
  • the barrier film 44 and the laminated film 36 are etched (see FIG. 6C).
  • the lower electrode 36 made of a laminated film is formed.
  • the barrier film 44 remains so as to cover the upper electrode 40 and the ferroelectric film 38. Thereafter, the photoresist film 102 is peeled off.
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 600 ° C for 30 to 120 minutes.
  • the noor film 46 is formed on the entire surface by, eg, sputtering or CVD.
  • the barrier film 46 for example, an aluminum oxide film having a thickness of 20 lOOnm is formed (see FIG. 7A).
  • the ferroelectric capacitor 42 covered with the barrier film 44 is further covered.
  • the barrier film 46 is formed.
  • heat treatment is performed in an oxygen atmosphere, for example, at 500 to 700 ° C for 30 to 120 minutes.
  • an interlayer insulating film 48 made of a silicon oxide film having a thickness of, eg, 1500 nm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 7B).
  • the surface of the interlayer insulating film 48 is planarized by, eg, CMP (see FIG. 7C).
  • This heat treatment is for removing moisture in the interlayer insulating film 48 and changing the film quality of the interlayer insulating film 48 so that moisture enters the interlayer insulating film 48.
  • the surface of the interlayer insulating film 48 is nitrided, and a SiON film (not shown) is formed on the surface of the interlayer insulating film 48.
  • contact holes 50a and 50b reaching the source / drain diffusion layer 22 are formed in the interlayer insulating film 48, the NORA film 46, the silicon oxide film 34, and the interlayer insulating film 27 by photolithography and etching. (See Figure 8 (a)).
  • a Ti film of, eg, a 20 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • the Ti film and the TiN film constitute a barrier metal film (not shown).
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tandastain film and the barrier metal film are polished by CMP, for example, until the surface of the interlayer insulating film 48 is exposed.
  • the conductor plugs 54a and 54b made of tungsten are loaded in the contact holes 50a and 50b, respectively (see FIG. 8 (b)).
  • a SiON film 104 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD.
  • the upper electrode 40 of the ferroelectric capacitor 42 is reached in the SiON film 104, the interlayer insulating film 48, the barrier film 46, and the barrier film 44 by photolithography and dry etching.
  • the contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 is formed (see FIG. 8 (c)).
  • heat treatment is performed in an oxygen atmosphere, for example, at 400 to 600 ° C for 30 to 120 minutes.
  • This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
  • the heat treatment may be performed in an ozone atmosphere. Even when heat treatment is performed in an ozone atmosphere, oxygen can be supplied to the ferroelectric film 38 of the capacitor, and the electrical characteristics of the ferroelectric capacitor 42 can be recovered.
  • the SiON film 104 is removed by etching.
  • a TiN film with a thickness of 150 nm, an AlCu alloy film with a thickness of 550 nm, a Ti film with a thickness of 5 nm, and a TiN film with a thickness of 150 nm are sequentially stacked on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the first metal wiring layer 56 that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected.
  • a silicon film 58 is formed on the entire surface by, eg, sputtering or CVD.
  • the barrier film 58 for example, an aluminum oxide film having a film thickness of 20 to 70 nm is formed (see FIG. 9B).
  • the barrier film 58 an aluminum oxide film having a thickness of 20 nm is formed.
  • the barrier film 58 is formed so as to cover the upper surfaces and side surfaces of the wirings 56a, 56b, and 56c.
  • a silicon oxide film 60 of, eg, a 2600 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 10A).
  • the surface of the silicon oxide film 60 is planarized by, eg, CMP (see FIG. 10B).
  • CMP see FIG. 10B.
  • This heat treatment is for removing moisture in the silicon oxide film 60 and changing the film quality of the silicon oxide film 60 so that moisture does not easily enter the silicon oxide film 60.
  • the surface of the silicon oxide film 60 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 60.
  • a silicon oxide film 61 having a thickness of, for example, lOOnm is formed on the planarized silicon oxide film 60 by, eg, plasma TEOSCVD. Since the silicon oxide film 61 is formed on the planarized silicon oxide film 60, the silicon oxide film 61 becomes flat.
  • This heat treatment is for removing moisture in the silicon oxide film 61 and changing the film quality of the silicon oxide film 61 so that moisture does not easily enter the silicon oxide film 61.
  • the surface of the silicon oxide film 61 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 61.
  • the barrier film 62 is formed on the flat silicon oxide film 61 by, eg, sputtering or CVD.
  • the barrier film 62 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed.
  • an aluminum oxide film having a thickness of 50 nm is formed as the noble film 62. Since the barrier film 62 is formed on the flat silicon oxide film 61, the barrier film 62 becomes flat.
  • a silicon oxide film 64 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 11A).
  • the barrier film 58, the silicon oxide film 60, the silicon oxide film 61, the barrier film 62, and the silicon oxide film 64 constitute the interlayer insulating film 66.
  • This heat treatment is for removing moisture in the silicon oxide film 64 and changing the film quality of the silicon oxide film 64 so that moisture does not easily enter the silicon oxide film 64.
  • the surface of the silicon oxide film 64 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 64.
  • the silicon oxide film 64 and the barrier are formed by photolithography and dry etching.
  • a contact hole 68 reaching the wiring 56c is formed in the film 62, the silicon oxide film 61, the silicon oxide film 60, and the silicon film 58 (see FIG. 11B).
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a barrier metal film (not shown) is constituted by the TiN film.
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tungsten film is etched back by, for example, the EB (etch back) method until the surface of the TiN film is exposed.
  • the conductor plug 70 made of tungsten is loaded in the contact hole 68 (see FIG. 12A).
  • an AlCu alloy film having a thickness of 500 nm, and a Ti film having a thickness of 5 nm for example,
  • a TiN film having a thickness of 150 nm is sequentially stacked.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the second metal wiring layer 72 that is, the wiring 72a and the wiring 72b electrically connected to the conductor plug 70 are formed (see FIG. 12B).
  • a silicon oxide film 74 of, eg, a 2200 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 13A).
  • the surface of the silicon oxide film 74 is flattened by, eg, CMP (see FIG. 13B).
  • This heat treatment is for removing water in the silicon oxide film 74 and changing the film quality of the silicon oxide film 74 so that the water does not easily enter the silicon oxide film 74.
  • the surface of the silicon oxide film 74 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 74.
  • a silicon oxide film 76 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD. Since the silicon oxide film 76 is formed on the planarized silicon oxide film 74, the silicon oxide film 76 becomes flat. [0151] Next, in a plasma atmosphere generated using NO gas or N gas, for example, 35
  • This heat treatment is for removing moisture in the silicon oxide film 76 and changing the film quality of the silicon oxide film 76 to make it difficult for moisture to enter the silicon oxide film 76.
  • the surface of the silicon oxide film 76 is nitrided, and a SiN film (not shown) is formed on the surface of the silicon oxide film 76.
  • a barrier film 78 is formed on the flat silicon oxide film 76 by, eg, sputtering or CVD.
  • the barrier film 78 for example, an aluminum oxide film having a thickness of 2070 nm is formed.
  • an aluminum oxide film having a thickness of 50 nm is formed as the noor film 78. Since the barrier film 78 is formed on the flat silicon oxide film 76, the barrier film 78 becomes flat.
  • a silicon oxide film 80 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 14 (a)).
  • the interlayer insulating film 82 is constituted by zero.
  • This heat treatment is for removing moisture in the silicon oxide film 80 and changing the film quality of the silicon oxide film 76 so that moisture does not easily enter the silicon oxide film 80.
  • the surface of the silicon oxide film 80 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 80.
  • contact horns 84a and 84b reaching the wirings 72a and 72b are formed in the silicon oxide film 80, the barrier film 78, the silicon oxide film 76, and the silicon oxide film 74 by photolithography and dry etching (FIG. 14). (See (b)).
  • a TiN film of, eg, a 50 nm-thickness is formed on the entire surface by, eg, sputtering.
  • a barrier metal film (not shown) is constituted by the TiN film.
  • a tungsten film of, eg, a 500 nm-thickness is formed on the entire surface by, eg, CVD.
  • the tungsten film is etched until the surface of the TiN film is exposed, for example, by the EB method. Chibak back. In this way, the conductor plugs 86a and 86b made of tungsten are loaded in the contact holes 84a and 84b, respectively (see FIG. 15 (a)).
  • an AlCu alloy film having a thickness of, for example, 500 nm and a TiN film having a thickness of, for example, 150 nm are sequentially stacked on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the third metal wiring layer 88 that is, the wiring 88a electrically connected to the conductor plug 86a and the wiring 88b electrically connected to the conductor plug 88b are formed (see FIG. 15 (b)). ).
  • a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
  • This heat treatment is for removing moisture in the silicon oxide film 90 and changing the film quality of the silicon oxide film 90 so that moisture does not easily enter the silicon oxide film 90.
  • the surface of the silicon oxide film 90 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 90.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
  • the silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
  • a photoresist film 106 is formed on the entire surface by, eg, spin coating.
  • an opening 108 is formed in the photoresist film 106 to expose a region where the opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90. .
  • Etch 90 an opening 96a reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92 and the silicon oxide film 90 (see FIG. 16B). Thereafter, the photoresist film 106 is peeled off.
  • a polyimide resin film 94 having a film thickness of 2 to 6 ⁇ m is formed by spin coating, for example. (See Fig. 17 (a)).
  • an opening 96b reaching the wiring (bonding pad) 88b is formed in the polyimide resin film 94 by photolithography (see FIG. 17B).
  • the semiconductor device according to the present embodiment is manufactured.
  • a PTHS test is performed on the semiconductor device according to the present embodiment, and the results of evaluating the PTHS characteristics of the semiconductor device according to the present embodiment are described.
  • the FeRAM chip of the semiconductor device according to the present embodiment was stored under conditions of 2 atm, temperature of 121 ° C, and humidity of 100%, and 168 hours, 336 hours, 504 hours, 504 hours, and 672 At each time point, the presence or absence of defective cells was confirmed for each of the five chip samples formed using the same woofer.
  • the thickness of the barrier film 58 was set to 20 nm
  • the thickness of the flat barrier film 62 was set to 50 nm
  • the monthly thickness of the flat rear film 78 was set to 70 nm.
  • the PTHS test similar to the above was performed when the flat barrier film 58 was not formed, that is, when only one flat barrier film was formed.
  • the thickness of the barrier film 58 was set to 70 nm
  • the thickness of the flat barrier film 78 was set to 70 nm.
  • the thickness of the barrier film 58 was 2 Onm
  • the thickness of the flat barrier film 78 was 50 nm.
  • the structure of the semiconductor device according to Comparative Examples 1 and 2 was the same as that of the semiconductor device according to the present embodiment except that the flat barrier film 58 was not formed.
  • defective cells occur at all of 168 hours, 336 hours, 504 hours, 504 hours, and 672 hours for all five chip samples. There was no.
  • one of the five chip samples had one defective cell after 168 hours, and three defective cells after 336 hours. When 504 hours passed, there were 10 defective cells, and when 672 hours passed, there were 18 bad cells. For other chip samples, 168 hours and 336 hours have passed. No defective cells were generated up to the time point, but one defective cell was generated after 504 hours, and 26 defective cells were reached after 672 hours. Furthermore, in other chip samples, no defective cells were generated until 168 hours and 336 hours passed, but 22 defective cells were generated after 504 hours and failed after 672 hours passed. There were 62 Senores. Of the five chip samples, only two chip samples had no defective cells at any time after 168 days temple, 3363 temples, 504 days temple, 504 hours, and 672 hours. there were.
  • the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved, and the mass production certification level of the PTHS test for FeRAM is sufficiently exceeded. It was confirmed that it was possible.
  • the barrier film for preventing the diffusion of hydrogen and moisture in addition to the barrier films 44, 46, 58, the first film formed above the ferroelectric capacitor 42 is provided.
  • the electrical characteristics of the ferroelectric capacitor 42 can be reliably prevented from being deteriorated by hydrogen and moisture, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be greatly improved.
  • FIG. 18 is a sectional view showing the structure of the semiconductor device according to the present embodiment.
  • FIGS. 19 to 21 are process sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
  • the basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment.
  • the semiconductor device according to the present embodiment is different from the semiconductor device according to the first embodiment in that the semiconductor device according to the present embodiment further includes a NOR film 114 formed above the third metal wiring layer 88 (wirings 88a and 88b).
  • a silicon oxide film 112 having a thickness of, eg, 1500 nm is formed on the interlayer insulating film 82 and the wirings 88a and 88b.
  • the surface of the silicon oxide film 112 is flattened by, for example, CMP after the formation thereof, and the silicon oxide film 112 on the wiring 88b remains, for example, with a film thickness of 350 nm.
  • a silicon film 114 is formed on the flattened silicon oxide film 112.
  • the barrier film 114 for example, an aluminum oxide film having a thickness of 2070 nm is used. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the barrier film 114 is flat.
  • the barrier film 114 like the barrier films 44, 46, 58, 62, 78, diffuses hydrogen and moisture. It is a film having a function to prevent. Further, since the barrier film 114 is formed on the flattened silicon oxide film 112, it is flat, and in the same way as the barrier films 62 and 78, compared with the barrier films 44, 46 and 58, the barrier film 114 is extremely flat. It is formed with good coverage. Accordingly, such a flat barrier film 114 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 114 is not only the memory cell area of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, but also the peripheral circuit area, etc. It is formed over the entire surface of the FeRAM chip including
  • a silicon oxide film 90 having a thickness of 50 to 150 nm is formed on the barrier film 114.
  • a silicon nitride film 92 having a thickness of 350 nm is formed on the silicon oxide film 90.
  • a polyimide resin film 94 with a film thickness of 36 ⁇ m is formed on the silicon nitride film 92.
  • the polyimide resin film 94, the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 have an opening 96 reaching the wiring (bonding pad) 88b. That is, in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112, an opening 96a reaching the wiring (bonding pad) 88b is formed. In the polyimide resin film 94, an opening 96b is formed in a region including the opening 96a formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112.
  • the semiconductor device according to the present embodiment is formed above the ferroelectric capacitor 42 in addition to the barrier films 44, 46, and 58 as a barrier film for preventing diffusion of hydrogen and moisture.
  • the main feature is that it has a flat barrier film 114.
  • the semiconductor device according to the present embodiment is flat in the semiconductor device according to the first embodiment.
  • the flat barrier film 114 is formed above the third metal wiring layer 88, so that the hydrogen and moisture are more securely barriered, and the hydrogen and moisture are ferroelectric capacitors. Reaching the ferroelectric film 38 of 42 can be prevented more reliably. As a result, deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the PTHS characteristics of the semiconductor device having the ferroelectric capacitor can be further greatly improved.
  • the third metal wiring layer (wiring 88a, wiring 88b) is formed in the same manner as in the semiconductor device manufacturing method according to the first embodiment shown in FIGS.
  • a silicon oxide film 112 of, eg, a 1500 nm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 19A).
  • the surface of the silicon oxide film 112 is planarized by, eg, CMP (see FIG. 19B).
  • This heat treatment is for removing moisture in the silicon oxide film 112 and changing the film quality of the silicon oxide film 112 so that the moisture does not easily enter the silicon oxide film 112.
  • the surface of the silicon oxide film 112 is nitrided, and a SiON film (not shown) is formed on the surface of the silicon oxide film 112.
  • a barrier film 114 is formed on the flattened silicon oxide film 112 by, eg, sputtering or CVD.
  • the nore film 114 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the barrier film 114 is formed on the planarized silicon oxide film 112, the NOR film 114 becomes flat.
  • a silicon oxide film 90 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD.
  • a silicon nitride film 92 of, eg, a 350 nm-thickness is formed by, eg, CVD method
  • the silicon nitride film 92 is for blocking moisture and preventing the metal wiring layers 88, 72, 56 and the like from being corroded by moisture.
  • a photoresist film 106 is formed on the entire surface by, eg, spin coating.
  • an opening reaching the wiring (bonding pad) 88b is formed in the silicon nitride film 92, the silicon oxide film 90, the barrier film 114, and the silicon oxide film 112 in the photoresist film 106 by photolithography.
  • An opening 108 exposing the region is formed.
  • the photoresist film 106 is peeled off.
  • the semiconductor device according to the present embodiment is manufactured.
  • the barrier film for preventing the diffusion of hydrogen and moisture in addition to the barrier films 44, 46, 58, the first film formed above the ferroelectric capacitor 42 is provided.
  • the deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and moisture can be more reliably prevented, and the ferroelectric capacitor 42 can be prevented.
  • the PTHS characteristics of a semiconductor device having a shita can be further greatly improved.
  • FIG. 22 is a cross-sectional view showing the structure of the semiconductor device according to the present embodiment.
  • FIGS. 23 and 24 are process cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. Note that the same components as those of the semiconductor device and the manufacturing method thereof according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted or simplified.
  • the basic configuration of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment.
  • the semiconductor device according to the present embodiment is different from the first embodiment in that it further includes a flat barrier film 116 between the ferroelectric capacitor 42 and the first metal wiring layer 56 (wirings 56a, 56b, 56c). This is different from the semiconductor device.
  • the rear film 116 is formed on the interlayer insulating film 48 on which the conductor plugs 50a and 50b are carried.
  • the barrier film 116 for example, an aluminum oxide film having a thickness of 20 to 70 ⁇ m is used.
  • the interlayer insulating film 48 is flattened and the barrier film 116 is formed on the flattened interlayer insulating film 48, the barrier film 116 is flat.
  • the barrier film 116 is a film having a function of preventing diffusion of hydrogen and moisture. Further, since the barrier film 116 is formed on the flattened silicon oxide film 48, it is flat, and, like the barrier films 62 and 78, compared with the barrier films 44, 46 and 58, It is formed with good coverage. Therefore, such a flat barrier film 116 can more reliably prevent hydrogen and moisture from diffusing. Actually, the barrier film 116 is not only the memory cell area of the FeRAM chip in which a plurality of memory cells having the ferroelectric capacitor 42 are arranged, as in the barrier films 62 and 78, but also the peripheral circuit area. Etc. are formed over the entire surface of the FeRAM chip.
  • a silicon oxide film 118 having a thickness of lOOnm is formed on the barrier film 116.
  • a contact hole 52a reaching the upper electrode 40 is formed in the silicon oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the barrier film 44. Also silicon acid A contact hole 52b reaching the lower electrode 36 is formed in the oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the rear film 44.
  • a contact hole 120a reaching the conductor plug 54a is formed in the silicon oxide film 118 and the barrier film 116. Further, a contact hole 120b reaching the conductor plug 54b is formed in the silicon oxide film 118 and the barrier film 116.
  • a wiring 56a electrically connected to the conductor plug 54a and the upper electrode 40 is formed on the silicon oxide film 118, in the contact hole 52a, and in the contact hole 120a.
  • a wiring 56b electrically connected to the lower electrode 36 is formed on the silicon oxide film 118 and in the contact hole 52b.
  • a wiring 56c electrically connected to the conductor plug 54b is formed on the silicon oxide film 118 and in the contact hole 120b.
  • the ferroelectric film 42 and the ferroelectric capacitor are used as the barrier film for preventing the diffusion of hydrogen and moisture in addition to the barrier films 44, 46, and 58.
  • the ferroelectric capacitor 42 and the first metal formed above the ferroelectric capacitor 42 in addition to the flat barrier films 62 and 78 in the semiconductor device according to the first embodiment. Since the flat barrier film 116 is formed between the wiring layer 56 and the barrier layer 116, hydrogen and moisture are more securely blocked, and the hydrogen and moisture reach the ferroelectric film 38 of the ferroelectric capacitor 42 more reliably. Can be prevented. As a result, it is possible to more reliably prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water, and to further greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor. it can.
  • the conductor plugs 54a and 54b are formed in the same manner as in the method of manufacturing the semiconductor device according to the first embodiment shown in FIGS. 4 to 7, FIG. 8A, and FIG. see a)).
  • NOR film 116 is formed by, for example, sputtering or CVD.
  • the noria film 114 for example, an aluminum oxide film having a thickness of 20 to 70 nm is formed. Since the interlayer insulating film 48 is flattened and the barrier film 116 is formed on the flattened interlayer insulating film 48, the barrier film 116 becomes flat.
  • a silicon oxide film 118 of, eg, a lOOnm-thickness is formed on the entire surface by, eg, plasma TEOSCVD (see FIG. 23B).
  • contact holes 120a and 120b reaching the conductor plugs 54a and 54b are formed in the silicon oxide film 118 and the barrier film 116 by photolithography and dry etching (see FIG. 23C).
  • an SiON film 122 having a thickness of, for example, lOOnm is formed on the entire surface by, eg, CVD (see FIG. 24A).
  • the upper portion of the ferroelectric capacitor 42 is formed on the SiONfl layer 122, the silicon oxide film 118, the barrier film 116, the interlayer insulating film 48, the barrier film 46, and the rear film 44 by photolithography and dry etching.
  • a contact hole 52a reaching the electrode 40 and a contact hole 52a reaching the lower electrode 36 of the ferroelectric capacitor 42 are formed (see FIG. 24B).
  • heat treatment is performed in an oxygen atmosphere, for example, at 500 ° C for 60 minutes. This heat treatment is for recovering the electrical characteristics of the ferroelectric capacitor 42 by supplying oxygen to the ferroelectric film 38 of the ferroelectric capacitor 42.
  • the SiON film 122 is removed by etching.
  • a TiN film having a thickness of 150 nm, an AlCu alloy film having a thickness of 550 nm, a Ti film having a thickness of 5 nm, and a TiN film having a thickness of 150 nm, for example, are sequentially laminated on the entire surface.
  • a conductor film is formed by sequentially stacking a TiN film, an AlCu alloy film, a Ti film, and a TiN film.
  • the conductor film is patterned by photolithography and dry etching.
  • the first metal wiring layer 56 that is, the wiring 56a electrically connected to the upper electrode 40 of the ferroelectric capacitor 42 and the conductor plug 54a, and the lower electrode 36 of the ferroelectric capacitor 42 are electrically connected.
  • the barrier films 44, 46, and 58 are used as barrier films for preventing the diffusion of hydrogen and moisture, and the ferroelectric capacitors 42 and the ferroelectric capacitors 42 are formed.
  • the capacitor 42 can be further reliably prevented from reaching the ferroelectric film 38. As a result, it is possible to more reliably prevent deterioration of the electrical characteristics of the ferroelectric capacitor 42 due to hydrogen and water, and to further greatly improve the PTHS characteristics of the semiconductor device having the ferroelectric capacitor. it can.
  • ferroelectric film 38 is not limited to the PZT film, but is any other ferroelectric film. Can be used as appropriate.
  • ferroelectric film 38 Pb La Zr Ti O
  • a 1-X X 1-Y Y 3 film (PLZT film), an SrBi (Ta Nb) O film, a BiTi O film, or the like may be used.
  • the lower electrode 36 is composed of the laminated film of the aluminum oxide film 36a and the Pt film 36b.
  • the material of the conductor film or the like that constitutes the lower electrode 36 is limited to the force and the material. It ’s not something that ’s fixed.
  • Ir film, IrO film, Ru film, RuO film, SrRuO stront
  • the lower electrode 38 may be composed of a (muruthenium oxide) film (SR film) or a Pd film.
  • SR film a (muruthenium oxide) film
  • Pd film a film that is laminated film of the IrO film 40a and the IrO film 40b.
  • upper electrode 40 is composed of Ir film, Ru film, RuO film, SRO film, Pd film
  • the barrier film 62 is formed between the first metal wiring layer 56 and the second metal wiring layer 72, and the second metal wiring is formed.
  • the case where the barrier film 78 is formed between the layer 72 and the third metal wiring layer 88 will be described.
  • the barrier film 62, 78 and the barrier above the third metal wiring layer 88 are described.
  • the case where the film 114 is formed will be described.
  • the case where the barrier film 116 is formed between the ferroelectric capacitor 42 and the first metal wiring layer 56 in addition to the barrier films 62 and 78 will be described.
  • the flat barrier film may be formed by forming at least two layers of the barrier films 62, 78, 114, and 116, and / or three layers of the rear layers 62, 78, 114, and 116. Alternatively, all four layers of 62, 78, 114, and 116 may be formed. Further, more flat barrier films may be formed according to the number of metal wiring layers formed on the semiconductor substrate 10.
  • the noria film is not limited to the aluminum oxide film.
  • a film having a function of preventing diffusion of hydrogen or moisture can be appropriately used as the barrier film.
  • the silicon film for example, a film made of a metal oxide can be used as appropriate.
  • the barrier film made of a metal oxide for example, tantalum oxide or titanium oxide can be used.
  • the barrier film is not limited to a film made of a metal oxide.
  • silicon nitride film (SiN film) or silicon nitride oxide film (SiON film) should be used as the barrier film.
  • a coating type oxide film or an organic film having a hygroscopic property such as a resin film made of polyimide, polyarylene, polyarylene ether, benzocyclobutene, or the like can be used as the barrier film.
  • barrier film made of the same material is used for all the barrier films to be formed.
  • the barrier film made of different materials Can also be used as appropriate.
  • an aluminum oxide film is used as the barrier film 62 formed closest to the ferroelectric capacitor 42 among the flat barrier films 62, 78, 114.
  • a silicon nitride film may be used as the barrier film 78 or the barrier film 114 formed above the noria film 62.
  • a film made of a metal oxide such as an aluminum oxide film or a silicon nitride film As a flat barrier film 114 formed above the third metal wiring layer 88 and having an opening 96b reaching the wiring (bonding pad) 88b, an organic material having a hygroscopic property is used. You can also form a film.
  • the case where the CMP method is used as a method for planarizing the surface of the insulating film constituting the interlayer insulating film has been described as an example. It is not limited to the law.
  • the surface of the insulating film may be flattened by etching.
  • As an etching gas for example, Ar gas can be used.
  • the circuit is formed on the semiconductor substrate 10 by the three metal wiring layers of the first metal wiring layer 56, the second metal wiring layer 72, and the third metal wiring layer 88.
  • the number of metal wiring layers constituting the circuit on the semiconductor substrate 10 is not limited to three. The number of metal wiring layers can be appropriately set according to the design of the circuit configured on the semiconductor substrate 10.
  • a case where a 1T1 C type memory cell having one transistor 24 and one ferroelectric capacitor 42 is formed has been described as an example, but the configuration of the memory cell is It is not limited to 1T1C type.
  • the configuration of the memory cell in addition to the 1T1C type, various configurations such as a 2T2C type having two transistors and two ferroelectric capacitors can be used.
  • a FeRAM structure semiconductor device having a planar type cell In the above-described embodiment, a FeRAM structure semiconductor device having a planar type cell.
  • the scope of the present invention is not limited to this.
  • the present invention can also be applied to a FeRA M structure semiconductor device having a stack type cell and having a gate length set to, for example, 0.18 ⁇ m.
  • FIG. 25 is a cross-sectional view showing the structure of a FeRAM structure semiconductor device having a stack type cell to which the present invention is applied.
  • an element isolation region 212 that defines an element region is formed on a semiconductor substrate 210 made of, for example, silicon.
  • Uenoles 214a and 214b are formed in the semiconductor substrate 210 in which the element isolation region 212 is formed.
  • a gate electrode (gate wiring) 218 is formed on the semiconductor substrate 210 on which the wells 214a and 214b are formed via a gate insulating film 216.
  • the gate electrode 218 has, for example, a polycide structure in which a metal silicide film such as a cobalt silicide film, a nickel silicide film, or a tungsten silicide film is stacked on a polysilicon film in accordance with the gate length of the transistor.
  • a silicon oxide film 219 is formed on the gate electrode 218.
  • Sidewall insulating films 220 are formed on the side walls of the gate electrode 218 and the silicon oxide film 219.
  • a source / drain diffusion layer 222 is formed on both sides of the gate electrode 218 on which the sidewall insulating film 220 is formed.
  • the transistor 224 having the gate electrode 218 and the source / drain diffusion layer 222 is formed.
  • the gate length of the transistor 224 is set to, for example, 0.18 / im.
  • an interlayer insulating film 227 formed by sequentially laminating a SiON film 225 and a silicon oxide film 226 is formed on the semiconductor substrate 210 on which the transistor 224 is formed.
  • the surface of the interlayer insulating film 227 is planarized.
  • a barrier film 228 made of, for example, an aluminum oxide film is formed on the interlayer insulating film 227.
  • Contact barriers 230a and 230b force S reaching the source / drain diffusion layer 222 are formed in the barrier film 228 and the interlayer insulating film 227, and are reduced.
  • Barrier methanol films (not shown) formed by sequentially laminating Ti films and TiN films are formed in the contact holes 230a and 230b.
  • Conductor plugs 232a and 232b made of tungsten are buried in the contact holes 230a and 230b in which the barrier metal film is formed.
  • an Ir film 234 electrically connected to the conductor plug 232a is formed on the barrier film 228, an Ir film 234 electrically connected to the conductor plug 232a is formed.
  • a ferroelectric film 238 of the ferroelectric capacitor 242 is formed on the lower electrode 236.
  • the upper electrode 240 of the ferroelectric capacitor 242 is formed.
  • the upper electrode 240, the ferroelectric film 238, the lower electrode 236, and the Ir film 234 that are laminated are patterned together by etching and have substantially the same planar shape.
  • a ferroelectric capacitor 242 composed of the lower electrode 236, the ferroelectric film 238, and the upper electrode 240 is formed.
  • the lower electrode 236 of the ferroelectric capacitor 242 is electrically connected to the conductor plug 232a via the Ir film 234.
  • a SiON film 244 having a film thickness comparable to or thinner than the Ir film 234 is formed on the region of the interlayer insulating film 227 where the Ir film 234 is not formed.
  • a silicon oxide film may be formed on the region of the interlayer insulating film 227 where the Ir film 234 is not formed.
  • a barrier film 246 having a function of preventing the diffusion of hydrogen and moisture is formed on the ferroelectric capacitor 242 and the SiON film 244.
  • a barrier film 246 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • a silicon oxide film 248 is formed on the barrier film 246, and the strong dielectric capacitor 242 is embedded by the silicon oxide film 248.
  • the surface of the silicon oxide film 248 is planarized.
  • a flat barrier film 250 having a function of preventing the diffusion of hydrogen and moisture is formed on the planarized silicon oxide film 248, a flat barrier film 250 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • the nore film 250 for example, an anolymium oxide film is used.
  • a silicon oxide film 252 is formed on the barrier film 250.
  • An interlayer insulating film 253 is constituted by the con oxide film 252.
  • a contact hole 254a reaching the upper electrode 240 of the ferroelectric capacitor 242 is formed in the silicon oxide film 252, the barrier film 250, the silicon oxide film 248, and the barrier film 246.
  • a contact hole 254b reaching the conductor plug 232b is formed in the silicon oxide film 252, the barrier film 250, the silicon oxide film 248, the noria film 246, and the SiON film 244.
  • a barrier metal film (not shown) formed by sequentially stacking a Ti film and a TiN film is formed. As a barrier metal film, without forming a Ti film
  • a barrier metal film made of a TiN film may be formed.
  • Conductive plugs 256a and 256b made of tungsten are respectively carried in the contact holes 254a and 254b in which the barrier metal film is formed.
  • a wiring 258a electrically connected to the conductor plug 256a and a wiring 258b electrically connected to the conductor plug 256b are formed.
  • a silicon oxide film 260 is formed on the silicon oxide film 252 on which the wirings 258a and 258b are formed, and the self-insulating lines 258a and 258b are applied by the silicon oxide film 260.
  • the surface of the silicon oxide film 260 is flattened.
  • a flat barrier film 262 having a function of preventing the diffusion of hydrogen and moisture is formed on the flattened silicon oxide film 260.
  • the noria film 262 for example, an anolymium oxide film is used.
  • a silicon oxide film 264 is formed on the barrier film 262.
  • the interlayer insulating film 265 is constituted by the silicon oxide film 260, the silicon rear film 262, and the silicon oxide film 264.
  • a contact hole 268 reaching the wiring 258b is formed in the silicon oxide film 264, the barrier film 262, and the silicon oxide film 260.
  • a barrier metal film (not shown) is formed by sequentially stacking a Ti film and a TiN film.
  • a conductor plug 270 made of tungsten is loaded in the contact hole 268 in which the barrier metal film is formed.
  • a wiring 272 electrically connected to the conductor plug 268 is formed on the silicon oxide film 264.
  • a silicon oxide film 274 is formed on the silicon oxide film 264 on which the wiring 272 is formed, and the wiring 272 is embedded by the silicon oxide film 274.
  • the surface of the silicon oxide film 274 is flattened.
  • a flat barrier film 276 having a function of preventing the diffusion of hydrogen and moisture is formed on the planarized silicon oxide film 274.
  • a flat barrier film 276 having a function of preventing the diffusion of hydrogen and moisture is formed.
  • a silicon oxide film 278 is formed on the barrier film 276.
  • the flat barrier films 250, 262, and 276 that prevent the diffusion of hydrogen and moisture are formed as in the above-described embodiment.
  • the flat barrier film for preventing the diffusion of hydrogen and moisture is sufficient if at least two layers are formed, and all three layers of the rear films 250, 262, and 276 are formed. It does not have to be. Further, if necessary, a larger number of flat rear films may be formed.
  • the semiconductor device and the manufacturing method thereof according to the present invention are useful for improving the reliability of a semiconductor device having a ferroelectric capacitor.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)

Abstract

Un dispositif semi-conducteur comprenant un condenseur ferro-électrique (42) formé sur un substrat semi-conducteur (10) et ayant une électrode inférieure (36), une pellicule ferro-électrique (38) formée sur l'électrode inférieure (36) et une électrode supérieure (40) formée sur la pellicule ferro-électrique (38), une pellicule d'oxyde de silicium (60) formée sur le substrat semi-conducteur (10) et le condenseur ferro-électrique (42) et ayant une surface planxx, une pellicule de barrière planaire (62) formée sur la pellicule d'oxyde de silicium (60) via une pellicule d'oxyde de silicium (61) et empêchant la diffusion d'hydrogène ou d'humidité, une pellicule d'oxyde de silicium (74) formé sur une pellicule barrière (62) ayant une surface planxx et une pellicule barrière xx (78) formée sur la pellicule d'oxyde de silicium (74) via une pellicule d'oxyde de silicium (76) et empêchant la diffusion d'hydrogène ou d'humidité.
PCT/JP2004/009429 2004-07-02 2004-07-02 Dispositif semi-conducteur et son processus de fabrication WO2006003707A1 (fr)

Priority Applications (6)

Application Number Priority Date Filing Date Title
PCT/JP2004/009429 WO2006003707A1 (fr) 2004-07-02 2004-07-02 Dispositif semi-conducteur et son processus de fabrication
PCT/JP2005/011955 WO2006003940A1 (fr) 2004-07-02 2005-06-29 Dispositif semi-conducteur et méthode de fabrication
JP2006528750A JP5202846B2 (ja) 2004-07-02 2005-06-29 半導体装置及びその製造方法
CN2005800266413A CN1993828B (zh) 2004-07-02 2005-06-29 半导体装置
KR1020067027308A KR100985793B1 (ko) 2004-07-02 2005-06-29 반도체 장치 및 그 제조 방법
US11/647,198 US8552484B2 (en) 2004-07-02 2006-12-29 Semiconductor device and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2004/009429 WO2006003707A1 (fr) 2004-07-02 2004-07-02 Dispositif semi-conducteur et son processus de fabrication

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PCT/JP2005/011955 Continuation WO2006003940A1 (fr) 2004-07-02 2005-06-29 Dispositif semi-conducteur et méthode de fabrication
US11/647,198 Continuation US8552484B2 (en) 2004-07-02 2006-12-29 Semiconductor device and method for fabricating the same

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JP4997939B2 (ja) * 2006-11-29 2012-08-15 富士通セミコンダクター株式会社 半導体装置及びその製造方法

Citations (4)

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Publication number Priority date Publication date Assignee Title
JP2001036026A (ja) * 1999-05-14 2001-02-09 Toshiba Corp 半導体装置及びその製造方法
JP2001060669A (ja) * 1999-06-17 2001-03-06 Fujitsu Ltd 半導体装置及びその製造方法
JP2002110937A (ja) * 2000-10-05 2002-04-12 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP2002110932A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置及びその製造方法

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JP3114710B2 (ja) * 1998-11-30 2000-12-04 日本電気株式会社 強誘電体メモリ及びその製造方法
JP2001015696A (ja) * 1999-06-29 2001-01-19 Nec Corp 水素バリヤ層及び半導体装置
JP3466174B2 (ja) * 2001-09-27 2003-11-10 沖電気工業株式会社 半導体装置およびその製造方法
JP2003197878A (ja) * 2001-10-15 2003-07-11 Hitachi Ltd メモリ半導体装置およびその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001036026A (ja) * 1999-05-14 2001-02-09 Toshiba Corp 半導体装置及びその製造方法
JP2001060669A (ja) * 1999-06-17 2001-03-06 Fujitsu Ltd 半導体装置及びその製造方法
JP2002110932A (ja) * 2000-09-28 2002-04-12 Toshiba Corp 半導体装置及びその製造方法
JP2002110937A (ja) * 2000-10-05 2002-04-12 Hitachi Ltd 半導体集積回路装置およびその製造方法

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KR100985793B1 (ko) 2010-10-06
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CN1993828B (zh) 2012-02-08
CN1993828A (zh) 2007-07-04

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