WO2005107203A1 - 自動周波数制御回路および自動周波数制御方法 - Google Patents
自動周波数制御回路および自動周波数制御方法 Download PDFInfo
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- WO2005107203A1 WO2005107203A1 PCT/JP2004/006182 JP2004006182W WO2005107203A1 WO 2005107203 A1 WO2005107203 A1 WO 2005107203A1 JP 2004006182 W JP2004006182 W JP 2004006182W WO 2005107203 A1 WO2005107203 A1 WO 2005107203A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
- H04L27/22—Demodulator circuits; Receiver circuits
- H04L27/227—Demodulator circuits; Receiver circuits using coherent demodulation
- H04L27/2275—Demodulator circuits; Receiver circuits using coherent demodulation wherein the carrier recovery circuit uses the received modulated signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0024—Carrier regulation at the receiver end
- H04L2027/0026—Correction of carrier offset
- H04L2027/0028—Correction of carrier offset at passband only
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0044—Control loops for carrier regulation
- H04L2027/0046—Open loops
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
- H04L2027/0083—Signalling arrangements
- H04L2027/0089—In-band signals
Definitions
- the present invention relates to a PSK modulation signal of a digital wireless communication system using a PSK (Phase Shift Keying) modulation method, and more particularly to an automatic frequency control circuit and an automatic frequency control method for correcting a frequency deviation when the PSK modulation signal is received.
- PSK Phase Shift Keying
- Non-Patent Document 1 discloses a differential detection demodulator using the PSK modulation method.
- the automatic frequency control circuit described in this document performs frequency deviation correction on a received signal obtained by performing PSK modulation on an arbitrary data sequence.
- FIG. 1 is a block diagram showing a configuration of a conventional automatic frequency control circuit disclosed in Non-Patent Document 1 described above.
- the automatic frequency control circuit comprises an arc tangent means 90, a delay unit 91, a subtractor 92, an adder 93, a decision unit 94, a modulation component removing means 95, and an averaging means 96. It is configured.
- the output of the receiving antenna 11-1 is input to the detection means 12-1.
- the detection means 12-1 is composed of a local oscillator, a mixer, a low-pass filter, and the like.
- the output of the detection means 12-1 is input to the A / D converter il 3-1.
- An output line extending from the AZD converter 13-1 is connected to the arctangent means 90 of the automatic frequency control circuit.
- the output line extending from the arctangent means 90 branches into two branches, one of which is connected to the delay unit 91.
- the other output line extending from the arctangent means 9 ° and the output line of the delay device 91 are connected to one subtractor 92.
- the output line extending from the subtractor 92 is connected to one of the two input ports of the adder 93. It is connected to the.
- the output line extending from the adder 93 branches into two branches, one of which is connected to the decision unit 94, and the other of which is connected to the modulation component removing means 95.
- the output line extending from the decision unit 94 is branched into two, one of which is directed to the output port and the other is turned back and connected to the modulation component removing means 95.
- the output line of the modulation component removing means 95 is connected to the averaging means 96.
- the output line of the averaging means 96 is connected to the adder 93.
- the PSK signal received by the receiving antenna 111 is quasi-synchronously detected by the detecting means 12-1, and is output as a received baseband complex signal.
- the A / D converter 13-1 performs AZD conversion of the quasi-coherently detected received baseband complex signal and outputs received baseband complex data.
- the automatic frequency control circuit inputs the received baseband complex data.
- the received baseband complex data input to the automatic frequency control circuit is first input to arctangent means 90.
- the arctangent means 90 finds and outputs baseband phase data, which is the argument of the received baseband complex data.
- the delay unit 91 outputs the baseband phase data with a time delay of one symbol period.
- the subtracter 92 subtracts the one-symbol period time-delayed baseband phase data output from the delay unit 91 from the non-delayed baseband phase data output from the arctangent means 90 and outputs the result.
- the adder 93 adds the subtraction result output from the subtractor 92 and angle information for correcting a frequency deviation output from the averaging means 96 described later, and outputs the result.
- the determiner 94 outputs demodulated data obtained by determining the angle information output from the adder 93.
- the modulation component removing means 95 outputs frequency error correction information obtained by subtracting the angle information output from the adder 93 from the ideal angle for the demodulated data output from the determiner 94.
- the frequency error correction information is obtained by expressing the frequency deviation of the difference between the actual frequency deviation and the frequency deviation currently estimated by the automatic frequency control circuit in phase. It is.
- the averaging means 96 averages and integrates the frequency error correction information output from the modulation component removing means 95. This integration result is output to the adding means 93 as angle information for correcting the frequency deviation.
- the conventional automatic frequency control circuit performs the feedback control so that the frequency error correction information output from the modulation component removing means 95 becomes “0”, thereby reducing the currently estimated frequency deviation. Since it approaches the actual frequency deviation, it is possible to perform frequency deviation correction on a signal obtained by PSK-modulating an arbitrary data sequence.
- the conventional automatic frequency control circuit performs the correction operation on the assumption that the received signal is an arbitrary data sequence that is PSK-modulated. Therefore, in an environment where the SN ratio of the received signal is poor, a decision error occurs in the decision unit 94. Even when a preamble signal having a known pattern is received, it is difficult to perform highly accurate frequency deviation correction in a short time.
- the conventional automatic frequency control circuit requires the assumption that bit timing synchronization has been established.If bit timing synchronization is not established, the frequency deviation estimation characteristics may be affected by intersymbol interference and the like. There is also a problem of deterioration.
- the present invention has been made to solve the above-described problems, and an object of the present invention is to provide an automatic frequency control circuit capable of performing high-accuracy frequency deviation correction in a short time by using a known pattern of a brimble signal. Aim.
- the present invention provides an automatic frequency control circuit that can perform high-accuracy frequency deviation correction in a short time even when bit timing synchronization is not established, by using the periodicity of a preamble signal that is a known pattern.
- An object is to provide an automatic frequency control method. 2
- a two-symbol period signal portion composed of at least a two-symbol period signal is a data sequence arranged at a predetermined position, and performs a frequency deviation correction of a PSK-modulated reception signal.
- the frequency control circuit performs a preprocessing unit that calculates the amount of phase rotation between (2 XM) symbol periods (M is a natural number) from the received signal, and the (2 XM) symbol period from the amount of phase rotation between (2 XM) symbol periods.
- (2 XM) Offset elimination means for extracting the phase rotation amount during the symbol period by subtracting the phase rotation amount due to the modulation component of the period, and (2 XM) )
- a correction data generation unit that generates correction data that has been subjected to phase correction processing for canceling phase rotation based on the amount of phase rotation between symbol periods. . Therefore, for a received signal having a two-symbol periodic signal part consisting of a two-symbol periodic signal at a predetermined position, bit timing synchronization is established by using the periodicity of the two-symbol periodic signal part, which is a known pattern. Even if not performed, it is possible to perform highly accurate frequency deviation correction in a short time.
- a frequency deviation correction of a PSK-modulated reception signal is performed by forming a data sequence in which a two-symbol period signal portion including at least a two-symbol period signal is arranged at a predetermined position.
- a preprocessing procedure is performed to determine the amount of phase rotation between (2 XM) symbol periods (M is a natural number) from the received signal, and then the (2 XM) symbol period (M is Performs an offset removal procedure to subtract the amount of phase rotation due to the modulation component between (2 XM) symbol periods from the amount of phase rotation between (natural numbers), and the phase rotation between (2 XM) symbol periods due to the frequency deviation between the transmitter and the receiver.
- a correction data generation procedure is performed to generate correction data that has been subjected to phase correction processing to cancel the phase rotation.
- FIG. 1 is a block diagram showing a configuration of a conventional automatic frequency control circuit
- FIG. 2 is a block diagram showing a configuration of an example of an automatic frequency control circuit according to Embodiment 1 of the present invention
- FIG. FIG. 4 is a block diagram showing a configuration of a 2M symbol phase rotation amount calculating means
- FIG. 4 is a table showing an example of an output signal of the 2M symbol phase rotation amount calculating means
- FIG. 6 is a block diagram showing another example of the frequency control circuit
- FIG. 6 is a block diagram showing still another example of the automatic frequency control circuit of Embodiment 1
- FIG. 7 is an automatic frequency control circuit of Embodiment 1.
- FIG. 8 is a timing chart showing an example of the operation of the control circuit.
- FIG. 8 is a timing chart showing an example of the operation of the control circuit.
- FIG. 8 is a block diagram showing an example of the configuration of an automatic frequency control circuit according to the second embodiment having N receiving antennas. Is an implementation with N receive antennas
- FIG. 10 is a block diagram illustrating another configuration of the automatic frequency control circuit according to Embodiment 2
- FIG. 10 is a block diagram illustrating the configuration of the automatic frequency control circuit according to Embodiment 3 having one receiving antenna.
- FIG. 11 is an operation timing chart of the integrator
- FIG. 12 is an example of the configuration of an automatic frequency control circuit according to Embodiment 4 having N receiving antennas
- FIG. FIG. 14 is a block diagram illustrating a configuration of an example of an automatic frequency control circuit according to a fifth embodiment.
- FIG. 14 is a block diagram illustrating a configuration of another example of an automatic frequency control circuit according to the fifth embodiment.
- Embodiment 1 of the present invention data including a preamble signal having a period of 2 symbols is used.
- An automatic frequency control circuit and an automatic frequency control method in which a signal receives a PSK-modulated signal with one receiving antenna and corrects the frequency deviation will be described.
- FIG. 2 is a block diagram showing a configuration of an example of the automatic frequency control circuit according to the first embodiment of the present invention.
- the automatic frequency control circuit includes a pre-processing unit, an offset removing unit 17 and a correction data generation unit.
- the pre-processing unit includes a complex multiplication type one-symbol differential detection means 14-11, an arc tangent means 15 and a 2 ⁇ symbol phase rotation amount calculation means 16.
- the correction data generation unit includes a dividing means 18, an integrator 20, and a frequency deviation correcting means 20-1.
- the processes performed by the pre-processing unit, the offset removing unit 17 and the correction data generating unit are respectively performed by the pre-processing unit, the offset removing unit 17 and the correction data of the automatic frequency control method according to the embodiment of the present invention. And a generator.
- the output of the receiving antenna 111 is input to the detecting means 122-1.
- the detection means 12-1 is composed of a local oscillator, a mixer, a low-pass filter, and the like. Further, the output of the detection means 12-1 is input to the A / D converter 13-1.
- An output line extending from the A / D converter 13-1 is input to the automatic frequency control circuit. One of them is connected to a complex multiplying one-symbol differential detection means 14-11.
- the output line extending from the complex multiplication type one-symbol differential detection means 14-11 is connected to the arc tangent means 15.
- the output line extending from the arctangent means 15 is connected to the 2 ⁇ symbol phase rotation amount calculation means. 2 ⁇
- the output line extending from the symbol phase rotation amount calculation means is connected to the offset removal means 17.
- the output line of the offset removing means 17 is connected to the dividing means 18, and the output line of the dividing means 18 is connected to the averaging means 19.
- the output line of the averaging means 19 is connected to the integrator 20.
- the output line extending from the integrator 20 is connected to the frequency deviation correcting means 20-1 together with the other output line extending from the A / D converter 13-1.
- the output line of the frequency deviation correcting means 20-1 extends to an output
- FIG. 3 is a block diagram showing the configuration of the 2 ⁇ symbol phase rotation amount calculating means 16. It is.
- the 2M symbol phase rotation amount calculation means 16 is composed of (2M ⁇ 1) delay units and (2M ⁇ 1) adders.
- the output line extending from the arctangent means 15 branches into two branches, one of which is connected to the first delay unit 41_1.
- the output line extending from the first delay unit 41-1 branches into two branches, one of which is connected to the first adder 41-11 together with the other output line extending from the arctangent means 15. I have.
- the other output line extending from the first delay device 41-11 is connected to the second delay device 41-12.
- the output line extending from the second delay unit 41-2 branches into two branches, one of which is connected to the second adder 41-2 together with the output line of the first adder 41-1. Have been.
- the other output line extending from the second delay device 41-2 is connected to the third delay device 41-3, and the output line extending from the third delay device 41-13 is forked.
- One is connected to the third adder 4 1 1 3 together with the output line of the second adder 41-2, and this is repeated until finally the (2M-1) th delay
- the output line of adder 41 (2M-1) is connected to the (2M-1) th adder 41-1 (2M-1), and the output line of adder 41-1 (2M-1) is 2M symbol phase.
- the output of the rotation amount calculation means 16 is provided.
- FIG. 4 is a chart showing an example of an output signal of the 2M symbol phase rotation amount calculating means 16.
- the vertical axis indicates the phase rotation amount [degree] between two symbol periods, and the horizontal axis indicates time [symbol].
- FIG. 5 is a block diagram showing another example of the automatic frequency control circuit according to the first embodiment.
- the automatic frequency control circuit includes a pre-processing unit including a complex multiplication type 2M symbol delay detection unit 43_1, an averaging unit 44, and an arc tangent unit 15, an offset removal unit 17, a division unit 18, and an integration unit. And a correction data generation unit configured with a frequency deviation correction means 20-1.
- the steps in which the pre-processing unit, the offset removing unit 17 and the correction data generating unit are executed are respectively the pre-processing procedure of the automatic frequency control method according to the first embodiment of the present invention,
- the offset removal procedure and the correction data generation procedure are configured.
- An output line extending from the AZD converter 13-1 is input to the automatic frequency control circuit. One of them is connected to the complex multiplying 2 M symbol differential detection means 43-1. The output line extending from the complex multiplication type 2 M symbol differential detection means 43-1 is connected to the averaging means 44. The output line extending from the averaging means 44 is connected to the offset removing means 17.
- the output line of the offset removing means 17 is connected to the dividing means 18.
- the output line of the dividing means 18 is connected to the averaging means 19, and the output line of the averaging means 19 is connected to the integrator 20.
- the output line extending from the integrator 20 is connected to the frequency deviation correcting means 20-1 together with the other output line extending from the A / D converter 13-1.
- the output line of the frequency deviation correcting means 20-1 extends to an output port (not shown).
- FIG. 6 is a block diagram showing still another example of the automatic frequency control circuit according to the first embodiment.
- an output line extending from the A / D converter 13-1 is connected to the arc tangent means 15 of the automatic frequency control circuit.
- the output line extending from the arctangent means 15 branches into two branches, one of which is connected to the 2M symbol delay unit 45.
- the other output line extending from the arctangent means 15 and the output line of the 2M symbol delay unit 45 are connected to one subtractor 46.
- the output line extending from the subtractor 46 is connected to the offset removing means 17.
- Other configurations are the same as those of the automatic frequency control circuit shown in FIGS. 1 and 5.
- FIG. 7 is a timing chart showing an example of the operation of the automatic frequency control circuit according to the first embodiment.
- the horizontal axis shows the passage of time.
- a PSK-modulated received signal in which a two-symbol periodic signal portion consisting of a two-symbol periodic signal is a data sequence arranged at the head position is targeted. ing.
- the frequency deviation is estimated when the preamble signal is received, and when the preamble signal ends, the frequency deviation estimated when the preamble signal is received is held and the frequency deviation is corrected.
- the automatic frequency control circuit receives a PSK signal at receiving antenna 11-11, performs quasi-synchronous detection at detecting means 12-1, and outputs a received baseband complex signal.
- the A / D converter 13-1 performs A / D conversion of the quasi-synchronously detected received baseband complex signal and outputs received baseband complex data.
- the complex multiplication type one-symbol differential detection means 14-1 divides the reception baseband complex data output from the A / D converter 13-1 and the one-symbol period time before Performs complex multiplication of the complex conjugate of the received baseband complex data and outputs the complex multiplication result.
- i is the time in symbol period units
- ⁇ i is the argument of the received baseband complex data at time ij i
- j Is the imaginary unit
- Li + jLq is the complex multiplication result which is the output of the complex multiplication type one-symbol differential detection means 14-1
- * indicates the complex conjugate operation.
- the argument ⁇ 6 ⁇ ⁇ of the complex value Li + jLq which is the result of the complex multiplication, indicates the amount of phase rotation during one symbol period.
- the 2M symbol phase rotation amount calculating means 16 calculates the phase rotation amount between one symbol period output from the arctangent means 15 (2 XM) the phase rotation amount between symbol periods ⁇ 0 3 ⁇ 4i ( - ⁇ i_ 2M )) is calculated and output.
- M is a value of a natural number.
- phase rotation amount ⁇ 6 3 ⁇ 4i [degree] between (2XM) symbol periods when a preamble signal of two symbol periods is received in consideration of the frequency deviation of the transmitting / receiving device is expressed by the following equation (2). It has a value independent of time i.
- S [degree] is a phase rotation amount due to a modulation component between two symbol periods of the preamble pattern, and is a known value.
- the offset removing unit 17 calculates the phase rotation by the modulation component between the (2XM) symbol periods from the phase rotation amount ⁇ [degree] output from the (2 XM) symbol periods output from the 2M symbol phase rotation amount calculating unit 16. by subtracting the amount MX S, which depends on the frequency deviation between transmission and reception apparatus (2xm) phase rotation amount between the symbol period (2 XMX360 X Af / f s ) by extracting the [degree] output.
- the subtraction result (2 ⁇ 3 ⁇ Af / f s) [degree] is the modulo 360 are [degree], with a value of -180 [degree] ⁇ 180 [degree] .
- Dividing means 18, divided by by the frequency deviation ⁇ between transmitting and receiving apparatus is output from the offset removing unit 17 phase rotation amount between (2 ⁇ ) symbol periods (2 ⁇ 360 ⁇ Af / f s) [degree] of (2 XM) By doing so, the frequency deviation between the transmitting and receiving The phase rotation amount during one symbol period is calculated and output.
- the averaging means 19 improves the SN ratio by averaging the phase rotation amount for one symbol period due to the frequency deviation between the transmitting and receiving devices output from the dividing means 18, and outputs the result.
- the integrator 20 integrates and outputs the phase rotation amount for one symbol period due to the averaged frequency deviation between the transmitting and receiving devices output from the averaging means 19.
- the frequency deviation correction means 2 1-1 is provided between the transmitting and receiving devices based on the integration result output from the integrator 20 with respect to the received spanned complex data output from the A / D converter 13-1. Performs a phase correction process to cancel the phase rotation caused by the frequency deviation A f of, and outputs the complex data after the phase correction process.
- a two-symbol period signal part consisting of a two-symbol period signal consists of a data sequence arranged at a predetermined position.
- the (2 XM) The phase rotation amount due to the modulation component between (2 XM) symbol periods is subtracted from the phase rotation amount between symbol periods (M is a natural number), and the phase deviation between (2 XM) symbol periods due to the frequency deviation between the transmitting and receiving devices Since it has an offset removing means 17 that extracts and outputs the amount of rotation, the frequency deviation between the transmitting and receiving devices is estimated based on a two-symbol periodic signal part consisting of signals with two symbolic cycles as a known pattern. It is possible to do.
- a complex multiplication 1-symbol delay detection means 144-1 that performs complex multiplication of the reception baseband complex data and a complex conjugate of the reception baseband complex data one symbol cycle time earlier, and a complex multiplication 1-symbol delay detection Means 14 4 1
- the inverse tangent means 15 for calculating the argument of the result of the complex multiplication output from 1 and the argument output from this arc tangent means 15 and the amount of phase rotation during the symbol period (2 ⁇ ⁇ )
- the symbol rotation amount calculating means 16 for calculating the symbol phase rotation amount, the phase rotation amount during the above-mentioned (2 ⁇ ⁇ ) symbol period can be easily calculated.
- the automatic frequency control circuit uses a pre- By using the ampoule signal, the frequency deviation can be performed without estimating the modulation component, and the averaging means 19 can perform the averaging process without loss of signal energy due to erroneous determination of the modulation component. Therefore, highly accurate frequency deviation correction can be performed in a short time.
- phase rotation amount 0 i [degree] between (2 XM) symbol periods output from the 2M symbol phase rotation amount calculating means 16 is a value that does not depend on time, the automatic rotation according to the present embodiment is performed.
- the frequency control circuit can perform highly accurate frequency deviation correction in a short time even when bit timing synchronization is not established.
- the automatic frequency control circuit according to the present embodiment shown in FIG. 2 has a configuration having the averaging means 19 at the subsequent stage of the dividing means 18, but the same applies even if the order of these two processes is changed. Is output.
- a configuration may be employed in which the averaging means 19 performs the averaging processing and then the dividing means 18 performs the division processing.
- a 2M symbol phase rotation amount calculating means 16 is provided with a delay unit 4 1-1 to 4 1-(2M- 1). Is output after a time delay of.
- the declination of the received baseband complex data at time i [symbol] is 0 i [degree]
- the 1-symbol differentially detected phase data output from arctangent means 15 is ⁇ ewCdegree]
- the 2M symbol phase rotation amount calculation means 16 calculates the phase rotation amount ⁇ 03 ⁇ 4i between ( 2XM ) symbol periods. It is possible to do so.
- ⁇ ⁇ ⁇ 1 ( ⁇ + ⁇ ⁇ 1 , ⁇ + ⁇ .. + ⁇ 0 U —
- the automatic frequency control circuit according to the present embodiment can also have a configuration as shown in FIG.
- i is the time in symbol period units
- j is the imaginary unit
- * is the complex conjugate operation
- Li ′ + jLq ′ is the output of the complex multiplying 2M symbol differential detection means 43-1.
- the averaging means 44 averages the complex signal output from the complex multiplying 2M symbol differential detection means 43-1, thereby improving the SN ratio and outputting the signal.
- the arc tangent means 15 outputs the argument of the complex signal averaged by the averaging means 44 and outputs this.
- the reception baseband complex data and the complex number conjugate of the reception baseband complex data before (2 XM) symbol period time are used.
- the averaging process is performed after the complex multiplication type 2 ⁇ symbol differential detection means, but instead, the offset removal means 17 or the division means is used.
- the same effect can be obtained by averaging the phase data output from 18. That is, the averaging process may be performed after the offset removing unit 17 or the dividing unit 18.
- the automatic frequency control circuit according to the present embodiment can also have a configuration as shown in FIG.
- the 2 ⁇ symbol delay unit 45 gives the argument of the received baseband complex data with a time delay of (2 ⁇ ) symbol periods and outputs it.
- the received baseband complex data at time i [symbol] When the deflection angle and 0 i [d egree], the signal output from the 2 M-symbol delay unit 4 5 becomes ⁇ i_ 2M [degree].
- the subtracting means 46 subtracts the signal e i — 2M [degree] output from the 2M symbol delay unit 45 from the argument ⁇ i [degree] of the received baseband complex data, and outputs the result.
- the value output from the subtracting means 46 is ( ⁇ i ⁇ i ⁇ 2M ) [degree].
- the arctangent means 15 for calculating the first argument of the received baseband complex data, and the arctangent means 15 output from the arctangent means 15 The second argument is obtained by giving a time delay of (2 XM) symbol periods to the argument of 1 to obtain a 2M symbol delay means 45, and subtracting the second argument from the first argument (2 XM) subtraction means 46 for calculating the amount of phase rotation between symbol periods.
- 2M symbol delay means 45 and the subtraction means 46 it is possible to calculate the phase rotation amount between (2 XM) symbol periods and to estimate the frequency deviation ⁇ f between the transmitting and receiving apparatuses.
- the same effect as that of the automatic frequency control circuit shown in FIG. 2 can be obtained.
- the automatic frequency control circuit in FIG. 6 has a configuration in which the averaging means 19 is provided after the dividing means 18 in the same manner as the automatic frequency control circuit in FIG. Even if is replaced, the same calculation result is output. That is, a configuration may be employed in which the averaging means 19 performs the averaging processing and then the dividing means 18 performs the division processing.
- the automatic frequency control circuit according to the present embodiment shown in FIGS. 2, 5, and 6 cannot perform frequency deviation estimation when transmission data is random data. .
- the frequency deviation estimating operation of the received signal to which the preamble signal is added at the head is performed using the automatic frequency control circuit according to the present embodiment only when the preamble signal is received.
- the frequency deviation value estimated at the time of receiving the preamble signal is held and the frequency deviation correction operation is performed. Synchronous state can be maintained.
- a switching signal (external signal) is externally input to the averaging means 19 in FIGS. 2 and 6 and the dividing means 18 in FIG.
- the processing operation is different between the averaging means 19 and the dividing means 18.
- the averaging means 19 uses the switching signal to perform two operations: an operation of averaging the output from the dividing means 18 and an operation of holding the output at a predetermined value and continuing to output the value thereafter. It is designed to switch between operations.
- the dividing means 18 is configured to switch between two operations: an operation of dividing the output from the offset removing means 17 and an operation of keeping the output at a predetermined value and continuing to output the value thereafter. I have. As a result, switching between the frequency deviation estimating operation and the frequency deviation correcting operation performed while holding the estimated frequency deviation value is performed.
- the switching of the operation of the automatic frequency control circuit (frequency deviation estimation) and the operation of the estimated frequency deviation holding (frequency deviation correction) is performed by inputting a switching signal and receiving the received signal. This is performed at the moment when the signal switches from preamble signal to random data.
- the timing of this switching may be any timing.
- the operation may be switched without waiting for random data.
- the present embodiment is directed to a received signal to which a preamble signal is added at the head, a two-symbol period signal portion including a two-symbol period signal does not necessarily have to be at the head of the data sequence. The present application can be applied if it is arranged at a predetermined position.
- a signal including a preamble signal having a two-symbol period is subjected to PSK modulation with two or more reception antennas to correct a frequency deviation.
- An automatic frequency control circuit that performs the following will be described.
- the automatic frequency control circuit according to the second embodiment is obtained by adding a circuit for synthesizing signals received by a plurality of antennas to the automatic frequency control circuit according to the first embodiment.
- FIG. 8 is a block diagram showing a configuration of an example of an automatic frequency control circuit having N (N is a natural number of 2 or more) receiving antennas.
- the automatic frequency control circuit is composed of N complex multiplying one-symbol differential detection means 14-1 to 14-N, an adder 23, an arc tangent means 15, and a 2M symbol phase rotation amount. It is composed of a pre-processing unit composed of calculating means 16, offset removing means 17, dividing means 18, integrator 20, and N frequency deviation correcting means 21_1_1 to 21-N. And a correction data generating unit to be used.
- N receiving antennas 111-1-111-N are respectively input to N detecting means 12-1-1-1-2-N.
- the output of ⁇ 1 2-N is input to N A / D converters 13-1-13-N.
- the output line of the offset removing means 17 is connected to the dividing means 18, the output line of the dividing means 18 is connected to the averaging means 19, and the output line of the averaging means 19 is connected to an integrator. Connected to 20.
- the output line extending from the integrator 20 is branched into N lines, each of which has N AZD converters 13 3::! 1 to 3—N frequency deviation correction means 2 1— 1 to 2 1— along with the other output line extending from N Connected to N.
- N frequency deviation correcting means 21-1-21 One N output lines extend to an output port (not shown).
- FIG. 9 is a block diagram showing another configuration of the automatic frequency control circuit having N receiving antennas.
- the automatic frequency control circuit comprises N complex multiplying 2M symbol differential detection means 43-1 to 43_N, calo calculator 24, averaging means 44, arctangent means 15, offset removal means 17, Division means 18, integrator 20, and ⁇ N frequency deviation correction means 20— :! ⁇ 20—N.
- the outputs of the N receiving antennas 111-1-11-1N are input to N detecting means 12-1 to 12-N, respectively. Further, the outputs of the N detection means 12-1 to 12-N are input to N A / D converters 13-1 to 13-N.
- Output lines extending from the N AZD converters 13-1 to 13-N are input to the automatic frequency control circuit. One of them is connected to N complex multiplying 2M symbol differential detection means 43-1-43-N. All the output lines extending from the N complex multiplying 2M symbol differential detection means 43_ ;! to 43-N are connected to the adder 23. The output line of the adder 23 is connected to the averaging means 44. The output line extending from the averaging means 44 is connected to the offset removing means 17.
- the output line of the offset removing means 17 is connected to the dividing means 18, the output line of the dividing means 18 is connected to the averaging means 19, and the output line of the averaging means 19 is connected to the integrator 20. . Then, the output line extending from the integrator 20 branches into N lines, each of which has N frequency deviation corrections together with the other output line extending from the N A / D converters 13_1 to 13—N. Means 21-1 to 21-N are connected. The output lines of the N frequency deviation correctors 21-1 to 21-N extend to output ports (not shown).
- the automatic frequency control circuit according to the present embodiment receives the PSK signals at the receiving antennas 11-1 to 11-1N, respectively, and 06182
- 1 2—N Performs quasi-synchronous detection on the signals received by the corresponding receiving antennas 11 1—1 to 11 1N to output a received baseband complex signal.
- the local oscillator used for frequency conversion in the detection means 12_1 to 12-N is common to all branches.
- the A / D converters 13-1 to 13 -N perform AZD conversion of the corresponding quasi-synchronously detected received baseband complex signals and output received baseband complex data.
- Complex multiplication type 1-symbol differential detection means 14 1 1 to 14 1 N are the received baseband complex data output from the corresponding AZD converters 13-1 to 13-N, respectively, and the corresponding 1 symbol. Performs complex multiplication with the complex conjugate of the received baseband complex data before the cycle time and outputs the result of the complex multiplication.
- the common local oscillator is used for the detection means 1 2-;! To 1 2-N, the frequency deviation between the transmitting and receiving devices is the same in all branches.
- the addition means 23 is a complex multiplication type one-symbol differential detection means 14! 1 14 1 Add all N complex multiplication results output from N.
- the pre-processing unit includes N antennas 1 1 1 1 1 to 1 1 N Complex multiplication of the received baseband complex data output from the respective antennas and the conjugate complex numbers of the received baseband complex data one symbol cycle time earlier output from the corresponding antennas 111-1-111 Complex multiplication results output from N complex multiplying 1-symbol differential detection means 141-1-1-14 N and N complex multiplying 1-symbol differential detection means 141-1-14-1N ,
- An arc tangent means 15 for calculating the argument of the complex multiplication result output from the addition means 23, 2 M symbol phase rotation amount calculating means 16 for calculating the amount of phase rotation between (2 XM) symbol periods from the argument output from the arc tangent means 15.
- the argument of the complex signal output from the addition means 23 is determined by the embodiment shown in FIG.
- Complex multiplication type 1 1-symbol delay detection means 1 4 1 1 1 Similarly to the argument of the complex signal output from 1, the phase rotation amount due to the modulation component for 1 symbol period and the frequency between the transmitter and receiver for 1 symbol period It has the value of the sum with the phase rotation amount due to the deviation.
- the stage subsequent to the adding means 23 has the same configuration as that of the automatic frequency control circuit according to the first embodiment shown in FIG. 2 so that signals received by two or more antennas can be used.
- Frequency deviation estimation can be performed, and frequency correction means 2 1— :! Up to 21_N can be used to correct the frequency deviation.
- the automatic frequency control circuit according to the present embodiment shown in FIG. 8 is similar to the automatic frequency control circuit according to the first embodiment shown in FIG. Although the configuration having 19 is adopted, the same operation result is output even if the order of these processes is changed. In other words, the configuration may be such that the averaging unit 19 performs the averaging process and then the division unit 18 performs the division process.
- the automatic frequency control circuit according to the present embodiment can also have a configuration as shown in FIG.
- FIG. 9 is a block diagram showing another example of the automatic frequency control circuit according to the second embodiment.
- the complex multiplication type 2 M symbol differential detection means 43-1 to 43-N calculates and outputs a complex signal having a phase rotation amount between (2 XM) symbol periods, respectively.
- a common local oscillator is used for detection means 12-1 to 12-N, transmission and reception are performed.
- the frequency deviation between the devices is the same for all branches.
- the addition means 24 is a complex multiplication type 2 M symbol differential detection means 4 3. 4 4 Add all complex signals output from 3 ⁇ N and output.
- the pre-processing unit performs the reception baseband complex output from the N antennas each receiving the PSK-modulated signal of the 2-symbol period signal.
- N complex multiplying type 2M symbol differential detection means 4 3 which performs complex multiplication of the data and the conjugate complex number of the received baseband complex data before (2 XM) symbol period output from the corresponding antenna.
- the argument of the complex signal output from the addition means 24 is determined by the embodiment shown in FIG. Complex multiplication type of 1 2 M symbol differential detection means 4 3-1
- the stage subsequent to the adding means 24 has the same configuration as the automatic frequency control circuit according to the first embodiment shown in FIG. 5, so that even if signals received by two or more antennas are used, Deviation estimation can be performed, and frequency correction means 2 1 1 1 to 21 1-N frequency deviation; It is possible to do a positive.
- the averaging process is performed after the adding means 24. Instead, the phase data output from the offset removing means 17 or the dividing means 18 The same effect can be obtained by averaging. In other words, the averaging process is performed after the offset removing unit 17 or the dividing unit 18. It may be.
- the automatic frequency control circuit according to the present embodiment shown in FIGS. 8 and 9 cannot perform frequency deviation estimation when transmission data is random data.
- the frequency deviation is estimated using the automatic frequency control circuit according to the present embodiment.
- the frequency deviation corrected during reception of the preamble signal is held and the frequency deviation is corrected. It is possible to keep the synchronization state.
- the automatic frequency control circuit is provided at a stage subsequent to the offset removing means 17 and at least based on a switching signal from the outside.
- a dividing means 18 or an averaging means 19 as a switching means which operates so as to switch between an operation of estimating a frequency deviation for a signal of two symbol periods and an operation of holding an estimated frequency deviation for other signals.
- the switching between the operation of the automatic frequency control circuit and the operation of holding the estimated frequency deviation is described as the moment when the received signal switches from the preamble signal to the random data. The timing is good.
- a received signal to which a preamble signal is added at the beginning is targeted.
- a two-symbol period signal portion composed of a two-symbol period signal does not necessarily have to be at the beginning of the data sequence.
- the present application is applicable as long as it is arranged at a predetermined position.
- one reception is performed for a PSK-modulated signal having a data format in which a preamble signal of two symbol periods is added to the beginning.
- the preamble signal is received, high-precision frequency deviation estimation is performed in a short time using the automatic frequency control circuit described in Embodiment 1, and the received signal shifts from the preamble signal to the random data section. Then, the operation is switched, and the frequency deviation is estimated using the estimated frequency deviation at the time of receiving the preamble signal as the initial value.
- FIG. 10 is a block diagram showing a configuration of an automatic frequency control circuit according to Embodiment 3 having one receiving antenna.
- the automatic frequency control circuit comprises a complex multiplication type 1-symbol delay detection means 14-1, arctangent means 15, 2 M symbol phase rotation amount calculation means 16, offset removal means 17, division Means 18, averaging means 19, integrator 20, subtractor 30, modulation component removing means 31, averaging means 32 and integrator 34.
- the automatic frequency control circuit shown in FIG. 10 is different from the automatic frequency control circuit shown in FIG. 2 in that a subtractor 30, modulation component removing means 31, averaging means 32 and an integrator 34 are added. It is a thing.
- a second integrator 20 is newly provided on an output line extending from the integrator 20 to the averaging means 19.
- the output line extending from the arctangent means 15 branches into two branches, one of which is connected to the 2M symbol phase rotation amount calculating means 16 as in FIG. 2, and the other is a subtractor 3 Connected to 0.
- the output line of the subtractor 30 is connected to the modulation component removing means 31.
- the output line of the modulation component removing means 31 is connected to the averaging means 32.
- the output line of the averaging means 32 is connected to the integrator 34.
- a switching signal is externally input to the integrator 34.
- the output line of the integrator 34 is bifurcated, and one is connected to feed back to the subtractor 30.
- the other is connected to integrator 20.
- Other configurations are the same as those of the automatic frequency control circuit of FIG. FIG. 11 is an operation timing chart of the integrator 34.
- the automatic frequency control circuit according to the present embodiment is configured such that a subtraction means 30 outputs an output from an integrator 34 described later based on the phase rotation amount for one symbol period output from the arctangent means 15. The estimated phase rotation amount during one symbol period is subtracted.
- the modulation component removing unit 31 determines a modulation component based on the subtraction result output from the subtraction unit 30. Then, the phase rotation amount due to the frequency deviation estimation error during one symbol period is extracted by subtracting the phase rotation amount during one symbol period due to the determined modulation component from the subtraction result output from the subtraction means 30. Output.
- the averaging means 32 averages the phase rotation amount due to the frequency deviation estimation error for one symbol period output from the modulation component removing means 31 to improve the SN ratio and output the signal.
- the integrator 34 updates the integrated value to the value output from the averaging means 19 when receiving the preamble, and outputs the integrated value when receiving random data. It integrates and outputs the output phase rotation amount due to the averaged frequency deviation estimation error during one symbol period.
- the automatic frequency control circuit according to the present embodiment performs the same operation as the automatic frequency control circuit according to the first embodiment shown in FIG. 2 when receiving a brimble signal, and estimates the frequency deviation when receiving random data. Since the frequency deviation is estimated by performing feedback control so that the error becomes "0", high-speed, high-accuracy, power and good frequency deviation tracking characteristics when receiving a random pattern are realized.
- the automatic frequency control circuit according to the present embodiment shown in FIG. 10 has a configuration in which the averaging means 19 is provided at the subsequent stage of the dividing means 18, but the same applies even if the order of these processes is changed. Is output.
- a configuration may be adopted in which the averaging means 19 performs the averaging processing and then the dividing means 18 performs the division processing.
- the operation of updating to the value output from the averaging means 19 and the averaging output from the averaging means 32 are performed by the integrator 34 of the automatic frequency control circuit according to the present embodiment. Integrates phase rotation due to frequency deviation estimation error during one symbol period T / JP2004 / 006182
- the operation switching is described as the moment when the received signal switches from the preamble signal to the random data, but the processing switching timing may be any timing.
- the integrator 34 of the automatic frequency control circuit two operations are performed by the integrator 34 of the automatic frequency control circuit according to the present embodiment.
- the operation of updating to the value output from the averaging means 19, the averaging means 3 There may be performed three operations: an operation of integrating the phase rotation amount due to the averaged frequency deviation estimation error during one symbol period output from 2; and an operation of holding the integrated value.
- the value of the estimated frequency deviation can be retained even when there is no signal where the PSK modulated signal is not received, and it is possible to prevent malfunction of the automatic frequency control circuit when there is no signal. is there.
- a switching signal is externally input to the integrator 34, and the operation is internally switched by the switching signal.
- the integrator 34 outputs the value output from the averaging means 18 as it is in response to the switching signal (external signal), and integrates and outputs the amount of phase rotation output from the averaging means 18.
- the operation switches to at least three types of operations that maintain the,, and integral values as the estimated frequency deviation. Embodiment 4.
- a PSK-modulated signal having a data format in which a preamble signal of two symbol periods is added to the beginning is received by N reception antennas, and a preamble signal is received.
- highly accurate frequency deviation estimation is performed in a short time using the automatic frequency control circuit described in Embodiment 2, and when the received signal moves from the preamble signal to the random data section, the estimated frequency at the time of reception of the briamble signal is received.
- the automatic frequency control circuit according to the fourth embodiment is different from the automatic frequency control circuit according to the second embodiment in that an automatic frequency control circuit for random data of the automatic frequency control circuit according to the third embodiment is added. Therefore, only the processing after the timing of switching from the reception of the preamble signal to the reception of the random data is described below, and the same configuration is denoted by the same reference numeral. Omitted.
- FIG. 12 is a configuration example of an automatic frequency control circuit according to the fourth embodiment having N receiving antennas.
- the integrator 34 updates the integrated value to the value output from the averaging means 19 and outputs the integrated value at the time of receiving a burst, as in the third embodiment.
- the phase averaging means 32 integrates the phase rotation amount due to the averaged frequency deviation estimation error for one symbol period and outputs the result.
- the automatic frequency control circuit according to the present embodiment performs the same operation as the automatic frequency control circuit according to the second embodiment shown in FIG. 8 when receiving a briumple signal, and performs the third embodiment when receiving random data.
- the frequency deviation is estimated by performing feedback control so that the frequency deviation estimation error becomes "0". Therefore, even when two or more receiving antennas are used, high-speed and high-precision First, good frequency deviation tracking characteristics at the time of random pattern reception are realized.
- the automatic frequency control circuit according to the present embodiment shown in FIG. 12 has a configuration in which the averaging means 19 is provided after the dividing means 18, but the same applies even if the order of these processes is changed. Is output. In other words, a configuration may be adopted in which the averaging means 19 performs the averaging processing and then the dividing means 18 performs the division processing.
- the integrator 34 of the automatic frequency control circuit updates the value output from the averaging means 19 to the value output from the averaging means 32.
- the switching of the operation for integrating the phase rotation amount due to the averaged frequency deviation estimation error during one symbol period has been described as the moment when the received signal switches from the pre-completion signal to random data. Any timing is fine.
- the integrator 34 of the automatic frequency control circuit two operations are performed by the integrator 34 of the automatic frequency control circuit according to the present embodiment.
- the operation of updating to the value output from the averaging means 19, the averaging means 3 There may be performed three operations: an operation of integrating the phase rotation amount due to the averaged frequency deviation estimation error during one symbol period output from 2; and an operation of holding the integrated value.
- the value of the estimated frequency deviation can be held even when there is no PSK modulated signal and no signal is received. It is possible to prevent malfunction of the automatic frequency control circuit at the time of a signal.
- a PSK-modulated signal having a data format in which a preamble signal of two symbol periods is added at the beginning is received by N receiving antennas, and
- the complex signal output from the complex multiplication type 1-symbol differential detection means is added based on the branch control signal indicating which branch signal is to be used.
- the automatic frequency control circuit according to the fifth embodiment is different from the automatic frequency control circuit according to the second or fourth embodiment in that the complex signal output from the complex multiplying one-symbol differential detection means is used for addition. Since the function of selecting whether or not to select each branch is added, and other configurations are the same, only the part that adds the complex signal output from the complex multiplication type one-symbol differential detection means will be described below. Description The same components are denoted by the same reference numerals, and description thereof is omitted.
- FIG. 13 is an example of the configuration of the automatic frequency control circuit according to the fifth embodiment, and is different from the automatic frequency control circuit according to the second embodiment shown in FIG. This is a configuration in which the function of selecting whether or not to use the complex signal output from the means for addition for each branch is added.
- a branch control signal is input to the adder 40 from outside.
- FIG. 14 is another example of the configuration of the automatic frequency control circuit according to the fifth embodiment, which is different from the automatic frequency control circuit according to the fourth embodiment shown in FIG. This is a configuration in which the function of selecting whether or not to use the complex signal output from the symbol differential detection means for addition for each branch is added.
- the automatic frequency control circuit according to the fifth embodiment is composed of a complex multiplication type one-symbol differential detection means 1411-1 to 141-N output from an addition means 40 based on a branch control signal. It selects whether or not to add complex signals for each branch, performs addition, and outputs the addition result.
- the automatic frequency control circuit according to the fifth embodiment realizes low power consumption by reducing the number of branches used for addition when the SN ratio is good, and has a poor SN ratio. In this case, by increasing the number of branches used for addition, it is possible to obtain a large diversity gain and achieve good frequency synchronization characteristics.
- the automatic frequency control circuit according to the fifth embodiment shown in FIG. 13 or FIG. 14 has a configuration in which an averaging means 19 is provided after the dividing means 18. Even if the order of the processing is changed, the same operation result is output. That is, averaging
- the configuration may be such that the division processing is performed by the division means 18 after the averaging processing is performed by the means 19.
- the automatic frequency control circuit comprises a force receiving antenna 111 controlling the branch used in the adding means 40 by a branch control signal.
- Detector 1 2—1 to 1 2—N Detector 1 2—1 to 1 2—N
- AZD converter 1 3 _ 1 to 1 3—N Detector 1 2—1 to 1 2—N
- Complex multiplying 1-symbol differential detector 1 4—1 to 14—N or addition
- the control may be performed at any one or more of the means 40.
- the timing of switching between the operation of the configuration example of the automatic frequency control circuit according to the present embodiment shown in FIG. 13 and the operation of holding the estimated frequency deviation is arbitrary. Timing is good.
- an integrator 34 of another configuration example of the automatic frequency control circuit according to the present embodiment shown in FIG. The switching timing of the operation to update to the value output from 9 and the averaging means 32 The operation to switch the operation to integrate the phase rotation amount due to the averaged frequency deviation estimation error during one symbol period output from 2 is arbitrary. Good.
- the integrator 34 of the automatic frequency control circuit according to the present embodiment includes an operation of updating to a value output from the averaging means 19, The operation of integrating the phase rotation amount due to the averaged frequency deviation estimation error during one symbol period output from 32 and the operation of retaining the integrated value may be performed.
- the value of the estimated frequency deviation can be held even when there is no signal in which the PSK modulated signal is not received. It is possible to prevent malfunction of the automatic frequency control circuit at the time of a signal.
- an automatic frequency control circuit and an automatic frequency control method according to the present invention Is useful for a digital wireless communication system using the PSK modulation method, and in particular, PSK-modulated reception is a data sequence in which a two-symbol period signal portion consisting of a two-symbol period signal is arranged at a predetermined position. It is suitable for a frequency control circuit for correcting the frequency deviation of a signal and an automatic frequency control method.
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Abstract
Description
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CN200480004970.3A CN1754363A (zh) | 2004-04-28 | 2004-04-28 | 自动频率控制电路以及自动频率控制方法 |
PCT/JP2004/006182 WO2005107203A1 (ja) | 2004-04-28 | 2004-04-28 | 自動周波数制御回路および自動周波数制御方法 |
JP2006519139A JPWO2005107203A1 (ja) | 2004-04-28 | 2004-04-28 | 自動周波数制御回路および自動周波数制御方法 |
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JP2011103650A (ja) * | 2009-10-30 | 2011-05-26 | Fujitsu Ltd | フィードバックループを用いた周波数オフセット評価 |
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0548341A (ja) * | 1991-08-13 | 1993-02-26 | Oki Electric Ind Co Ltd | Afc装置 |
JPH0787149A (ja) * | 1993-09-14 | 1995-03-31 | Nec Corp | 復調装置 |
JPH09266499A (ja) * | 1996-01-26 | 1997-10-07 | Oki Electric Ind Co Ltd | デジタル復調回路、最大値検出回路及び受信装置 |
JP2000022613A (ja) * | 1998-07-06 | 2000-01-21 | Matsushita Electric Ind Co Ltd | 最大比合成ダイバーシティ受信装置 |
JP2002044176A (ja) * | 2000-07-31 | 2002-02-08 | Mitsubishi Electric Corp | 無線通信用受信装置 |
-
2004
- 2004-04-28 CN CN200480004970.3A patent/CN1754363A/zh active Pending
- 2004-04-28 WO PCT/JP2004/006182 patent/WO2005107203A1/ja active Application Filing
- 2004-04-28 JP JP2006519139A patent/JPWO2005107203A1/ja not_active Withdrawn
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0548341A (ja) * | 1991-08-13 | 1993-02-26 | Oki Electric Ind Co Ltd | Afc装置 |
JPH0787149A (ja) * | 1993-09-14 | 1995-03-31 | Nec Corp | 復調装置 |
JPH09266499A (ja) * | 1996-01-26 | 1997-10-07 | Oki Electric Ind Co Ltd | デジタル復調回路、最大値検出回路及び受信装置 |
JP2000022613A (ja) * | 1998-07-06 | 2000-01-21 | Matsushita Electric Ind Co Ltd | 最大比合成ダイバーシティ受信装置 |
JP2002044176A (ja) * | 2000-07-31 | 2002-02-08 | Mitsubishi Electric Corp | 無線通信用受信装置 |
Non-Patent Citations (1)
Title |
---|
SHIMAKATA Y.,OHSAWA H.: "Performance of the PSK Baseband Differential Detector", THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS SOGO TAIKAI KOEN RONBUNSHU, TSUSHIN 1, vol. 2-B-360, 15 March 1991 (1991-03-15), XP002994213 * |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2011103650A (ja) * | 2009-10-30 | 2011-05-26 | Fujitsu Ltd | フィードバックループを用いた周波数オフセット評価 |
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