WO2005036402A1 - テストプログラムデバッグ装置、半導体試験装置、テストプログラムデバッグ方法、及び試験方法 - Google Patents
テストプログラムデバッグ装置、半導体試験装置、テストプログラムデバッグ方法、及び試験方法 Download PDFInfo
- Publication number
- WO2005036402A1 WO2005036402A1 PCT/JP2004/014659 JP2004014659W WO2005036402A1 WO 2005036402 A1 WO2005036402 A1 WO 2005036402A1 JP 2004014659 W JP2004014659 W JP 2004014659W WO 2005036402 A1 WO2005036402 A1 WO 2005036402A1
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- test
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- range
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/28—Error detection; Error correction; Monitoring by checking the correct order of processing
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318314—Tools, e.g. program interfaces, test suite, test bench, simulation hardware, test compiler, test program languages
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
Definitions
- Test program debug device semiconductor test device, test program debug method, and test method
- the present invention relates to a test program debug device, a semiconductor test device, a test program debugging method, and a test method.
- the present invention relates to a test program debugging apparatus and a test program debugging method for virtually executing a test program for a semiconductor test apparatus to debug a test program, and to test a device under test by executing the test program.
- the present invention relates to a semiconductor test device and a test method.
- a semiconductor test apparatus executes a test program for the semiconductor test apparatus, thereby supplying a test pattern to the device under test and performing various tests on the device under test.
- This test program consists of a huge number of instructions that specify test conditions, test pattern generation, test pattern comparison, etc., and are created or changed according to the type of semiconductor test equipment and the type of device under test. . If a test program is created or modified, it must be verified that the test program operates properly.
- test programs are verified by using a general-purpose computer such as a workstation to execute a test program on a semiconductor test device and a test program debug device that simulates a device under test (for example, a test program).
- Patent Document 1 Japanese Patent Application Laid-Open No. 2001-51025
- the test program is composed of a huge number of instructions as described above, and therefore, it takes a lot of time to execute the test program.
- the conventional test program debug device cannot execute only a part of the instructions of the test program, and can verify only the instructions of some of the plurality of test items. Multiple test patterns Even when verifying only an instruction for generating a part of the test pattern, all instructions of the test program must be executed. Therefore, there was a problem that it took a lot of time to verify the test program.
- an object of the present invention is to provide a test apparatus that can solve the above-described problems. This object is achieved by a combination of features described in the independent claims.
- the dependent claims define further advantageous embodiments of the present invention.
- a test program debugging apparatus for debugging a test program for a semiconductor test apparatus, wherein a device simulator under test simulating a device under test and a test program are executed.
- a semiconductor test apparatus simulator for simulating the semiconductor test apparatus and supplying a test pattern to the device simulator under test.
- the semiconductor test equipment simulator includes a verification range obtaining unit that obtains a verification range that is a range of an instruction to be verified in the test program, and a verification range acquisition unit that includes a non-verification range other than the verification range in the test program.
- an instruction execution unit for executing the non-setting instruction simplified by the instruction simplification unit.
- the non-setting instruction is, as a non-setting instruction, a pattern generation instruction for generating a test pattern, and a pattern for comparing an output pattern output from the device simulator under test with an expected value for the test pattern.
- the instruction simplification unit includes a comparison instruction, the instruction simplification unit simplifies the pattern generation instruction and the pattern comparison instruction, and the instruction execution unit executes the verification range instruction and the setting instruction, and the simplified pattern generation instruction and the pattern comparison instruction. May be.
- the instruction simplification unit may set the non-setting instruction as an instruction that is not executed by the instruction execution unit, and the instruction execution unit may execute the verification range instruction and the setting instruction, and may not execute the non-setting instruction.
- debugging of a test program for a semiconductor test apparatus is performed.
- the semiconductor test equipment simulator acquires a verification range that is a range of instructions to be verified in the test program, and the device-under-test simulator obtains a non-verification range that is a range other than the verification range in the test program.
- the non-verification range instructions included in the non-verification range instructions other than the setting instruction for setting the device-under-test simulator are simply executed.
- the device simulator under test holds in advance the output pattern for the test pattern supplied by the simulator power of the semiconductor test equipment, and holds in advance the test pattern of the simulator power of the semiconductor test equipment based on the non-setting instruction. Then, an output pattern may be output.
- a semiconductor test apparatus for testing a device under test by executing a test program, wherein a range of an instruction to be used for testing the device under test in the test program.
- a test range acquisition unit that acquires a test range that is a non-test range instruction included in a non-test range that is a range other than the test range in the test program, other than a setting instruction for setting the device under test
- An instruction simplification unit that simplifies the non-setting instruction, and an instruction execution unit that executes the non-setting instruction simplified by the test range instruction, the setting instruction, and the instruction simplification unit included in the test range.
- the non-setting instruction is, as the non-setting instruction, a pattern generation instruction for generating a test pattern and a pattern comparison instruction for comparing the test pattern output from the device under test with the expected value for the test pattern.
- the instruction simplification unit simulates the pattern generation instruction and the pattern comparison instruction
- the instruction execution unit simulates the test range instruction and the setting instruction, and the simplified pattern generation instruction and the pattern comparison instruction. May be performed.
- a device simulator under test that simulates a device under test, and a test program for a semiconductor test device are executed to simulate the semiconductor test device, thereby providing a device simulator under test.
- Test equipment that supplies test patterns to the semiconductor
- a test program debugging method using a test program debugging device including a simulator wherein a step of obtaining a verification range, which is a range of an instruction to be verified in the test program, and a range other than the verification range of the test program.
- a test method for testing a device under test by executing a test program comprising: The step of acquiring a certain test range and the non-test range instructions included in the non-test range, which is a range other than the test range in the test program, are the non-test range commands other than the setting command for setting the device under test. There is a step of simplifying the setting instruction, and a step of executing a test range instruction, a setting instruction, and a simplified non-setting instruction included in the test range.
- test program debugging device and a test program debugging method capable of accurately verifying a desired instruction included in a test program in a short time, and to provide a desired test item included in a test program.
- a semiconductor test apparatus and a test method that can selectively test can be provided.
- FIG. 1 is a diagram showing an example of a configuration of a test program debugging device 100.
- FIG. 2 is a diagram showing an example of a configuration of a semiconductor test apparatus 200.
- FIG. 3 is a diagram showing an example of a configuration of a test program 110 and a pattern program 300.
- FIG. 1 shows an example of a configuration of a test program debugging device 100 according to an embodiment of the present invention.
- the test program debug device 100 is implemented by a general-purpose computer such as a workstation, and simulates the operation of the semiconductor test device 200 and the device under test 202 to verify whether the test program 110 operates normally. To debug. As described above, since the test program debug device 100 simulates the semiconductor test device 200 and the device under test 202, first, the configuration and operation of the actual semiconductor test device 200 will be described with reference to FIG. .
- FIG. 2 shows an example of a configuration of a semiconductor test apparatus 200 according to an embodiment of the present invention.
- the semiconductor test apparatus 200 includes a test module 206 connected to the device under test 202 to exchange test patterns with the device under test 202, a test module control unit 204 for controlling the test module 206, and a test module control unit 204. And a tester bus 222 connecting the test module 206 and the test module 206.
- the test module control unit 204 includes a test program 110, an application program 210, a language analysis execution unit 212, and a tester library 21. 4 and a tester bus driver 216. Then, the application program 210 functions as the test range obtaining unit 218 and the instruction simpler unit 220.
- the test module 206 includes a register 224, a memory 226, and a test execution unit 228.
- the test program 110 describes the contents of a test performed on the device under test 202.
- the language analysis execution unit 212 analyzes the syntax of the test program 110 and operates the semiconductor test apparatus 200 according to the test program 110.
- the application program 210 operates in cooperation with the test program 110 and the language analysis execution unit 212, and controls application of a test pattern to the device under test 202.
- the tester library 214 converts the instructions of the test program 110 parsed by the language analysis executing unit 212 into register-level instructions, generates pattern data, sets the test module 206, and sets up the test module 206. Is instructed to perform a measurement operation. Then, the tester bus driver 216 transfers the pattern data generated by the tester library 214 to the register 224 via the tester bus 222.
- the register 224 stores the pattern data generated by the tester library 214, and supplies the stored pattern data to the test execution unit 228 directly or via the memory 226. Then, the test execution unit 228 tests the device under test 202 based on the pattern data stored in the register 224 or the memory 226, and stores the test result in the register 224 or the memory 226. Then, the tester bus driver 216 takes in the test results stored in the register 224 or the memory 226 into the tester library 214 via the tester bus 222. Then, the application program 210 performs pass / fail judgment of the device under test 202, characteristic analysis of the device under test 202, and the like based on the test results taken into the tester library 214.
- the test program debug device 100 shown in FIG. 1 simulates the operations of the semiconductor test device 200 and the device under test 202, and verifies whether or not the test program 110 operates normally. To debug. Next, the configuration and operation of the test program debug device 100 will be described with reference to FIG.
- the test program debug apparatus 100 includes a device under test simulator 104 that simulates the device under test 202, and a semiconductor test apparatus 200 that executes the test program 110. And a semiconductor test apparatus simulator 102 that simulates a test pattern and supplies a test pattern to the device under test 202.
- the semiconductor test equipment simulator 102 includes a test module emulator 108 that emulates the test module 206, an emulator control unit 106 that controls the test module emulator 108, an emulator control unit 106, and a test module emulator 108. And a test result analysis / judgment unit 136 for analyzing the test result of the device simulator under test 104.
- the emulator control unit 106 includes a test program 110, an application program 112, a language analysis execution unit 114, a tester library 116, and a tester bus emulator 118. Then, the application program 112 functions as a verification range acquisition unit 120 and a command simplification unit 122.
- the test module emulator 108 includes a virtual register 126, a virtual memory 128, and a virtual test execution unit 130.
- the emulator control unit 106 performs the same operation as the test module control unit 204 shown in FIG. 2, and controls the test module emulator 108 that realizes the operation of the test module 206 shown in FIG. 2 by software.
- the test program 110 is a ported version of the test program 110 shown in FIG. 2, and is to be debugged by the test program debug device 100.
- the language analysis execution unit 114 analyzes the syntax of the test program 110 and operates the semiconductor test equipment simulator 102 according to the test program 110.
- the application program 112 operates in cooperation with the test program 110 and the language analysis execution unit 114, and controls application of a test pattern to the device simulator 104 under test.
- the tester library 116 is an example of the instruction execution unit of the present invention.
- the language analysis execution unit 114 converts the instructions of the test program 110 parsed by the language analysis execution unit 114 into register-level instructions to generate pattern data. And setting of the test module emulator 108, and instructs the test module emulator 108 to perform a measurement operation. Then, the test bus emulator 118 transfers the pattern data generated by the tester library 116 to the virtual register 126 via the virtual tester bus 124.
- the virtual register 126 stores the pattern data generated by the tester library 116, and supplies the stored pattern data to the virtual test execution unit 130 directly or via the virtual memory 128. Then, the virtual test execution unit 130 sets the virtual register 126 or The virtual memory 128 performs a virtual test of the device under test simulator 104 based on the pattern data, and stores the virtual test result in the virtual register 126 or the virtual memory 128. Then, the tester bus emulator 118 takes in the virtual test result stored in the virtual register 126 or the virtual memory 128 into the tester library 116 via the virtual tester bus 124.
- test result analysis determination unit 136 compares the virtual test result stored in the tester library 116, the virtual register 126, or the virtual memory 128 with the expected value of the virtual test result generated in advance. Then, the test result analysis / determination unit 136 verifies whether the test program 110 is operating normally, and notifies the user of the verification result. For example, when the virtual test result is different from the expected value, the line number or the like of the test program 110 that is the basis of the virtual test result is displayed on a monitor or printed by a printer.
- FIG. 3 shows an example of the configuration of the test program 110 and the pattern program 300.
- the test program 110 measures, for each test number 302, which is an identifier of a test item, a test condition instruction group 304 for specifying test conditions, and an output pattern from the device under test 202 or the test module emulator 108.
- a measurement instruction group 306 is provided.
- the measurement instruction group 306 includes a setting instruction 308 that is an instruction for setting the test module 206 or the test module emulator 108, a pattern generation instruction 310 that is an instruction for generating a test pattern, and a test pattern
- a pattern comparison instruction 312 for comparing an output pattern output from the device under test 202 or the device under test simulator 104 with an expected value generated in advance.
- the setting instruction 308 is, for example, setting of a register value.
- the pattern program 300 is called by the pattern generation instruction 310 and has information for generating a test pattern. Specifically, the pattern program 300 holds pattern data 316 indicating the test pattern in association with the address 314 of the test pattern.
- the test program debugging device 100 shown in FIG. 1 verifies the test program 110 by sequentially executing the test program 110 shown in FIG. Or a range of the pattern data to be verified in the pattern program 300, and the instructions of a part of the selected test program 110 may be verified! That is, the verification range obtaining unit 120 obtains a verification range, which is a range of an instruction to be verified in the test program 110, based on a user's instruction input. For example, when the user specifies the test number 302 or the range of the test number 302 in the test program 110, the verification range obtaining unit 120 obtains the test number 302 or the range of the test number 302 as the verification range. I do.
- the verification range acquisition unit 120 may acquire, as a verification range, a range of a test pattern to be verified in the pattern program 300 based on a user's instruction input. For example, when the user specifies the address 314 of the test pattern in the pattern program 300 or the range of the address 314 of the test pattern, the verification range acquisition unit 120 outputs the test pattern of the address 314 of the specified test pattern or the specified test pattern. The test pattern in the range of the test pattern address 314 may be acquired as the verification range. In addition, when the test pattern address 314 and the count range in the pattern program 300 are specified by the user, the verification range obtaining unit 120 determines the test pattern within the specified count range from the specified test pattern address 314. May be acquired as the verification range. If none of the address 314 of the test pattern, the address range of the test pattern, and the address 314 of the test pattern and the count range are specified, the verification range obtaining unit 120 transmits the All test patterns may be acquired as the verification range.
- the instruction simplification unit 122 includes, among the non-verification range instructions which are instructions included in the non-verification range that is a range other than the verification range acquired by the verification range acquisition unit 120 in the test program 110,
- the non-setting instruction which is an instruction other than the setting instruction 308 for setting the device simulator under test 104, is simplified.
- the instruction simplification unit 122 simplifies the pattern generation instruction 310 and the pattern comparison instruction 312, which are non-setting instructions, and converts them into simple instructions.
- the instruction simplification unit 122 detects an execution instruction of the test pattern provided in the preceding stage of the pattern generation instruction 310, and simply executes an instruction subsequent to the execution instruction of the test pattern in a test item including the execution instruction of the test pattern. Do
- the tester library 116 checks the verification range instruction which is an instruction included in the verification range acquired by the verification range acquisition unit 120, the setting instruction 308 of the non-verification range instruction, and the non-verification instruction.
- the non-setting instruction simplified by the instruction simplification unit 122 among the verification instructions is executed, and the test module emulator 108 is operated.
- the instruction simple setting unit 122 may set the non-setting instruction as an instruction that is not executed by the tester library 116.
- the tester library 116 may execute the verification range instruction and the setting instruction, and may not execute the non-setting instruction.
- the verification range specified by the user can be verified in a short time by simplifying the command other than the verification range obtained from the user. Furthermore, among instructions outside the verification range acquired from the user, instructions for setting the register values of the device simulator under test 104 and the like are executed without simplification, thereby verifying some instructions of the test program 110. Even when the range is within the range, the device under test simulator 104 can be operated in the same environment as in the case where all of the test programs 110 are verified, so that the test programs 110 can be accurately verified.
- the device simulator under test 104 executes the simulation based on the non-setting command in a simple setting. May be.
- the device-under-test simulator 104 has an output pattern table 138 in which output patterns for the test patterns supplied from the semiconductor test apparatus simulator 102 are stored in advance. Then, for the test pattern from the semiconductor test equipment simulator 102 based on the non-setting instruction, the device simulator under test 104 outputs an output pattern held in advance in association with the test pattern.
- the simulation time by the device-under-test simulator 104 can be reduced, and the verification range can be quickly verified.
- the semiconductor test apparatus 200 shown in FIG. 2 tests the device under test 202 by sequentially executing the test program 110 shown in FIG.
- a range of instructions to be tested or a range of pattern data to be tested in the pattern program 300 may be selected to test a part of the selected test program 110.
- the test range obtaining unit 218 obtains a test range which is a range of an instruction to be tested in the test program 110 based on an instruction input by the user.
- a test producer When the user designates the test number 302 or the range of the test number 302 in the system 110, the test range acquisition unit 218 acquires the test number 302 or the range of the test number 302 as the test range.
- the test range acquisition unit 218 may acquire, as a test range, a range of a test pattern to be tested in the pattern program 300 based on a user's instruction input.
- the test range acquisition unit 218 determines the test pattern of the address 314 of the specified test pattern or the specified test pattern.
- the test pattern in the range of the test pattern address 314 may be acquired as the test range.
- the test range obtaining unit 218 determines the test pattern within the specified count range from the address 314 of the specified test pattern. May be acquired as the test range. If none of the test pattern address 314, the test pattern address range, and the test pattern address 314 and the count range are specified, the test range obtaining unit 218 May be obtained as a test range.
- the instruction simplification unit 220 includes a non-test range instruction that is an instruction included in a non-test range that is a range other than the test range acquired by the test range acquisition unit 218 in the test program 110.
- the non-setting instruction other than the setting instruction 308 for setting the device under test 202 is simplified.
- the command simplification unit 220 simplifies the pattern generation command 310 and the pattern comparison command 312, which are non-setting commands, and converts them into simple commands.
- the tester library 214 includes a test range instruction which is an instruction included in the test range acquired by the test range acquisition unit 218, a setting instruction 308 among non-test range instructions, and an instruction simplification unit 220 among non-test range instructions.
- the instruction simplification unit 220 may set the non-setting instruction as an instruction not executed by the tester library 214 as another example of the non-setting instruction. Then, the tester library 214 may execute the test range instruction and the setting instruction, and may not execute the non-setting instruction.
- test range specified by the user can be tested in a short time. Furthermore, when a command for setting the register value of the device under test 202 among instructions other than the test range obtained from the user is executed without simplification, a part of the test program 110 is set as the test range. Even so, the device under test 202 can be operated in the same environment as when all the test programs 110 are tested, so that the test program 110 can be accurately tested.
- test program debug device and a test program debug method capable of accurately verifying a desired instruction included in a test program in a short time.
- a semiconductor test apparatus and a test method capable of selectively testing desired test items included in the semiconductor device can be provided.
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Abstract
Description
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
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JP2005514571A JPWO2005036402A1 (ja) | 2003-10-07 | 2004-10-05 | テストプログラムデバッグ装置、半導体試験装置、テストプログラムデバッグ方法、及び試験方法 |
EP04792070A EP1672508A4 (en) | 2003-10-07 | 2004-10-05 | TEST PROGRAM DE-GROWING DEVICE, SEMICONDUCTOR TESTING DEVICE, AND TESTING METHOD |
US11/211,162 US7269773B2 (en) | 2003-10-07 | 2005-08-24 | Test program debugger device, semiconductor test apparatus, test program debugging method and test method |
Applications Claiming Priority (2)
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JP2003348617 | 2003-10-07 | ||
JP2003-348617 | 2003-10-07 |
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US11/211,162 Continuation US7269773B2 (en) | 2003-10-07 | 2005-08-24 | Test program debugger device, semiconductor test apparatus, test program debugging method and test method |
Publications (1)
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WO2005036402A1 true WO2005036402A1 (ja) | 2005-04-21 |
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US (1) | US7269773B2 (ja) |
EP (1) | EP1672508A4 (ja) |
JP (2) | JPWO2005036402A1 (ja) |
KR (1) | KR20060108662A (ja) |
CN (1) | CN100412811C (ja) |
TW (1) | TWI334489B (ja) |
WO (1) | WO2005036402A1 (ja) |
Cited By (3)
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JP2009116878A (ja) * | 2007-11-05 | 2009-05-28 | Advantest Corp | 試験装置のシミュレーションシステム、方法、及びプログラム製品 |
JP2009116876A (ja) * | 2007-11-05 | 2009-05-28 | Advantest Corp | 試験装置のシミュレーションシステム、方法、及びプログラム製品 |
WO2011001462A1 (ja) * | 2009-06-29 | 2011-01-06 | 株式会社アドバンテスト | 試験装置 |
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US7970594B2 (en) * | 2005-06-30 | 2011-06-28 | The Mathworks, Inc. | System and method for using model analysis to generate directed test vectors |
US8874425B2 (en) | 2007-03-22 | 2014-10-28 | The Invention Science Fund I, Llc | Implementing performance-dependent transfer or execution decisions from service emulation indications |
US8495708B2 (en) * | 2007-03-22 | 2013-07-23 | The Invention Science Fund I, Llc | Resource authorizations dependent on emulation environment isolation policies |
US8438609B2 (en) | 2007-03-22 | 2013-05-07 | The Invention Science Fund I, Llc | Resource authorizations dependent on emulation environment isolation policies |
US9378108B2 (en) * | 2007-03-22 | 2016-06-28 | Invention Science Fund I, Llc | Implementing performance-dependent transfer or execution decisions from service emulation indications |
US9558019B2 (en) | 2007-03-22 | 2017-01-31 | Invention Science Fund I, Llc | Coordinating instances of a thread or other service in emulation |
WO2008120389A1 (ja) * | 2007-03-29 | 2008-10-09 | Fujitsu Limited | メモリテスト回路、半導体集積回路およびメモリテスト方法 |
WO2009149583A1 (en) * | 2008-06-12 | 2009-12-17 | Zoran Corporation | System and method for locating a fault on a device under test |
US7984353B2 (en) * | 2008-08-29 | 2011-07-19 | Advantest Corporation | Test apparatus, test vector generate unit, test method, program, and recording medium |
CN102006183A (zh) * | 2010-11-12 | 2011-04-06 | 百度在线网络技术(北京)有限公司 | 一种用于基于配置参数配置网络设备的方法与配置设备 |
US9959186B2 (en) * | 2012-11-19 | 2018-05-01 | Teradyne, Inc. | Debugging in a semiconductor device test environment |
CN203117963U (zh) * | 2012-12-17 | 2013-08-07 | 新唐科技股份有限公司 | 提供图形化接脚接口的调试***与装置 |
WO2015135740A1 (en) * | 2014-03-10 | 2015-09-17 | Mhwirth As | Improved method for testing a control system |
US11513781B2 (en) * | 2020-08-07 | 2022-11-29 | International Business Machines Corporation | Simulating container deployment |
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2004
- 2004-10-05 WO PCT/JP2004/014659 patent/WO2005036402A1/ja active Application Filing
- 2004-10-05 EP EP04792070A patent/EP1672508A4/en not_active Withdrawn
- 2004-10-05 KR KR1020067008833A patent/KR20060108662A/ko not_active Application Discontinuation
- 2004-10-05 CN CNB2004800288761A patent/CN100412811C/zh not_active Expired - Fee Related
- 2004-10-05 JP JP2005514571A patent/JPWO2005036402A1/ja active Pending
- 2004-10-07 TW TW093130319A patent/TWI334489B/zh not_active IP Right Cessation
-
2005
- 2005-08-24 US US11/211,162 patent/US7269773B2/en not_active Expired - Fee Related
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2010
- 2010-02-26 JP JP2010043436A patent/JP2010146592A/ja active Pending
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JPH0749797A (ja) * | 1993-08-06 | 1995-02-21 | Mitsubishi Electric Corp | プログラム作成装置 |
JP2001051025A (ja) * | 1999-08-12 | 2001-02-23 | Advantest Corp | 半導体試験用プログラムデバッグ装置 |
Non-Patent Citations (1)
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009116878A (ja) * | 2007-11-05 | 2009-05-28 | Advantest Corp | 試験装置のシミュレーションシステム、方法、及びプログラム製品 |
JP2009116876A (ja) * | 2007-11-05 | 2009-05-28 | Advantest Corp | 試験装置のシミュレーションシステム、方法、及びプログラム製品 |
WO2011001462A1 (ja) * | 2009-06-29 | 2011-01-06 | 株式会社アドバンテスト | 試験装置 |
JPWO2011001462A1 (ja) * | 2009-06-29 | 2012-12-10 | 株式会社アドバンテスト | 試験装置 |
KR101239658B1 (ko) | 2009-06-29 | 2013-03-11 | 가부시키가이샤 어드밴티스트 | 시험 장치 |
Also Published As
Publication number | Publication date |
---|---|
US20060248390A1 (en) | 2006-11-02 |
US7269773B2 (en) | 2007-09-11 |
EP1672508A1 (en) | 2006-06-21 |
TWI334489B (en) | 2010-12-11 |
JP2010146592A (ja) | 2010-07-01 |
KR20060108662A (ko) | 2006-10-18 |
TW200513660A (en) | 2005-04-16 |
CN1864143A (zh) | 2006-11-15 |
EP1672508A4 (en) | 2010-06-30 |
CN100412811C (zh) | 2008-08-20 |
JPWO2005036402A1 (ja) | 2007-11-22 |
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