WO2004109639A1 - 画素回路、表示装置、および画素回路の駆動方法 - Google Patents
画素回路、表示装置、および画素回路の駆動方法 Download PDFInfo
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- WO2004109639A1 WO2004109639A1 PCT/JP2004/008055 JP2004008055W WO2004109639A1 WO 2004109639 A1 WO2004109639 A1 WO 2004109639A1 JP 2004008055 W JP2004008055 W JP 2004008055W WO 2004109639 A1 WO2004109639 A1 WO 2004109639A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0852—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory with more than one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
- G09G2300/0861—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0254—Control of polarity reversal in general, other than for liquid crystal displays
- G09G2310/0256—Control of polarity reversal in general, other than for liquid crystal displays with the purpose of reversing the voltage across a light emitting or modulating element within a pixel
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/04—Maintaining the quality of display appearance
- G09G2320/043—Preventing or counteracting the effects of ageing
Definitions
- the present invention relates to a pixel circuit having an electro-optical element whose luminance is controlled by a current value, such as an organic EL (Electroluminescence) display, and an image display device in which the pixel circuits are arranged in a matrix.
- a current value such as an organic EL (Electroluminescence) display
- an image display device in which the pixel circuits are arranged in a matrix.
- the present invention relates to a so-called active matrix image display device in which a current flowing through an electro-optical element is controlled by a green gate type field effect transistor provided inside each pixel circuit, and to a driving method of the pixel circuit.
- an image display device for example, a liquid crystal display
- an image is displayed by arranging a large number of pixels in a matrix and controlling light intensity for each pixel according to image information to be displayed.
- the organic EL display is a so-called self-luminous display having a light-emitting element in each pixel circuit. Are not required, and the response speed is fast.
- each light emitting element is controlled by the value of a current flowing through the light emitting element to obtain a color gradation, that is, the light emitting element is of a current control type, which is much smaller than that of a liquid crystal display or the like.
- organic EL displays can be driven by a simple matrix method or an active matrix method.However, the former has a simple structure, but it is difficult to realize a large and fine display.
- the development of the active matrix method in which the current flowing through the light emitting element inside each window circuit is controlled by an active element provided inside the pixel circuit, generally a TFT (Thin Film Transistor), has been developed. It is being actively performed.
- TFT Thin Film Transistor
- FIG. 1 is a block diagram showing a configuration of a general organic EL display device.
- this display device 1 has a pixel array section 2 in which pixel circuits (PXLC) 2a are arranged in a matrix of mxn, a horizontal selector (HSEL) 3, a light scanner (WSCN) 4, and a horizontal selector. 3 has data lines DTLl to DTLn to which a data signal according to luminance information is supplied, and scanning lines WSLl to WSLm selectively driven by the write scanner 4.
- PXLC pixel circuits
- HSEL horizontal selector
- WSCN light scanner
- the horizontal selector 3 and the light scanner 4 may be formed on polycrystalline silicon, or may be formed around the pixel by MOS IC or the like.
- FIG. 1 is a circuit diagram showing an example of the configuration of a pixel circuit 2a (see, for example, Patent Document 1; US Pat. No. 5,684,365, Patent Document 2; Japanese Patent Application Laid-Open No. 8-234683). '
- the pixel circuit in FIG. 2 has the simplest circuit configuration among many proposed circuits, and is a so-called two-transistor driving circuit.
- the pixel circuit 2a in FIG. 2 includes a p-channel thin film field effect transistor (hereinafter, referred to as TFT) 11 and a TFT 12, a capacitor C11, and a light emitting element 13 including an organic EL element (OLED).
- TFT thin film field effect transistor
- TFT 12 a p-channel thin film field effect transistor
- C11 a capacitor
- OLED organic EL element
- DTL indicates a data line
- WSL indicates a scanning line.
- Organic EL devices are often referred to as OLEDs (Organic Light Bidding Lighting Diodes) because they have rectifying properties in many cases.In Figure 2 and others, the diode symbol is used as the light-emitting device. Does not necessarily require rectification.
- the source of the TFT 1 is connected to the power supply potential VCC, and the cathode (cathode) of the light emitting element 13 is connected to the ground potential GND.
- the operation of pixel circuit 2a in Figure 2 is It is as follows.
- the TFT 2 When the scanning line WSL is set to the selected state (here, low level) and the writing potential Vdata is applied to the data line DTL, the TFT 2 conducts and the capacitor C1 is charged or discharged, and the gate potential of the TFT 1 is Becomes Vdata.
- the scanning line WSL When the scanning line WSL is in a non-selected state (here, high level), the data line DTL is electrically disconnected from the TFT 11, but the gate potential of the TFT 11 is stably held by the capacitor C11.
- the current flowing through the TFT 1] and the optical element 13 has a value corresponding to the gate-source voltage Vgs of the TF], and the light emitting element 13 continues to emit light at a luminance corresponding to the current value.
- writing The operation of selecting the scanning line WSL and transmitting the luminance information given to the data line to the inside of the pixel as in step ST1 above is hereinafter referred to as “writing”.
- the light emitting element 3 continues to emit light at a constant luminance until the next rewriting.
- the value of the current flowing through the EL light emitting element 13 is controlled by changing the gate applied voltage of the drive transistor TFT11.
- the source of the p-channel drive transistor is connected to the power supply potential VCC, and the TFT 11 always operates in the saturation region. Therefore, it is a constant current source having the value shown in Equation 1 below.
- Vgs-IV t I Cox (Vgs-IV t I) 2 "'(1) where is the carrier mobility, C 0 X is the gate capacitance per unit area, and W is the gate L is the gate length, Vgs is the gate-source voltage of TFT 11 And Vth indicate the threshold values of the TFT 11 respectively.
- each light emitting element emits light only at the selected moment.
- the light emitting element continues to emit light even after writing is completed. This is particularly advantageous for large, high-definition displays, in that the peak brightness and peak current of the light-emitting element can be reduced as compared with those of.
- FIG. 3 is a diagram showing a change over time in current-voltage (I-V) characteristics of the organic EL element.
- I-V current-voltage
- the organic EL element continues to flow as described above, and even if the I-V characteristics of the organic EL element are deteriorated, the light emission luminance deteriorates with time. I will not.
- the pixel circuit 2a in Fig. 2 is composed of a P-channel TFT, but if it can be composed of an n-channel TFT, the conventional amorphous silicon (a-Si) process can be used in TFT fabrication. It can be used. This makes it possible to reduce the cost of the TFT substrate.
- a-Si amorphous silicon
- FIG. 4 is a circuit diagram showing a pixel circuit in which the p-channel TFT of the circuit of FIG. 2 is replaced with an n-channel TFT.
- the pixel circuit 2b in FIG. 4 has an n-channel TFT2], a TFT22, and a light emitting element 23 composed of a capacitive C2 organic EL element (OLED).
- DTL indicates a data line
- WSL indicates a scanning line.
- the drain side of TF.T1 is used as a drive transistor. Is connected to the power supply potential VCC, and the source is connected to the anode of the EL element 23, forming a source follower circuit.
- FIG. 5 is a diagram showing operating points of a TFT 21 as a drive transistor and an EL light emitting element 23 in an initial state.
- the horizontal axis represents the drain-source voltage Vds of the TFT 21, and the vertical axis represents the drain-source current Ids.
- the source voltage is determined by the operating point of the drive transistor TFT 21 and the EL light emitting element 23, and the voltage has a different value depending on the get voltage. -.
- the I-V characteristics of the EL element deteriorate with time. As shown in FIG. 6, the operating point fluctuates due to the deterioration over time, and the source voltage fluctuates even when the same gate voltage is applied.
- the gate-source voltage Vgs of the TFT 21 as the drive transistor changes, and the flowing current value changes.
- the value of the current flowing through the EL element 23 also changes. If the IV characteristics of the EL element 23 deteriorate, the light emission luminance of the source follower circuit shown in FIG. 4 changes over time.
- the source of the n-channel TFT 31 as a drive transistor is connected to the ground potential GND, the drain is connected to the cathode of the EL element 33, and the anode of the EL light emitting element 33 is connected to the power supply potential VCC. Circuit configuration to connect to
- the source potential is fixed and the TFT 3] operates as a constant current source as a drive transistor, similar to the drive by the p-channel TFT in FIG.
- the drive transistor is connected to the cathode of the EL light emitting element. This cathode connection requires the development of a new anode * cathode electrode, which is said to be extremely difficult with current technology.
- An object of the present invention is to provide a single source follower output without luminance degradation even if the current-voltage characteristics of a light emitting element change with time, and to enable a single source follower circuit of an n-channel transistor. It is an object of the present invention to provide a pixel circuit, a display device, and a method for driving a pixel circuit in which an n-channel transistor can be used as a driving element for an electro-optical element while using a source electrode.
- a first aspect of the present invention is a pixel circuit for driving an electro-optical element whose luminance changes according to a flowing current, comprising: a data line to which a data signal corresponding to luminance information is supplied; , First, second, third, and fourth nodes, first and second reference potentials, and a pixel capacitor connected between the first node and the second node.
- a drive transistor for controlling a current flowing through the current supply line in accordance with the potential of the control terminal a first switch connected to the third node, the second node and the third node And a second switch connected between the first node and the first node.
- a third switch connected between the fourth node and the potential; a fourth switch connected between the data line and the fourth node; and a third switch connected between the fourth node and a predetermined potential.
- a fifth switch connected to the second reference potential, the fifth switch, the third node, and the current of the drive transistor between the fifth reference potential and the second reference potential.
- the supply line, the first node, and the electro-optical element are connected in series.
- the driving transistor is a field-effect transistor
- a source is connected to the first node
- a drain is connected to the third node.
- the third switch is held in a conductive state
- the fourth switch is held in a non-conductive state
- the third switch is held in a non-conductive state.
- the first switch is held in a conductive state, the first node is connected to a fixed potential, and as a second stage, the second switch and the fifth switch are held in a conductive state, After the first switch is held in a non-conductive state, the second switch and the fifth switch are held in a non-conductive state, and as a third stage, the fourth switch is held in a conductive state. After the data transmitted through the data line is input to the fourth node, the fourth switch is held in a non-conductive state, and as a fourth stage, the third switch is held in a non-conductive state. You.
- the first switch and the fourth switch are held in a non-conductive state, and the third switch is held in a conductive state.
- the second node is connected to a fixed potential, and as a second stage, the second switch and the fifth switch are held in a conductive state, and the second switch is in a conductive state for a predetermined period.
- the second switch and the fifth switch are held in a non-conductive state, and as a third stage, the fourth switch is held in a conductive state and propagated through the data line.
- the fourth switch After the data to be input is input to the fourth node, the fourth switch is held in a non-conductive state, and as a fourth stage, the third switch is held in a non-conductive state. In In the third stage, the fourth switch is maintained in the conductive state after the second switch is maintained in the conductive state.
- the first switch when driving the electro-optical element, as the first stage, the first switch is held in a conductive state, and the fourth switch is held in a non-conductive state.
- the second switch and the fifth switch are held in a conductive state, and as a second stage, the first switch is held in a non-conductive state, while the third switch is turned on.
- the second node is connected to a fixed potential
- the second stage and the fifth switch are maintained in a non-conductive state as a third stage
- the fourth stage is maintained as a fourth stage.
- the fourth switch is kept in a non-conducting state after data transmitted through the data line while the other switch is kept in a conducting state is inputted to the fourth node.
- the first switch is maintained in a conductive state, while the third switch is maintained in a non-conductive state.
- a plurality of pixel circuits arranged in a matrix, a data line wired for each column in the matrix arrangement of the pixel circuits, and supplied with a data signal according to luminance information; A first and a second reference potential, the pixel circuit comprising: an electro-optical element whose luminance changes according to a flowing current; the first, second, third, and fourth nodes; A pixel capacitor connected between the first node and the second node; a coupling capacitor connected between the second node and the fourth node; A drive transistor that forms a current supply line between the first and second terminals and controls a current flowing through the current supply line in accordance with the potential of a control terminal connected to the second node; The first switch connected to the node and the second switch A second switch connected between the first node and the third node; a third switch connected between the first node and the fixed potential; a data switch connected to the data line; A fourth switch connected between the fourth node and a node,
- the first switch is complementary to the non-emission period of the electro-optical element.
- a driving circuit for holding the third switch in a conductive state while keeping the third switch in a non-conductive state for holding the third switch in a conductive state while keeping the third switch in a non-conductive state.
- an electro-optical element in which luminance changes according to a flowing current, a data line to which a data signal corresponding to luminance information is supplied, and the following: And a fourth node; first and second reference potentials; a pixel capacitor connected between the second node and the second node; a second node and the second node; A current supply line is formed between the ⁇ terminal and the second terminal, and a current supply line is formed between the ⁇ terminal and the second terminal according to the potential of the control terminal connected to the second node.
- the first switch, the third node, the current supply line of the driving transistor, the second node, and the electro-optical element are connected in series between the first reference potential and the second reference potential.
- a driving method of the pixel circuit wherein the first switch is held in a conductive state, the fourth switch is held in a non-conductive state, and the third switch is turned on. The first switch is connected to a fixed potential, the second switch and the fifth switch are held in a conductive state, and the first switch is held in a non-conductive state.
- Switch 2 and the switch 5 above are not connected. After the data transmitted through the data line is input to the fourth node, the fourth switch is turned off, and the fourth switch is turned off. Hold, and keep the third switch in a non-operating state to electrically disconnect the first node from the fixed potential.
- an electro-optical element whose luminance changes according to a flowing current, a data line to which a data signal according to luminance information is supplied, first, second, third, and And a fourth node; first and second reference potentials; a pixel capacitor connected between the first node and the second node; a second node and the fourth node; A current supply line is formed between the first terminal and the second terminal, and a current supply line is formed between the first terminal and the second terminal, and the current supply line is formed according to the potential of the control terminal connected to the second node.
- a drive transistor for controlling a current flowing through a current supply line a first switch connected to the third node; and a second switch connected between the second node and the third node.
- a third switch connected between the first node and the fixed potential; a fourth switch connected between the data line and the fourth node; A fifth switch connected between the node No. 4 and a predetermined potential, and
- the third switch, the third node, the current supply line of the drive transistor, the third node, and the electro-optical element are connected in series between the first reference potential and the second reference potential.
- the third switch and the fourth switch are kept in a non-conductive state
- the third switch is kept in a conductive state
- the first node is connected to a fixed potential
- the second node is connected to the second node.
- the second switch and the fifth switch are kept in a non-conductive state. Holding the fourth switch in a conductive state and inputting the data transmitted through the data line to the fourth node, and then holding the fourth switch in a non-conductive state;
- the first node is electrically disconnected from the fixed potential by holding the switch in a non-conductive state.
- an electro-optical element whose luminance changes according to a flowing current, a data line to which a data signal corresponding to luminance information is supplied, first, second, third, and A fourth node; first and second reference potentials; a pixel capacitor connected between the first node and the second node; a second node and the fourth node; A current supply line is formed between the first terminal and the second terminal, and the current supply line is formed in accordance with the potential of the control terminal connected to the second node.
- a drive transistor for controlling the current flowing through the supply line a first switch connected to the third node, and a second switch connected between the second node and the third node
- a third switch connected between the first node and the fixed potential
- a fourth switch connected between the data line and the fourth node
- a fifth switch connected between the fourth node and a predetermined potential
- a fifth switch connected between the first reference potential and the second reference potential.
- the fourth switch In a state in which the fourth switch is held in a non-conductive state, The second switch and the fifth switch are maintained in a conductive state, the first switch is maintained in a non-conductive state, while the third switch is maintained in a conductive state, and the third node is connected to the third switch.
- the second switch and the fifth switch are kept in a non-conducting state, the fourth switch is kept in a conducting state, and the data transmitted through the data line is transferred to the fourth switch.
- the fourth switch After the input to the third node, the fourth switch is kept in a non-conducting state, the second switch is kept in a conducting state, and the third switch is kept in a non-conducting state.
- Node 1 is electrically disconnected from the fixed potential.
- the first switch when the electro-optical element emits light, the first switch is kept in the on state (conductive state), and the second to fifth switches are kept in the off state (non-conductive state). You.
- the drive (drive) transistor is designed to operate in the saturation region, and the current I ds flowing through the electro-optical element takes a value represented by the above equation (1).
- the third switch is turned on while the first switch is kept on, the second switch, the fourth switch, and the fifth switch are kept off.
- the current flows through the third switch, and the source potential of the drive transistor falls to, for example, the ground potential GND. Therefore, it is applied to the electro-optical element.
- the applied voltage is also ov, and the electro-optical element does not emit light.
- the third switch even if the third switch is turned on, the voltage held in the pixel capacitance element, that is, the gate voltage of the drive transistor does not change, so that the current Ids is equal to the first switch, the third node, and the drive. Flows through the transistor, the third node, and the third switch.
- the second switch and the fifth switch are turned on while the third switch is kept on and the fourth switch is kept off, and the first switch is turned on. Turn off the switch.
- the drive transistor since the gate and the drain of the drive transistor are connected via the second switch, the drive transistor operates in the saturation region. Further, since the pixel capacitor and the coupling capacitor are connected in parallel to the gate of the drive transistor, the gate-drain voltage V gd gradually decreases with time. After a lapse of a predetermined time, the gate-source voltage Vgs of the drive transistor becomes the threshold voltage Vth of the drive transistor.
- the coupling capacitance element is charged with (Vofs-Vth), and the pixel capacitance element is charged with Vth.
- the second and fifth switches are turned off and the third switch is turned on until the third switch is kept on and the fourth switch is kept off.
- the drain voltage of the drive transistor becomes the first reference potential, for example, the power supply voltage.
- the fourth switch is turned on while the third and first switches are kept on, and the second and fifth switches are kept off.
- the input voltage propagated through the data line via the fourth switch is input, and the voltage change AV of the fourth node is coupled to the gate of the drive transistor.
- the gate voltage V g of the drive transistor is V th
- the coupling amount AV is determined by the capacitance value C 1 of the pixel capacitance element, the capacitance value C 2 of the coupling capacitance element, and the parasitic capacitance C 3 of the drive transistor.
- the fourth switch is turned off and the third switch is turned off while the first switch is kept on, the second and fifth switches are kept off.
- the drive transistor since the gate-source voltage of the drive transistor is constant even when the third switch is turned off, the drive transistor allows a constant current Ids to flow through the electro-optical element. As a result, the potential of the first node rises to the voltage Vx at which the current Ids flows through the electro-optical element, and the EL element emits light.
- the current-voltage (I-V) characteristics of the electro-optical element change as the emission time becomes longer. Therefore, the potential of the first node also changes.
- the gate-source voltage V gs of the drive transistor is kept constant, the current flowing through the electro-optical element does not change. Therefore, even if the I-V characteristic of the electro-optical element deteriorates, the constant current I ds always flows, and the luminance of the electro-optical element does not change.
- FIG. 1 is a block diagram showing a configuration of a general organic EL display device.
- FIG. 2 is a circuit diagram showing one configuration example of the pixel circuit of FIG.
- FIG. 3 is a diagram showing the change over time of the current-voltage (IV) characteristics of the organic EL device.
- FIG. 4 is a circuit diagram showing a pixel circuit in which the P-channel TFT of the circuit of FIG. 2 is replaced with an n-channel TFT.
- FIG. 5 is a diagram showing operating points of a TFT and an EL element as drive transistors in an initial state.
- FIG. 6 is a diagram showing the operating points of the TFT and the EL element as the drive transistor after aging.
- FIG. 7 is a circuit diagram showing a pixel circuit in which a source of an n-channel TFT as a drive transistor is connected to a ground potential.
- FIG. 8 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the first embodiment.
- FIG. 9 is a circuit diagram showing a specific configuration of the pixel circuit according to the first embodiment in the organic EL display device of FIG.
- 10A to 10D are timing charts for explaining a first driving method of the circuit in FIG.
- FIGS. 11A and 11B are diagrams for explaining the operation of the circuit of FIG. 9 according to the first driving method.
- FIG. 2A and FIG. 2B are diagrams for explaining the operation of the circuit of FIG. 9 according to the second driving method.
- FIG. 13A and FIG. 13B are diagrams for explaining the operation of the circuit of FIG. 9 according to the first driving method.
- FIGS. 14A and 14B are diagrams for explaining the operation of the circuit of FIG. 9 according to the first driving method.
- FIGS. 15E to 15D are evening charts for explaining the second driving method of the pixel circuit in FIG.
- Figure 16A and Figure 16B show the first and second driving methods for the pixel circuit in Figure 9. It is a figure for comparing and explaining the effect of the method. .
- 17A to 17D are evening charts for explaining a third driving method of the pixel circuit in FIG.
- FIGS. 18A and 18B are diagrams for explaining the operation of the circuit of FIG. 9 according to the third driving method.
- FIGS. 19A and 19B are diagrams for explaining the operation of the circuit of FIG. 9 according to the third driving method.
- FIGS. 2A and 2OB are diagrams for explaining the operation of the circuit of FIG. 9 according to the third driving method.
- FIGS. 21A and 21B are diagrams for explaining the operation of the circuit of FIG. 9 according to the third driving method.
- FIGS. 22A to 22D are evening charts for explaining the method # 4 of driving the pixel circuit of FIG.
- FIG. 23 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the second embodiment.
- FIG. 24 is a circuit diagram showing a specific configuration of a pixel circuit according to the second embodiment in the organic EL display device of FIG.
- FIGS. 25A to 25D are timing charts for explaining a method of driving the circuit of FIG. 24.
- FIGS. 26A and 26B are diagrams for explaining the operation according to the driving method of the circuit in FIG. 24.
- FIGS. 27A and 2.7B are diagrams for explaining the operation according to the driving method of the circuit of FIG.
- FIG. 28 is a diagram for explaining an operation according to the method of driving the circuit of FIG.
- FIG. 29 is a project diagram showing a configuration of an organic EL display device employing the pixel circuit according to the third embodiment.
- FIG. 30 is a circuit diagram showing a specific configuration of the pixel circuit according to the third embodiment in the organic EL display device of FIG.
- FIG. 31 is a timing chart for explaining a method of driving the circuits of FIGS. 31A to 31C and FIG. 30.
- FIG. 32 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the fourth embodiment.
- FIG. 33 is a circuit diagram showing a specific configuration of a pixel circuit according to the fourth embodiment in the organic EL display device of FIG.
- FIG. 34 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the fifth embodiment.
- FIG. 35 is a circuit diagram showing a specific configuration of a pixel circuit according to the fifth embodiment in the organic EL display device of FIG.
- FIG. 36 is a block diagram illustrating a configuration of an organic EL display device employing the pixel circuit according to the sixth embodiment.
- FIG. 37 is a circuit diagram showing a specific configuration of a pixel circuit according to the sixth embodiment in the organic EL display device of FIG. BEST MODE FOR CARRYING OUT THE INVENTION
- FIG. 8 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the first embodiment.
- FIG. 9 is a circuit diagram showing a specific configuration of the pixel circuit according to the first embodiment in the organic EL display device of FIG.
- the display device 100 has a pixel array section 102 in which pixel circuits (PXLC) 101 are arranged in an mxn matrix, and a horizontal selector.
- HSEL Light Scanner
- WSCN Light Scanner
- DSCN 1 1st Drive Scanner
- DSCN 2 2nd Drive Scanner
- AZRD Auto Zero Circuit
- Horizontal Selector Data line DTL 10] to DTL 10 n to which a data signal is supplied according to luminance information selected by 103, scanning line WSL to be selectively driven by light scanner 104] 0 to WSL] 0m
- 1st Drive line selectively driven by 05 DSL 101 to DSL 10 ms Drive line selectively driven by second drive scanner 106
- FIG. 9 also shows a specific configuration of one pixel circuit for simplification of the drawing.
- the pixel circuit 101 includes n-channel TFTs 111 to TFT 116, capacitors C111, C] 22, an organic EL element (0 LED: electro-optical element) consisting of:] 7, the second node ND ⁇ ], the second ND] 12, the third node ND 1] 3, and the fourth node ND 1 14 Yes 0
- DTL 101 indicates a data line
- WSL 101 indicates a scanning line
- DSL 101 and DSL 111 indicate a driving line
- AZL 101 indicates an auto-zero line.
- the TFT 1 constitutes the field effect transistor (drive transistor) according to the present invention
- the TFT 2] constitutes the second switch
- the TFT 113 constitutes the second switch.
- the switches, TFT 114 constitutes a third switch
- TFT 115 constitutes a fourth switch
- TFT 116 constitutes a fifth switch.
- the capacitor C 111 forms a pixel capacitance element according to the present invention
- the capacitor CI 12 forms a coupling capacitance element according to the present invention.
- the supply line (power supply potential) of the power supply voltage VCC corresponds to the reference potential of the [I]
- the ground potential GND corresponds to the second reference potential
- a first switch T is connected between a first reference potential (power supply potential VCC in the present embodiment) and a second reference potential (ground potential GND in the present embodiment).
- An FT 112, a third node ND 113, a TFT 111 as a drive transistor, a first node ND 11, and a light emitting element (OLED) 117 are connected in series. Specifically, the power source of the light emitting element # 17 is connected to the ground potential GND, the anode is connected to the first node # 1, and the source of the TFT] is connected to the first node.
- the drain of the TFT 111 is connected to the node NE 111, the drain of the TFT 111 is connected to the third node ND ⁇ 3, and the source / drain of the TFT 112 is connected between the third node ND 113 and the power supply potential VCC. Is connected.
- the gate of the TFT 111 is connected to the second node ND 112, and the gate of the TFT 112 is connected to the drive line DSL 111.
- the source / drain of TFT 13 is connected between the second node ND 1 12 and the third node 13, and the gate of TFT 113 is connected to the auto-zero line AZL 0 I have.
- the drain of the TFT 114 is connected to the first node ⁇ 1 and the first electrode of the capacitor C 111, and the source is connected to a fixed potential (in this embodiment, to the ground potential GNEO, and the gate of the TFT 114 is connected to the drive line It is connected to DSL 101. Also, the second electrode of the capacitor CI 11 is connected to the second node ND 1 12. The first electrode of the capacitor C 1 12 is connected to the second node ND 1 12 And the second electrode is connected to the fourth node ND1] 4.
- the data line DTL] 0] and the fourth node # 14 are connected to the source and drain of FT FT 1] 5 as the fourth switch, respectively.
- TFT 1 1 The gate of No. 5 is connected to the scanning line WSL101.
- the source and the drain of the TF 16 are connected between the fourth node ND 11 and the predetermined potential Vo fs.
- the gate of the TFT 116 is connected to the auto-zero line AZL] 0].
- the pixel circuit according to the present embodiment] 01 is connected between the gate and source of the TFT 11 1 as a drive transistor, and is connected to a capacitor C 11 1 as a pixel capacitance, and is used in a non-light emitting period.
- the source potential of the TFT 111 is connected to a fixed potential via the TFT 114 as a switch transistor, and the gate-drain of the TFT 111 is connected to It is configured to perform the correction.
- FIG. 10A shows the scanning signal ws [1] applied to the scanning line WSL 101 of the pixel array in the first row
- FIG. 10B shows the driving line DSL 1 in the first row of the pixel array
- FIG. 10C shows the driving signal ds [1] applied to the pixel array 01
- FIG. 10C shows the driving signal ds [2] applied to the driving line DSL 11 1 in the first row of the pixel array
- FIG. 10D shows the pixel array
- a period indicated by Te is a light emitting period
- a period indicated by Tne is a non-light emitting period
- Tvc is a canceling period of the threshold Vth
- Tw is The period shown is the writing period.
- the scanning signal ws [1] from the light scanner 104 to the scanning line WSL 101 is set to low level, as shown in FIGS. 108 to 10D.
- the drive signal ds []] to the drive line DSL 101 is set to low level by the drive scanner 105, and the auto-zero signal az [1] to the auto-zero line AZL] 0] is output by the auto-zero circuit] 07. Is set to one level, and the drive signal ds [2] Selectively set to high level.
- the TFT 112 is kept in the ON state (conductive state), and the TFTs 113 to 116 are kept in the OFF state (non-conductive state).
- the drive transistor 111 is designed to operate in the saturation region, and the current I ds flowing through the EL light emitting element 17 takes a value represented by the above formula.
- the scanning signal ws [1] from the light scanner 04 to the scanning line WSL 10] is held at a low level.
- the auto-zero signal az [1] to the auto-zero line AZL 101 is held at a low level by the auto-zero circuit 107, and the drive signal ds [2] to the drive line DSL 11 1 is set to a high level by the drive scanner 106.
- the drive signal ds [1] to the drive line DSL 101 is selectively set to the high level by the drive scanner 105.
- the TFT 112 is turned on, the TFT 113, the TFT 115, and the TFT 116 are kept off, and the TFT 114 is turned off. Turn on.
- the voltage applied to the EL light emitting elements 1 to 7 is also 0 V, and the EL light emitting element 117 does not emit light.
- the TFT 114 even when the TFT 114 is turned on, the voltage held in the capacitor C 1] 1, that is, the gate voltage of the TFT 11 1 does not change, so that the current I ds is as shown in FIG. 11B. Then, it flows through the path of the TFT1 12, the third node ND1 13, the TFT111, the first node ND11K and the TFT114.
- the scanning signal ws [1] from the light scanner 104 to the scanning line WSL 101 is held at a low level.
- Drive line DSL 1 by drive scanner 105 With the drive signal ds [1] to 01 held at the high level, the auto-zero circuit 107 sets the auto-zero signal az [1] to the auto-zero line AZL 101 to the high level, and then, as shown in FIG.10C
- the drive scanner 106 sets the drive signal ds [2] to the drive line DSL 111 to a low level.
- the TFT.114 while the TFT.114 is kept in the ON state and the TFT 115 is kept in the OFF state, the TFT113, the TFT 116 is turned on, and the TFT1 2 turns off.
- the gate and the drain of the TFT 111 are connected via the TFT 113, so that the TFT 111 operates in the saturation region.
- the capacitances CI 11 and C 1 12 are connected in parallel to the gate of the TFT 11, the gate-drain voltage Vgd of the TFT 11 1 With this, it gradually decreases. After a lapse of a predetermined time, the gate-source voltage Vgs of the TFT 1111 becomes the threshold voltage Vth of the TFT 1111.
- the scanning signal ws [1] to the scanning line WSL 101 from the light scanner 104 is held at a low level, and the driving signal to the driving line DSL 101 by the drive scanner 105.
- the drive signal ds [2] to the drive line DSL 11 1 1 is held at the mouth level by the drive scanner 106
- the auto-zero circuit A ZL 101 The drive zero signal az [1] is set to low level, and then the drive signal ds [2] to the drive line DSL]] 1 is set to high level by the drive scanner 06 as shown in FIG. 10C. Is set.
- the TFT 114 is turned on, the TFT 115 is kept off, the TFT 113, the TFT 116 is turned off, and the TFT 112 is turned off. Turn on. As a result, the TFT 111 Pin voltage becomes the power supply voltage V CC.
- the drive signal ds [1] to the drive line DSL 101 is held at a high level by the drive scanner 105, and the drive line DSL 11 1 is held by the drive scanner 106. While the drive signal ds [2] to 1 is held at a high level and the auto-zero signal az [1] to the auto-zero line AZL 101 is held at a low level by the auto-zero circuit 107, the light scanner 104 The scanning signal ws [1] to the scanning line WSL 101 is set to the high level.
- the TFTs 114 and TF 112 are turned on, the TFT 13 and the TFT 116 are kept off, and the TFT 115 Turns on.
- the input voltage V in transmitted through the data line DTL 101 via the TFT 115 is input, and the voltage change of the node ND] 4 is coupled to the gate of the TFT]].
- the gate voltage Vg of the TFT 111 is Vth, and the amount of coupling is the capacitance C 1 of the capacitor C 111, the capacitance C 2 of the capacitor C 112, and the TFT 111. Is determined by the parasitic capacitance C3 of 1 as shown in Equation 2 below. ⁇
- the current I ds according to the amount of voltage coupled to the gate of the TFT 111 is Flows.
- the drive signal ds [2] to the drive line DSL]]] is held at a high level, and the auto-zero signal az [1] to the auto-zero line AZL 101 is held at a low level by the auto-zero circuit 107.
- the scanning signal ws [1] to the scanning line 1 WSL] 01 from the light scanner 104 is set to low level, and then the driving signal ds [1] to the driving line DSL 101 is set to low level by the drive scanner 105. Is determined.
- the TFT 112 is turned on, the TFTs 113 and 116 are kept off, the TFT 115 is turned off, and the TFT 114 is turned off. .
- the TFT 111 since the gate-source voltage of the TFT 111 is constant even when the TFT 111 is turned off, the TFT 111 flows a constant current Ids to the EL light emitting element 117. Thus, the potential of the first node ND111 rises to the voltage Vx at which the current Ids flows through the EL element 117, and the EL element 117 emits light.
- the current-voltage (I-V) characteristics of the EL light-emitting element change as the light-emitting time becomes shorter. Therefore, the potential of the node ND] 1] also changes.
- the gate-source voltage Vgs of the TFT 111 is kept constant, the current flowing through the EL element 117 does not change. Therefore, even if the I-V characteristic of the EL element 17 deteriorates, the constant current Ids always flows, and the luminance of the EL element 117 does not change.
- This second driving method is different from the above-described first driving method in the timing of turning on the TFT 112 as the first switch in the non-light emitting period Tne.
- the timing at which the TFT 112 is turned on is set after the TFT 115 is turned off.
- the TFT 111 operates from the linear region to the saturated region as shown in FIG. 16A.
- the TFT 115 when the TFT 115 is turned on after the TFT 112 is turned on as in the first driving method described above, the TFT 111 operates only in the saturation region as shown in FIG. 16B. Since the channel length of the transistor is shorter in the saturation region than in the linear region, the parasitic capacitance C 3 is small.
- the parasitic capacitance C 3 of the TFT 111 can be made smaller than turning on 2 o
- the parasitic capacitance C 3 can be reduced, the amount of coupling from the drain to the gate of TF T 1]] can be reduced when the TFT 112 is turned on, and the capacity of the capacitor C 111 can be reduced. Since the capacitance value C 1 and the capacitance value C 2 of the capacitance C 1 12 can be made sufficiently larger than the parasitic capacitance C 3, the voltage of the fourth node ND 114 when the TFT 115 is turned on can be reduced. The change amount is coupled to the gate of the TFT 11 1 according to the magnitudes of C l and C 2.
- the first driving method is better than the second driving method.
- the third driving method is different from the first driving method described above in the timing of turning on the TFT 112 as the first switch in the non-light emitting period Tne.
- the TFT 112 functions as a duty switch. The operation will be described below.
- a scanning signal ws [1] from the light scanner 104 to the scanning line WSL 101 is used. Is set to the low level, the drive signal ds (1) to the drive line DSL 101 is set to the mouth level by the drive scanner 105, and the auto-zero circuit 107 sets the auto-zero signal az to the AZL 101 to the auto-zero line az [1] is set to a low level, and the drive signal ds [2] to the drive line DSL 11 1 is selectively set to a high level by the drive scanner 106.
- the TFT 112 is kept in the ON state (conductive state), and the TFT 113-TFT 116 is in the OFF state (non-conductive state). Is held.
- the drive transistor 1.1 is designed to operate in the saturation region, and the current I ds flowing through the EL light emitting element 117 takes the value shown by the above equation (1).
- the scanning signal ws [1] from the light scanner 104 to the scanning line WSL 101 becomes low level.
- the auto-zero signal az [1] to the auto-zero line AZL101 is held at a low level by 07, and the drive signal ds [1] to the drive line DSL 101 by the drive scanner 105 is held. Is held at the low level, the drive scanner 106 sets the drive signal ds [2] to the drive line DSL 111 at the low level.
- the TFTs 113 to 116 are turned off while the TFTs 113 to 116 are kept off.
- the drain voltage of the TFT 1] 1 drops to the source voltage.
- no current flows through the EL light emitting element 17 and the potential of the first node ND 111 drops to the threshold voltage Ve of the EL light emitting element. Then, the EL element 117 does not emit light.
- the scanning signal ws [1] from the light scanner 104 to the scanning line WSL 101 becomes low level.
- the drive signal ds [1] to the drive line DSL101 is set to high level by 105, and then the autozero line AZL101 to the autozero line AZL101 by the autozero circuit 107 as shown in Fig.17D.
- az [1] is set to high level.
- the TFT 114 is turned on, and the TFT 113 and the TFT 111 are turned on. 6 turns on.
- the potential of the first node ND 111 becomes the ground potential GND level, and the drain voltage of the TFT 111 also becomes the ground potential GND level.
- the potential change of the fourth node ND 114 is coupled to the gate of the TFT 111 through the capacitor C 2, and the TFT 113 is turned on.
- the gate-drain voltage Vg d of 1 changes. This force coupling amount is defined as V0.
- the timing of turning on the TFT 114, the TFT 113, and the TFT 116 may be such that the TFT 114 is turned on after the TFT 113, TFT 116 is turned on.
- the gate and drain of the TFT 111 are connected to each other and the amount of potential change at the fourth node ND 114 is coupled to the gate of the TFT 111, the gate of the TFT 111 is connected to the ground potential GND level. May be lowered.
- the scanning signal ws [1] to the scanning line W SL 101 from the light scanner 104 is held at a low level, and the driving line
- the drive scanner ds [1] to the DSL] 0] is held at a high level
- the auto-zero signal az [1] to the auto-zero line AZL101 is held at a high level by the auto-zero circuit 107.
- the drive signal ds [2] to the flow line DSL 1 1 1 is set to high level.
- the TFTs 114, TFT 113, and TFT 1.16 are turned on, and the TFTs 1 and 2 are turned on while the TFTs 1 and 5 are kept off.
- the gate-drain voltage of the TFT]] increases to the power supply voltage VCC.
- the drive signal d s [2] to the drive line DSL 111 is set to the low level by the drive scanner 106 as shown in FIG. 17C.
- the TFTs 114, TFT 113, and TFT] 16 are on, the TFT] 5 is kept off, and the TFT 12 is off. I do.
- the gate-source voltage Vgs of the TFT 11 becomes the threshold voltage V th of the TFT 11.
- the scanning signal ws [1] to the scanning line WSL ⁇ 01 is held at a low level from the light scanner 104, and the driving scanner 105 drives the scanning line ws [1] to the driving line DSL 101.
- the signal ds []] is held at a high level and the drive signal ds [2] to the drive line liSL 1 11 is held at a low level by the drive scanner 106
- the auto-zero circuit 107 sets the auto-zero line A ZL 101.
- the auto-zero signal az [1] is set to a low level, and then the drive signal ds [2] to the drive line: DSL 1] 1 is set to a high level by the drive scanner 106.
- the TFT 113 and the TFT 116 are turned off and the TFT 112 is turned on while the TFT 14 is kept in the on state.
- the drain voltage of the TFT 111 becomes the power supply voltage again.
- the drive signal ds [1] to the drive line DSL 101 is held at a high level by the drive scanner 105, and the drive line 106 is driven by the drive scanner 106.
- the drive signal ds [2] to the DSL 1 1 1 is held at a high level, and the auto-zero signal az [1] to the auto-zero line AZL] 0] is held at a low level by the auto-zero circuit] 07.
- the scanning signal ws [1] from Tosgiana 104 to the scanning line WSL 101 is set to high level.
- the TFT 114 and the TFT 112 are kept in the on-state, and the TFT 113 and the TFT 116 are kept in the off-state.
- TFT 1 15 turns on.
- the input voltage Vi II propagated through the data line DTL 101 via the TFT 115 is input, and the voltage change ⁇ at the node ND 114 is coupled to the TFT 11 1 gate. Let it.
- the gate voltage Vg of the TFT 11 1 has a value of V th, and the amount of cutting ⁇ is the capacitance C 1 of the capacitor C 11, the capacitance C 2 of the capacitor 11 2, and the TFT 11 1 Is determined by the parasitic capacitance C 3 of Equation 2 above
- the drive signal ds [2] to the drive line DSL 11 1 is held at the high level by the drive scanner 106 and the auto-zero circuit 107 Auto-zero line AZL 101 With the auto-zero signal az [1] to 011, held at a low level, the scanning line WSL from the light scanner 104 The scanning signal ws [1] to 101 is set to low level, and then the drive signal 105 to the drive line DSL 101 is set to low level by the drive scanner 105.
- the TFT]] 2 is in the ON state, and the TFTs 113 and 16 are kept in the OFF state. 5 turns off and TFT 1 1 4 turns off.
- the gate-source voltage of the TFT 111 is constant, so that the TFT 111 flows a constant current I ds to the EL light emitting element 107.
- the potential of the first node ND111 rises to the voltage Vx at which the current Ids flows through the EL element 117, and the EL element 117 emits light.
- the current-voltage (I-V) characteristics of the EL light-emitting element change as the light-emitting time increases. Therefore, the potential of the first node ND111 also changes.
- the gate-source voltage Vgs of the TFT 111 is kept at a constant value, the current flowing through the EL element 117 does not change. Therefore, even if the I-V characteristic of the EL element 117 is degraded, the constant current Ids always flows, and the luminance of the EL element 117 does not change.
- the above is the third driving method of the pixel circuit in FIG. 9. As shown in FIGS. 22A to 22D, the timing for turning on the TFT 112 is set after the TFT 115 is turned off. It is also possible to adopt the fourth driving method.
- the TFT 111 operates from the linear region to the saturated region.
- the TFT 112 when the TFT 112 is turned on and then the TFT 115 is turned on as in the third driving method described above, the TFT 111 operates only in the saturation region.
- the transistor has a smaller parasitic capacitance C 3 in the saturation region than in the linear region, so the parasitic capacitance C 3 is small.
- the TFT 1 1 5 is turned on before the TFT 1 1 5 Turning on the TFT can reduce the parasitic capacitance C3 of the TFT 111, as compared with turning off the TFT 115 and then turning on the TFT 112 as in the fourth driving method.
- the parasitic capacitance C 3 can be reduced, the amount of coupling from the drain to the gate of the TFT 111 can be reduced when the TFT 112 is turned on, and the capacitance of the capacitor C 111 can be reduced. Since the capacitance C 2 of the value C 1 and the capacitance C 1 12 can be made sufficiently larger than that of C 3, the amount of change in the voltage of the fourth node ND 1 14 when the TFT 1 15 is turned on is Depending on the size of C 1 and C 2, it will be coupled to the TFT 111 gate.
- the third driving method is better than the fourth driving method.
- the voltage driving type TFT active matrix organic EL device In the display, a capacitor C 11 1 is connected between the gate and the source of TFT 11 1 as a drive transistor, and the source side (the first node ND 1) 1 of TFT 11 1 is connected to a fixed potential through TFT 114. (In this embodiment, GND).
- the gate and the drain of the TFT 111 are connected via the TFT 113 to cancel the threshold value Vth, and the capacity is set to the capacity CI 11. Since the configuration is such that the threshold voltage Vth is charged and the input voltage Vin is applied to the gate of the TFT 111 from the threshold voltage Vth, the following effects can be obtained. it can.
- the threshold voltage of the TFT 1111 as a drive transistor can be easily canceled, variation in the current value of each pixel can be reduced, and uniform image quality can be obtained.
- the timing of each switching transistor By setting the timing of each switching transistor, the value of the current flowing in the pixel during the non-light emitting period can be reduced, and low power consumption can be realized. Also, even if the IV characteristics of the EL light-emitting element change with time, a source follower output without luminance degradation can be performed.
- a source follower circuit of an n-channel transistor becomes possible, and the n-channel transistor can be used as a driving element of an EL light-emitting element while using the current anode and cathode electrodes.
- a transistor of a pixel circuit can be formed using only n channels, and an a-Si process can be used in the manufacture of a TFT. As a result, the cost of the TFT substrate can be reduced.
- FIG. 23 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the second embodiment.
- FIG. 24 is a circuit diagram showing a specific configuration of a pixel circuit according to the second embodiment in the organic EL display device of FIG.
- the difference between the second embodiment and the above-described second embodiment is that the drive scanner is integrated into one, and the drive signal ws CI applied to the drive line DSL101-DSL10m is changed to the TFT114.
- This is configured so that the inverted signal / ws [1] of the drive signal ws [1] is supplied to the gate of the TFT 112 by the inverter 108-1 and I 08-ni.
- the TFTs 112 and 114 are turned on and off complementarily. That is, when TFT 112 is on, TFT 114 is held off, and when TFT 112 is off, TFT 111 is held on.
- the operation of the second embodiment will be described with reference to FIGS. 25A to 25D and FIGS. 26A, B, 27A, B, and 28.
- the scanning signal ws [1] from the light scanner 104 to the scanning line WSL 101 is set to low level.
- the drive signal ds [1] is set to a low level, and the auto-zero circuit a07 sets the auto-zero signal az [1] to the auto-zero line AZL 101 to a low level.
- the TFT 112 is kept in the ON state (conductive state) and the TFTs 113 to 116 are kept in the OFF state (non-conductive state). Is done.
- the drive transistor]] is designed to operate in the saturation region, and the current ⁇ d s flowing through the EL light emitting element 117 takes a value represented by the above equation ⁇ .
- the scanning signal ws [1] from the light scanner 104 to the scanning line WSL 101 is at a low level.
- the drive signal ds [1] to the drive line DSL 101 is held at a low level by the drive scanner 105 and the auto-zero signal az []] to the auto-zero line AZL] 0] by the auto-zero circuit 107 Is set to high level.
- the TFT 112 is turned on, the TFT] 4 and the TFT 100 are kept off, and the TFT 113 and the TFT 116 are kept in the off state. Turns on.
- the drain and gate of the TFT 111 are connected, and the voltage rises to the power supply voltage. Further, when the TFT 16 turns on, the potential change of the fourth node ND 114 is coupled to the gate of the TFT 111 through the capacitor 12, and between the gate and the drain of the TFT 111. The voltage Vg d changes.
- the scanning signal ws [1] to the scanning line WSL 101 from the light scanner 104 is held at a low level, and the auto-zero circuit 107 executes the auto-zero signal to the auto-zero line AZL 101.
- the az CD held at a high level, drive scanner 105 connects to drive line DSL 101
- the drive signal dsn is set to high level.
- the TFT 114, the TFT 113, and the TFT 116 are kept in the ON state, and the TFT 121, and the TFT 115 are kept in the OFF state.
- the potential of the first node ND111 drops to the ground potential GND level. Further, after a certain period of time, the gate-source voltage Vgs of the TFT 1111 becomes the threshold voltage Vth of the TFT 1111.
- the scanning signal ws [1] to the scanning line WSL 101 from the light scanner 104 is held at a low level, and the driving line DSL 101 With the drive signal ds [1] to the high level, the auto-zero signal az [1] to the auto-zero line AZL101 by the auto-zero circuit 107 is set to low level, and then the light scanner 104 Accordingly, the scanning signal ws [1] to the scanning line WSL101 is set to the high level.
- the TFT 114 and the TFT 116 remain off while the TFT 114 and the TFT 112 are kept on and off. Then, the TFT 115 turns on.
- the input voltage Vin propagated through the data line DTL 101 via the TFT 115 is input, and the voltage change ⁇ V at the node ND 114 is coupled to the gate of the TFT 1! .
- the coupling amount ⁇ to the TFT 111 is the capacitance C 1 of the capacitor C 111 and the capacitance C of the capacitor C 112. Only depends on 2.
- the auto-zero signal az [1] to the auto-zero line AZL101 is maintained at the mouth level by the auto-zero circuit 107 as shown in Figs.25A to 25D.
- the scanning signal ws [1] to the scanning line WSL 101 from the light scanner 104 is set to low level, and then the driving signal ds [1] to the driving line DSL 101 by the drive scanner 105 goes low. Set to level.
- the TFTs 113 and 116 are kept off, the TFTs 15 and 114 are turned off and the TFT 112 is turned on. .
- the drain voltage of the TFT 111 rises to the power supply voltage.
- the gate-source voltage of the TFT 1111 is constant, so that the TFT 111 flows a constant current Ids to the EL light emitting element # 17.
- the potential of the first node ND111 rises to the voltage Vx at which the current Ids flows through the EL element 17 and the EL element 117 emits light.
- the current-voltage (IV) characteristics of the EL light-emitting element change as the light-emitting time increases. Therefore, the potential of the first node ND111 also changes.
- the gate-source voltage Vgs of the TFT 111 is kept constant, the current flowing through the EL element 117 does not change. Therefore, even if the I-V characteristics of the EL element 17 deteriorate, the constant current Ids always flows, and the luminance of the EL element 17 does not change.
- the threshold voltage of the drive transistor TFT 111 can be easily canceled, so that the variation in the current value of each pixel can be reduced, and the uniform image quality can be obtained. Obtainable.
- the value of the current flowing in the pixel during the non-light emitting period can be reduced, and low power consumption can be realized.
- the lower source circuit of the n-channel transistor becomes possible, and the current
- the n-channel transistor can be used as a driving element of the EL light emitting element while the cathode electrode is used.
- a transistor of a pixel circuit can be configured with only n channels, and an a-Si process can be used in TFT creation. As a result, the cost of the TFT substrate can be reduced.
- FIG. 29 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the third embodiment.
- FIG. 30 is a circuit diagram showing a specific configuration of a pixel circuit according to the third embodiment in the organic EL display device of FIG.
- the display device 100B according to the third embodiment is different from the display device 100A according to the second embodiment in that the TFT 112 as the first switch in the pixel circuit is replaced with an n-channel TFT. In that a P-channel TFT] 12B was applied. In this case, since it is only necessary that the TFTs 112B and TFT114 be turned on and off in a complementary manner, each line as shown in FIG. 31A to FIG. It is only necessary to apply only the drive signal d s [1] to the book drive DSL 1 0] to DSL 1 Om.
- FIG. 32 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the fourth embodiment.
- FIG. 33 is a circuit diagram showing a specific configuration of a pixel circuit according to the fourth embodiment in the organic EL display device of FIG.
- TFT11 is replaced by P-channel TFT11C.
- the anode of the light emitting element 117 is connected to the power supply potential VCC
- the cathode is connected to the first node DN 111
- the source of the TFT] 11 C is connected to the first node ND 111
- the TFT 111 is connected.
- the drain of C is connected to the third node ND113
- the drain of TFT112 is connected to the third node ND113
- the source of TFT112 is connected to the ground potential GND.
- the TFT 114 is connected between the first node ND 1] 1 and the power supply potential VCC.
- connection relations are the same as those of the first embodiment, and the operation is performed in the same manner, so that the detailed description is omitted here.
- FIG. 34 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the fifth embodiment.
- FIG. 35 is a circuit diagram showing a specific configuration of a pixel circuit according to the fifth embodiment in the organic EL display device of FIG.
- the difference between the fifth embodiment and the fourth embodiment is that the drive scanner is integrated into one drive line and the drive signal ws [1] applied to the DSL 101 to DSL ⁇ Om Supply to the gate, Imper evening 109— ;! 109109—:
- the configuration is such that the inverted signal / ws [1] of the drive signal ws [1] due to m is supplied to the gate of the TFT 114.
- FIG. 36 is a block diagram showing a configuration of an organic EL display device employing the pixel circuit according to the sixth embodiment.
- FIG. 37 is a circuit diagram showing a specific configuration of a pixel circuit according to the sixth embodiment in the organic EL display device of FIG.
- the display device 100E according to the sixth embodiment is different from the display device 00D according to the fifth embodiment in that a TFT 112 as a first switch in a pixel circuit is replaced with an n-channel TFT.
- a TFT 112 as a first switch in a pixel circuit is replaced with an n-channel TFT.
- p-channel TFT 112D is applied.
- the TFT 112E and the TFT 114 are complementary (the only requirement is that they can be turned on and off; therefore, only the drive signal d s [1] needs to be applied to one drive line DSL 101 to DSL 1 Om in each row.
- the threshold voltage of the TFT 111 serving as the drive transistor can be easily canceled, so that the variation in the current value of each pixel can be reduced, and the uniform image quality can be achieved. Can be obtained.
- a source follower circuit of an n-channel transistor becomes possible, and an II-channel transistor can be used as a driving element of an EL light-emitting element while using the current anode and force source electrodes;
- a transistor of a pixel circuit can be configured with only n channels, and TF A—Si process can be used in T creation. As a result, the cost of the TFT substrate can be reduced.
- the pixel circuit, the display device, and the driving method of the pixel circuit of the present invention even if the current-voltage characteristics of the light-emitting element change with time, it is possible to perform one source-follow output without luminance degradation and to output the n-channel transistor.
- a source-lower circuit is possible, and n-channel transistors can be used as EL driving elements while using the current anode and cathode electrodes, so it can be used as a large, high-definition active matrix display. It is possible.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Control Of El Displays (AREA)
- Electroluminescent Light Sources (AREA)
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
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US10/558,372 US7714813B2 (en) | 2003-06-04 | 2004-06-03 | Pixel circuit, display device, and method for driving pixel circuit |
EP04735969.0A EP1632930B1 (en) | 2003-06-04 | 2004-06-03 | Pixel Circuit, Display Device and Method for Driving Pixel Circuit |
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JP2003159646A JP4062179B2 (ja) | 2003-06-04 | 2003-06-04 | 画素回路、表示装置、および画素回路の駆動方法 |
JP2003-159646 | 2003-06-04 |
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US (1) | US7714813B2 (ja) |
EP (1) | EP1632930B1 (ja) |
JP (1) | JP4062179B2 (ja) |
KR (1) | KR101033674B1 (ja) |
CN (1) | CN100452152C (ja) |
TW (1) | TWI243352B (ja) |
WO (1) | WO2004109639A1 (ja) |
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Also Published As
Publication number | Publication date |
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JP4062179B2 (ja) | 2008-03-19 |
JP2004361640A (ja) | 2004-12-24 |
KR20060026030A (ko) | 2006-03-22 |
US7714813B2 (en) | 2010-05-11 |
TW200428323A (en) | 2004-12-16 |
TWI243352B (en) | 2005-11-11 |
EP1632930A4 (en) | 2009-07-22 |
EP1632930A1 (en) | 2006-03-08 |
KR101033674B1 (ko) | 2011-05-12 |
CN100452152C (zh) | 2009-01-14 |
US20070120795A1 (en) | 2007-05-31 |
EP1632930B1 (en) | 2013-07-31 |
CN1799081A (zh) | 2006-07-05 |
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