WO2004095454A1 - 再生装置および方法 - Google Patents
再生装置および方法 Download PDFInfo
- Publication number
- WO2004095454A1 WO2004095454A1 PCT/JP2004/001918 JP2004001918W WO2004095454A1 WO 2004095454 A1 WO2004095454 A1 WO 2004095454A1 JP 2004001918 W JP2004001918 W JP 2004001918W WO 2004095454 A1 WO2004095454 A1 WO 2004095454A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- signal
- transfer rate
- adjustment information
- output
- synchronization adjustment
- Prior art date
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Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
- G11B7/12—Heads, e.g. forming of the optical beam spot or modulation of the optical beam
- G11B7/14—Heads, e.g. forming of the optical beam spot or modulation of the optical beam specially adapted to record on, or to reproduce from, more than one track simultaneously
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B27/00—Editing; Indexing; Addressing; Timing or synchronising; Monitoring; Measuring tape travel
- G11B27/10—Indexing; Addressing; Timing or synchronising; Measuring tape travel
- G11B27/19—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier
- G11B27/28—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording
- G11B27/30—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording
- G11B27/3027—Indexing; Addressing; Timing or synchronising; Measuring tape travel by using information detectable on the record carrier by using information signals recorded by the same method as the main recording on the same track as the main recording used signal is digitally coded
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
- G11B7/004—Recording, reproducing or erasing methods; Read, write or erase circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B7/00—Recording or reproducing by optical means, e.g. recording using a thermal beam of optical radiation by modifying optical properties or the physical structure, reproducing using an optical beam at lower power by sensing optical properties; Record carriers therefor
- G11B7/007—Arrangement of the information on the record carrier, e.g. form of tracks, actual track shape, e.g. wobbled, or cross-section, e.g. v-shaped; Sequential information structures, e.g. sectoring or header formats within a track
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B2220/00—Record carriers by type
- G11B2220/20—Disc-shaped record carriers
Definitions
- the present invention relates to a reproducing apparatus and method, and is particularly suitable for application to reproduction of a disk-shaped recording medium such as an improved constant angular velocity method.
- MCAV Modified Constant Angular Velocity
- CAV constant angular velocity
- This is a constant angular velocity (CAV) method that emphasizes high-speed access, in which the disk rotation speed is controlled to be constant and the transfer rate for recording and reproduction is set higher as the linear velocity increases.
- CLV constant linear velocity
- Japanese Patent No. 3106750 discloses a reproducing apparatus and a reproducing method of a disk-shaped recording medium having zones of different transfer rates such as the MCAV system.
- the disk-shaped recording medium of the MCAV method has a plurality of zones with different transfer rates, The difference between the outer and outermost transfer rates can be more than three times. For this reason, it is very difficult to reproduce the disk-shaped recording medium of the MCAV system with a single clock reproducing circuit.
- an apparatus for reproducing a disk-shaped recording medium of the MCAV system having a plurality of heads needs to be equipped with a clock extraction circuit for reproducing each head and corresponding to a different transfer rate. Therefore, in the conventional playback device, if signal processing of a wide range of transfer rates is enabled, there are problems that high performance and expensive components are required, the circuit scale is increased, and the cost is increased. Was.
- each transfer rate zone is divided into a high transfer rate zone and a low transfer rate zone. It has been proposed to extract the playback signal by each playback head and perform signal processing so that the sum of the transfer rates is always constant. In this case, there is a problem that a control system for managing the sum of the transfer rates for each zone to be constant becomes complicated.
- an object of the present invention is to provide a clock extraction circuit for reproducing signals obtained simultaneously from a plurality of heads. It is an object of the present invention to provide a reproducing apparatus and a method capable of realizing cost reduction and high speed operation. Disclosure of the invention
- the invention set forth in claim 1 is directed to a first and a second reading means from a disk-shaped recording medium in which data at a high transfer rate and data at a low transfer rate are recorded.
- a reproduction apparatus configured to simultaneously obtain a second reproduction signal, a signal arrangement conversion unit configured to arrange the first reproduction signal and the second reproduction signal in a time-division multiplexed manner, Synchronization adjustment information generating means for generating optimum synchronization adjustment information for each reproduction signal from the second reproduction signal, waveform equalization processing for performing waveform equalization processing on the output of the signal arrangement conversion means, and synchronization adjustment information.
- This is a reproducing apparatus having switching means for switching the characteristics of the waveform equalizing means in response thereto, and a PLL for generating a clock signal according to the synchronization adjustment information.
- the invention according to claim 6 of the present invention is characterized in that the first and second reproduced signals are read from a disk-shaped recording medium on which high-transfer rate data and low-transfer rate data are recorded by a plurality of reading means.
- This is a reproduction method in which the step characteristics are switched, the output signal of the waveform equalization step is input to the PLL, and a clock signal is generated according to the synchronization adjustment information.
- the first reproduced signal and the second reproduced signal are arranged in a time-division multiplexed manner, From the reproduced signal and the second reproduced signal, optimal synchronization adjustment information for each reproduction signal is generated, and the output of the signal arrangement conversion means is subjected to waveform equalization processing, and the characteristics of the waveform equalization are determined according to the synchronization adjustment information.
- FIG. 1 is a schematic diagram showing an example of a configuration of a reproducing apparatus according to an embodiment of the present invention.
- 2A and 2B are schematic diagrams showing an example of the operation of the head.
- 3A to 3D are schematic diagrams illustrating an example of signal arrangement conversion according to an embodiment of the present invention.
- 4A to 4E are schematic diagrams for explaining synchronization control according to an embodiment of the present invention.
- FIGS. 5A and 5B are schematic diagrams showing another example of the operation of the head.
- FIG. 1 shows an example of the configuration of a drive system and a clock extraction circuit of a playback device for a disk-shaped recording medium.
- Reference numeral 1 denotes a disk-shaped recording medium (hereinafter, referred to as a disk) of the MCAV system which reads recorded reproduction signals from both sides of the disk surface.
- the disk 1 is driven to rotate by a spindle motor 2.
- the disc 1 records video signals, audio signals, and the like encoded by the MPEG (Moving Picture Experts Group) 2 system or the like, and has data at a high transfer rate and data at a low transfer rate. I have. Details of these transfer rates will be described later.
- MPEG Motion Picture Experts Group
- a ch head 3 plays the surface of disc 1 and 4 plays back the back of disc 1.
- a ch head 3 and B ch head 4 read high and low transfer rate data.
- the first reproduced signal read by the Ach head 3 is supplied to the preamplifier 5, and the second reproduced signal read by the Behhead 4 is supplied to the preamplifier 6.
- the preamplifier 5 amplifies the second reproduced signal read by the Bch head 4.
- the preamplifier 6 amplifies the first reproduced signal read by the Ach head 3.
- the output signal of the preamplifier 5 and the output signal of the preamplifier 6 are both supplied to the signal arrangement conversion circuit 9 and the address demodulation unit 7.
- the address demodulation unit 7 demodulates address data from the output signal of the preamplifier 5 and detects a track shift and a linear velocity.
- the address demodulator 7 demodulates address data from the output signal of the preamplifier 6 and detects a track shift and a linear velocity.
- Information on each demodulated address data and each detected track shift and linear velocity is supplied to a reproduction control unit 8 and a microcomputer (hereinafter, referred to as a microcomputer) 10.
- the reproduction control unit 8 determines the position of the A-ch head 3 and the B-ch head 4 based on the information of each address demodulated by the address demodulation unit 7 and each detected track shift and linear velocity. Performs feedback control and rotation control of spindle motor 2. These pieces of control information are supplied to the microcomputer 10.
- the signal arrangement conversion circuit 9 arranges and converts output signals from the preamplifiers 5 and 6 on the time axis. Details of this arrangement conversion will be described later.
- the signal that has undergone the layout conversion by the signal layout conversion circuit 9 is stored in a FIFO (First In First ut 0 ut) buffer.
- the signal stored in the FIFO buffer is supplied to the signal processor 27 and clock Supplied to outlet 1 1.
- the microcomputer 10 recognizes the transfer rate based on the arrangement information obtained from the addressless conversion of the signal arrangement conversion circuit 9 and the switching information of the output of the preamplifier, that is, the switching information indicating the evening timing for switching the reproduction output of the two heads. .
- the microcomputer 10 creates optimal synchronization adjustment information based on the recognized transfer rate and various information supplied from the address demodulation unit 7, the reproduction control unit 8, and the signal arrangement conversion circuit 9.
- the synchronization adjustment information created by the microcomputer 10 is supplied to the electronic volume 26.
- the clock extraction unit 11 is an internal signal generation circuit that supports a high transfer rate and a low transfer rate.
- the output signal from the FIFO buffer of the signal arrangement conversion circuit 9 is first supplied to the waveform equalization circuit of the clock extraction unit 11.
- the waveform equalization circuit consists of a high-pass filter (hereinafter, referred to as HPF (High Pass Filter)) section 12, an adder 28, an RF amplifier 13, and a low-pass filter (hereinafter, LPF (Low Pass Filter). ) Section 14 and a binary limiter circuit (LIM) 15.
- HPF High Pass Filter
- LPF Low Pass Filter
- the HP F section 12 has an HP F 12a for a high transfer rate and an HP F 12b for a low transfer rate, and can switch between processing by control of the microcomputer 10. . This control is performed based on synchronization adjustment information based on the various information supplied to the microcomputer 10 described above, for example, transfer rate information and switching information of the output of the preamplifier.
- the output signal of HPF section 12 is supplied to adder 28.
- the adder 28 adds the output signal from the LPF section 14 to the output signal from the HPF section 12.
- the output signal of the adder 28 is amplified by the RF amplifier 13 and supplied to the binary limiter circuit 15.
- the binary limiter circuit 15 converts an analog signal supplied from the RF amplifier 13 into a digital binary signal.
- Output signal of binary limiter circuit 15 Is supplied to the LPF section 14 and the clock recovery circuit.
- the LPF unit 14 has an LPF 14 a for a high transfer rate and an LPF 14 b for a low transfer rate, and the control is performed by the microcomputer 10 to switch between the processes. This control is performed based on synchronization adjustment information based on the various information supplied to the microcomputer 10 described above, for example, transfer rate information and switching information of the output of the preamplifier.
- the output signal of LPF section 14 is returned to adder 28.
- the clock recovery circuit consists of an edge detection circuit 17, a phase comparator 18, a phase lock detection circuit 19, a charge pump circuit 20, a charge pump filter circuit 21, and a current-to-voltage converter (hereinafter referred to as VZ I converter 22) Internal clock signal generator (hereinafter referred to as VC ⁇ (Voltage Controlled Oscillator) as appropriate) 23, Timing adjustment circuit 24 and RF buffer 25.
- PLL is constituted by VC ⁇ 23, phase comparator 18, charge pump circuit 20 and charge pump filter circuit 21.
- the signal supplied from the binary limiter circuit 15 to the clock recovery circuit is first supplied to the edge detection circuit 17.
- the edge detection circuit 17 raises the digit signal supplied from the binary limiter circuit 15 in synchronization with each of the rising edge and the falling edge, and uses the pulse width of the VCO 23 output pulse. It is converted to a pulse time width of about 1 to 4 with a certain time width T The conversion of the pulse time width is determined by predetermined characteristics of the VCO 23 and a control signal a from the electronic polyme 26 described later.
- An edge detection pulse which is an output signal of the edge detection circuit 17 is supplied to the phase comparator 18.
- the phase comparator 18 compares the phase of the edge detection pulse from the edge detection circuit 17 with the output signal d of the VCO 23, and generates a comparison output having a pulse width corresponding to the phase difference.
- the comparison output of the phase comparator 18 is supplied to a phase lock detection circuit 19 described later.
- the comparison output of the phase comparator 18 is supplied to the charge pump circuit 20.
- the charge pump circuit 20 converts a phase difference time signal, which is a comparison output of the phase comparator 2, into a current value.
- the output signal of the charge pump circuit 20 is supplied to the charge pump filter 21.
- the charge pump filter 21 determines a time constant for transmission to the VC023 by, for example, a resistor and a capacitor C. That is, the charge pump filter 21 generates a control voltage to be supplied to the VCO 23 via the VZI converter 22.
- the current-converted output signal of the charge pump filter 21 is transmitted to the current-voltage conversion circuit 22.
- the I-converter 22 converts a current signal input from the charge pump filter 21 into a voltage signal.
- the output voltage of the V / I comparator 22 is supplied to the control terminal of the VCO 23 as a control voltage.
- the VCQ 23 generates a signal having a frequency corresponding to the output voltage of the V / I converter 22 based on a control signal b of the electronic volume 26 described later and an output signal c of the phase lock detection circuit 19.
- the signal generated by VC ⁇ 23 is fed back to phase comparator 18.
- the signal is output to the timing adjustment circuit 24.
- the output frequency from VC023 may be supplied to the phase comparator 18 and the timing matching circuit 24 after being divided by a divider (not shown).
- the timing matching circuit 24 varies the phase of the signal supplied from the VCO 23.
- the output signal of the timing matching circuit 24 is stored in the RF buffer 25.
- the RF buffer 25 supplies the stored signal to the signal processing unit 27.
- the signal processing unit 27 performs various signal processing on the output signal supplied from the signal arrangement conversion circuit 9. At that time, the output signal from the RF buffer 25 is used as a clock signal.
- the phase lock detection circuit 19 determines phase lock according to the comparison output input from the phase comparator 18.
- the output signal c as a result of the determination by the phase lock detection circuit 19 is supplied to the VCO 23.
- the electronic volume 26 generates the control signals a and b corresponding to each transfer rate based on the synchronization adjustment information supplied from the microcomputer 10, for example, the head switching information and the linear velocity information. ⁇ Perform optimization of 23.
- FIG. 2A is the front side of the disk 1 and FIG. 2B is the back side of the disk 1.
- the Ach head 3 accesses the surface of the disk 1 from the outer circumference to the inner circumference.
- the Bch head 4 accesses the track from the inner circumference to the outer circumference.
- the disc 1 has a plurality of zones.
- the surface of the disk 1 has first to fourth zones in order from the outside to the inside, and on the back surface, from the outside to the inside, It has zone 5 to zone 8 in order.
- the zones shown in Figs. 2A and 2B are simply divided into four on one side for simplicity of explanation, but the configuration of the zones is not limited to this. Absent.
- the disc 1 is a disc-shaped recording medium of the MCAV system, and data is recorded so that the information line density becomes almost constant. Therefore, when this is reproduced at a constant angular velocity, the transfer rate of the signal becomes higher toward the outer periphery and becomes lower toward the inner periphery.
- the transfer rate is divided into a high transfer rate and a low transfer rate at a predetermined position on the disk 1.
- the first zone, the second zone, the fifth zone, and the sixth zone on the outer peripheral side have a high transfer rate
- the third zone, the third zone on the inner peripheral side have a high transfer rate.
- Zone 4, zone 7, and zone 8 have low transfer rates. That is, the data recorded in Zone 1, Zone 2, Zone 5 and Zone 6 are considered to be high transfer rate data, and are recorded in Zone 3, Zone 4, Zone 7 and Zone 5. Data recorded in 8 zones is considered to be a low transfer rate overnight.
- the playback device accesses the two heads on the front and back sides in the radial direction of the disc in opposite directions, and the sum of the transfer rates is reduced. It can be controlled to be almost constant.
- the A-ch head 3 on the front surface is traced from the disk outer periphery to the inner peripheral side
- the B-ch head 4 on the back surface is traced from the inner peripheral surface of the disk to the outer peripheral side.
- FIGS. 3A-D show an example of two signal arrangements.
- FIG. 3A shows the head switching timing
- FIG. 3B shows the read signal of the Ach head
- FIG. 3C shows the read signal of the Bch head
- FIG. 3D shows the arrangement. This is the converted signal.
- the signal B—ad 1 0 0, read by the B ch head 4 shown in FIG. B-ad101, ... are time-division multiplexed as shown in Fig. D.
- Data units such as A-ad 0 and B-ad 100 0 that are time-division multiplexed are, for example, MPEG 2 program stream packets.
- Each of the arranged signals is input to the clock extracting unit 11, and based on the synchronization adjustment information such as the transfer rate information and the switching information, the microcomputer 10 causes the HPF unit 12 and the HPF unit 12 and the waveform equivalent circuit in the clock extracting unit 11 to Switch LPF section 14 to convert to optimal binary signal.
- FIG. 4A shows the multiplexed reproduced signal read by the Ach head 3 and the Bch head 4 as described above.
- FIG. 4B shows the switching signal.
- the electronic volume 26 sets the control signal a based on the above-described synchronization adjustment information, for example, two pieces of information of the transfer rate information and the switching information.
- Figure 4D shows the waveform of the multiplexed playback data.
- the edge detection circuit 23 determines the pulse width of the output signal from the limiter 15 based on the control signal a supplied from the electronic volume 26 as shown in FIG. Automatically set to about 1/4 of. Further, VC023 changes the frequency of the output clock signal based on the control signal b supplied from the electronic volume 26, as shown by the dashed line in FIG. It is changed so that it falls within the pulse width. As described above, by automatically controlling the relationship between these binary pulse widths and the VC ⁇ 26 clock signal in accordance with the change in the transfer rate, phase synchronization corresponding to a wide range of transfer rates can be achieved. Is
- FIG. 4C shows the phase lock detection signal.
- the output signal of the phase detection lock detection circuit 19 changes to a low level, as shown in FIG. 4C, in addition to the above-described two pieces of information of the synchronization adjustment information, for example, the transfer rate information and the switching information.
- the instantaneous change of the pulse width in the edge detection circuit 23 by the control signal “a” and the frequency change of VC 0 23 by the control signal “b” instantaneously perform high-speed phase synchronization.
- the clock signal thus optimally phase-synchronized is transmitted to a signal processing unit 27 of a signal processing system such as a running system and a demodulation unit subsequent to the clock extraction unit 11 to form a disk recording / reproducing apparatus.
- the trace trace of the head shown in Fig. 5A includes both A ch head 3 and B ch head 4 from the outer circumference to the inner circumference of the front and back surfaces of the disk, that is, from the zone with the higher transfer rate to the lower one. Traced to the zone.
- the trace pattern of the head shown in Fig. 5B shows that both the A-ch head 3 and the B-ch head 4 move from the inner circumference to the outer circumference on the front and back surfaces of the disk, that is, from the lower to the higher zone of the transfer rate. Is being traced.
- each head traces from the address data detected by the address demodulation unit 7. Access the track.
- the clock is extracted in the same manner as described above, and the synchronous clock signal output as a result is transmitted to the subsequent signal processing unit 27 to form a disk recording / reproducing apparatus.
- two heads, the Ach head 3 and the Bch head 4 are read from the MCAV disc-shaped recording medium.
- the readout signals are read out simultaneously at the same time, and the two readout readout signals are multiplexed in a time series by the signal arrangement conversion circuit 9 and are arranged and converted.
- the switching of the HPF section 12 and LPF section 14 and the edge detector 17 Since the microcomputer 10 controls the output of the electronic volume 26 so that the output of 23 is optimal, the clock extracting unit 11 can be configured by one system. This simplifies the circuit system, reduces the circuit scale, and realizes a very effective disc recording / reproducing device in terms of cost.
- the transfer rate information obtained from the head switching information and the linear velocity, and the adjustment parameters in the clock extraction unit 11 based on the information are used. By performing optimal control, it is possible to easily extract a good clock signal.
- Phase synchronization is possible even when freely accessed regardless of the sum of the transfer rates, and there is a significant merit to the speeding up of track control related to the servo system and the access speed at random access.
- a certain disk recording / reproducing device can be realized.
- the clock recovery circuit automatically controls and optimizes the pulse width of the edge detection circuit 17 and the output frequency of the VCO 23, so that phase synchronization and phase Synchronization can be maintained, and the ease and stability of track control related to the support system and the high-speed access during random access are dramatically improved.
- the disc 1 is a disc-shaped recording medium of the MCAV format, and the disc 1 is configured to have the head on the front side and the back side.
- the present invention is not limited to this. As long as it is a configuration for reading, a configuration having a head only on one side may be used.
- the disc 1 is not limited to the MCAV format, and can be applied to various disc-shaped recording media such as an optical disc, a magneto-optical disc, and a magnetic disc.
- the transfer rate is set to two, that is, a low transfer rate and a high transfer rate.
- the transfer rate can be further subdivided to correspond to three or more different transfer rates.
- the data of each head is alternately multiplexed in bucket units, but the reproduction from each head is performed. If the signals are multiplexed into one, other multiplexing configurations and data units may be used.
- the first and second reproduced signals simultaneously read from a disk-shaped recording medium by a plurality of reading means are optimized for each of the reproduced signals.
- Time-division multiplexing of the reproduced signals processing the time-division multiplexed reproduced signals by switching the waveform equalization characteristics according to the respective synchronization adjustment information, and generating the synchronization adjustment information.
- a single clock extraction circuit can be used, and a clock signal corresponding to the reproduction signal of a wide range of transfer rates can be generated without redundant circuit. It can be carried out. Therefore, it is possible to generate a quick signal corresponding to a reproduced signal having a wide range of transfer rates at high speed and at low cost.
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- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
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- Signal Processing For Digital Recording And Reproducing (AREA)
- Optical Recording Or Reproduction (AREA)
- Optical Head (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US10/554,184 US7564744B2 (en) | 2003-04-23 | 2004-02-19 | Clock system for reproducing apparatus and method |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003118471A JP3823939B2 (ja) | 2003-04-23 | 2003-04-23 | 再生装置および方法 |
JP2003-118471 | 2003-04-23 |
Publications (1)
Publication Number | Publication Date |
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WO2004095454A1 true WO2004095454A1 (ja) | 2004-11-04 |
Family
ID=33308072
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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PCT/JP2004/001918 WO2004095454A1 (ja) | 2003-04-23 | 2004-02-19 | 再生装置および方法 |
Country Status (5)
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US (1) | US7564744B2 (ja) |
JP (1) | JP3823939B2 (ja) |
KR (1) | KR20060013372A (ja) |
CN (1) | CN100442380C (ja) |
WO (1) | WO2004095454A1 (ja) |
Families Citing this family (4)
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JP4197524B2 (ja) * | 2006-01-27 | 2008-12-17 | 富士通テン株式会社 | 録音再生装置、録音再生方法及び車載用録音再生装置 |
JP5029411B2 (ja) * | 2008-02-19 | 2012-09-19 | ソニー株式会社 | 再生装置、再生方法、データ検出処理回路 |
CN101667438A (zh) * | 2009-09-17 | 2010-03-10 | 钟磊 | 立体视频的记录和播放方法 |
JP2011113590A (ja) * | 2009-11-25 | 2011-06-09 | Sony Corp | 光ディスクドライブ装置、その制御方法および光ディスクドライブシステム |
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JPH04254967A (ja) * | 1991-02-07 | 1992-09-10 | Nikon Corp | マルチヘッド光ディスク装置 |
JPH06180944A (ja) * | 1992-12-11 | 1994-06-28 | Matsushita Electric Ind Co Ltd | ディスク再生方法およびディスク再生装置 |
JPH0745007A (ja) * | 1993-05-28 | 1995-02-14 | Teac Corp | 光ディスク装置 |
JPH07296521A (ja) * | 1994-04-25 | 1995-11-10 | Sony Corp | ディスク装置 |
JPH1196668A (ja) * | 1997-09-25 | 1999-04-09 | Sony Corp | 光ディスク記録装置及び光ディスク再生装置 |
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US4873679A (en) * | 1986-12-25 | 1989-10-10 | Matsushita Electric Industrial Co., Ltd. | Optical information recording disk and optical information recording disk apparatus |
JPH0486183A (ja) * | 1990-07-30 | 1992-03-18 | Matsushita Electric Ind Co Ltd | 映像信号の記録再生装置 |
JP2853375B2 (ja) * | 1991-07-04 | 1999-02-03 | 松下電器産業株式会社 | 光学的記録再生装置 |
KR100230892B1 (ko) * | 1992-10-20 | 1999-11-15 | 모리시타 요이찌 | 디스크장치 |
JPH07230625A (ja) * | 1994-02-17 | 1995-08-29 | Pioneer Electron Corp | 光記録媒体並びにその記録装置及び再生装置 |
JP3552143B2 (ja) * | 1997-07-15 | 2004-08-11 | パイオニア株式会社 | 多層ディスク用キャリッジ制御装置 |
JP2000090589A (ja) * | 1998-09-11 | 2000-03-31 | Matsushita Electric Ind Co Ltd | クロックリカバリー装置 |
WO2000036602A1 (fr) * | 1998-12-17 | 2000-06-22 | Matsushita Electric Industrial Co., Ltd. | Circuit de synchronisation de phase/stabilisation de frequence |
US6437937B1 (en) * | 2000-04-24 | 2002-08-20 | Maxtor Corporation | Disk drive with high speed read/write capability |
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2003
- 2003-04-23 JP JP2003118471A patent/JP3823939B2/ja not_active Expired - Fee Related
-
2004
- 2004-02-19 WO PCT/JP2004/001918 patent/WO2004095454A1/ja active Application Filing
- 2004-02-19 KR KR1020057019970A patent/KR20060013372A/ko not_active Application Discontinuation
- 2004-02-19 US US10/554,184 patent/US7564744B2/en not_active Expired - Fee Related
- 2004-02-19 CN CNB2004800098748A patent/CN100442380C/zh not_active Expired - Fee Related
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JPH04254967A (ja) * | 1991-02-07 | 1992-09-10 | Nikon Corp | マルチヘッド光ディスク装置 |
JPH06180944A (ja) * | 1992-12-11 | 1994-06-28 | Matsushita Electric Ind Co Ltd | ディスク再生方法およびディスク再生装置 |
JPH0745007A (ja) * | 1993-05-28 | 1995-02-14 | Teac Corp | 光ディスク装置 |
JPH07296521A (ja) * | 1994-04-25 | 1995-11-10 | Sony Corp | ディスク装置 |
JPH1196668A (ja) * | 1997-09-25 | 1999-04-09 | Sony Corp | 光ディスク記録装置及び光ディスク再生装置 |
Also Published As
Publication number | Publication date |
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CN100442380C (zh) | 2008-12-10 |
JP2004326882A (ja) | 2004-11-18 |
KR20060013372A (ko) | 2006-02-09 |
JP3823939B2 (ja) | 2006-09-20 |
US7564744B2 (en) | 2009-07-21 |
US20060233074A1 (en) | 2006-10-19 |
CN1774763A (zh) | 2006-05-17 |
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