WO2002095817A2 - Composant a semi-conducteur comportant au moins une puce de semi-conducteur placee sur une puce de base servant de substrat, et son procede de production - Google Patents

Composant a semi-conducteur comportant au moins une puce de semi-conducteur placee sur une puce de base servant de substrat, et son procede de production Download PDF

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Publication number
WO2002095817A2
WO2002095817A2 PCT/DE2002/001783 DE0201783W WO02095817A2 WO 2002095817 A2 WO2002095817 A2 WO 2002095817A2 DE 0201783 W DE0201783 W DE 0201783W WO 02095817 A2 WO02095817 A2 WO 02095817A2
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Prior art keywords
chip
semiconductor
base
base chip
semiconductor chip
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PCT/DE2002/001783
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German (de)
English (en)
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WO2002095817A3 (fr
Inventor
Holger Huebner
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Infineon Technologies Ag
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Publication of WO2002095817A2 publication Critical patent/WO2002095817A2/fr
Publication of WO2002095817A3 publication Critical patent/WO2002095817A3/fr

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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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Definitions

  • the present invention relates to a semiconductor component with at least one semiconductor chip on a base chip serving as a substrate.
  • the invention further relates to a method for producing such a semiconductor component.
  • circuit parts that have to be manufactured using different technologies. For example, logic circuits are combined with memory circuits. Logic circuits require different manufacturing processes than the simply constructed memory chips. The same applies to a combination of a circuit breaker with its control. Such semiconductor components are integrated, for example, from two housed
  • Circuits mounted side by side on a substrate One of the modules then contains, for example, the memory, while the other integrated circuit contains all the components for the control.
  • the integrated circuits are electrically connected via the substrate.
  • Semiconductor components that are manufactured according to this principle are relatively large and require a large number of work steps to produce them.
  • the object of the invention is to specify a semiconductor component with at least two functional circuits, which fi Hi N
  • a plurality of semiconductor chips can also be applied and contacted on the base chip.
  • the semiconductor chips are then arranged side by side on the base chip.
  • the base chip has a larger area than the semiconductor chip or the plurality of semiconductor chips.
  • Contact elements for external contacting of the semiconductor component are provided in the uncovered area of the base chip.
  • the contact elements can be designed, for example, as bond pads. These can be used to contact the semiconductor component via bonding wires with corresponding contact elements of a substrate on which the semiconductor component is mounted.
  • the base chip has contact elements.
  • the semiconductor chips mounted on the base chip do not have such contact elements.
  • the electrical connection to the outside is made via the base chip and its contact elements.
  • the semiconductor chips can be made very small. This enables a considerable increase in the area yield on an afer.
  • the integrated circuits contacted with one another can be accommodated together in a single housing.
  • the area of the contact elements which are provided for external contacting is preferably larger than that
  • the base chip contains area-intensive structures, while the at least one semiconductor chip contains complex logic structures.
  • the base chip contains elements that can be manufactured using the cheaper technology, since in this case a lower yield of base chips per wafer is not as important.
  • the base chip can include, for example, switches, ESD structures, bus lines, test circuits, sensors and the like. It thus represents an active, intelligent substrate for the semiconductor chips mounted thereon.
  • the base chip preferably has as few metal levels as possible in order to enable simple and inexpensive production.
  • the semiconductor chips contain complex logical structures and have a larger number of metal levels. Since the production of such semiconductor chips is more complex and therefore more expensive, it is desirable to make these semiconductor chips as small as possible. This wish is taken into account with the proposed semiconductor component.
  • the at least one semiconductor chip can be ground thin. This results in an optimized semiconductor component in terms of overall height.
  • the semiconductor chip is designed as a two-layer or multi-layer chip stack, the chip stack preferably being designed as a three-dimensionally integrated system. This allows do Q fi
  • the respective contact areas of the at least one semiconductor chip and the base chip can also be connected via solder balls in order to implement the electrical contact.
  • a filler layer is preferably present between the at least one semiconductor chip and the base chip outside the areas occupied by the contact surfaces and / or the further metal surfaces in order to additionally mechanically stabilize the arrangement. This filler layer is known as a so-called "underfill”.
  • the method according to the invention for producing the semiconductor component described above comprises the following steps:
  • the contact areas are generated on the semiconductor chips and the base chips.
  • the semiconductor chips that is to say those integrated circuits which are placed on the base chips, are separated from the wafer composite.
  • at least one semiconductor chip is contacted on each base chip in such a way that mutually assigned contact areas of the at least one semiconductor chip and of the base chip face one another and the mutually facing contact areas are electrically conductively connected to one another.
  • the composite of the at least one semiconductor chip and the base chip from the wafer is then separated. All pretreatment steps, such as the deposition of various metallization layers, their structuring by lithography and so on, are thus carried out cost-effectively as a wafer process.
  • the integrated circuits lying one above the other can be housed or mounted directly on a substrate.
  • the production of the contact areas comprises the application of a sequence of structured metal layers, consisting of an adhesive layer, a diffusion barrier and a solderable metal layer.
  • the solderable metal layer is preferably applied by sputtering or galvanic reinforcement.
  • the contacting of the semiconductor chip on the base chip is preferably carried out by applying a contact pressure during the soldering process.
  • the diffusion soldering process mentioned at the outset is preferably used.
  • FIG. 1 shows a first exemplary embodiment of the semiconductor component according to the invention
  • FIG. 2a shows a second exemplary embodiment of the inventive semiconductor component before contacting a semiconductor chip on a
  • FIG. 2b shows an alternative embodiment of the base chip from FIG. 2a
  • FIG. 3 shows the application of contact areas and metal elements on the base chip during different process steps
  • FIG. 4 shows a second exemplary embodiment for the application of contact areas to the base chip during different method steps
  • Figure 5 shows a third embodiment for the application of contact surfaces and metal surfaces on the base chip and Figure 6 shows a fourth embodiment for the application of contact surfaces and other metal surfaces on the base chip.
  • Figure 1 shows in cross section a first embodiment of the semiconductor device according to the invention.
  • a semiconductor chip 20 is arranged on a base chip 10.
  • the base chip 10 and the semiconductor chip 20 each have contact areas.
  • the semiconductor chip 20 is oriented toward the base chip in such a way that the mutually assigned contact surfaces face one another and are connected to one another in an electrically conductive manner.
  • the electrical contacting of the assigned contact areas is realized in the present case in FIG. 1 by means of solder balls 30. These are placed between the respective contact areas and soldered to them.
  • the intermediate spaces are filled with a filler layer 31.
  • the base chip is substantially larger than the semiconductor chip 20.
  • the base chip is preferably produced using the cheaper technology, since in this case a lower yield of base chips per wafer is not as serious.
  • the base chip can contain switches, ESD structures, buses, test circuits and sensors.
  • Contact elements 12 are arranged on the base chip 10 on the same side as the semiconductor chip 20, only one contact element 12 being visible in the cross-sectional illustration in FIG. 1.
  • the contact element 12 is designed to be substantially larger than the contact surfaces and is used for external contacting of the semiconductor component. For example, a bonding wire can be bonded to the contact element 12.
  • the semiconductor component according to the invention has the advantage that the semiconductor chip 20 manufactured in the more expensive technology need not have large contact elements. This allows particularly small areas of the semiconductor chip ü ⁇ to CO ⁇ H in o in o in O c ⁇
  • rt 0 ⁇ - 1 ⁇ - 0 : ⁇ ü X Hl fi Hi rt 0.> 0 ⁇ CQ fi tt fi rt ⁇ 0 ⁇ IS] er J CQ ⁇ - ⁇ - ⁇ tr 0 ⁇ - 0 tr ⁇ - ⁇ ⁇ ⁇ 0 0 ⁇ - 0 H 1 ⁇ ⁇ 0 u> 0 ⁇ 0 ⁇ N 0 tr 0 fi 0 * ⁇
  • the semiconductor chips and the base chips 10 require only a small area, since the contacting of the respective upper metal surfaces (contact pads 14 or 24) is not carried out by conventional soldering areas with a size of 100 x 100 ⁇ m 2 , as is necessary in the case of conventional solder balls, but by small through-plating 15, 25. These have an area which corresponds to the area of front-end plated-through holes. The area required is approximately 11 ⁇ m 2 . These vias can be so small because they can be opened during wafer processing. In the later processing only a cheap contact lithography needs to be used.
  • the contact surfaces 11, 21 can be placed with one another with a substantially higher density when using the diffusion soldering method.
  • the average distance between two contact surfaces only needs to be 30 ⁇ m, which means that more than 10,000 contacts per cm 2 can be realized.
  • the "face to face” contact also ensures short connection paths between the base chip 10 and the semiconductor chip 20. This means that short signal delays, small dispersion u ⁇ t to in o in o c ⁇ O c ⁇
  • the metal layer 18 is etched away in the area of the areas not covered by the lacquer 33.
  • the etching can be carried out wet-chemically. An undercut must be compensated for by appropriate mask provision. This means that the lithography step must be finer than the final structures.
  • plasma etching could also be carried out, optionally anisotropically, that is to say without widening the structure.
  • FIG. 4 shows a further possibility of how the contact surfaces 11 and the further metal surfaces 13 can be applied by means of electroplating.
  • a barrier layer which consists for example of TiW, a Ti / TiN alloy or a Ta / TaN alloy, and an approximately 100 nm thick copper seed layer 19 are sputtered over the entire surface of the active side of the base chip 10. This is followed by negative lithography, which represents the later isolation trenches. These are represented by the lacquer bars 33.
  • the area between the lacquer walls 33 is then galvanically filled with copper (cf. right illustration in FIG. 4).
  • the lacquer walls 33 are next removed. In the areas in which the lacquer webs 33 were located, the germ layer 19 and the barrier layer 17 are etched away in a further step. This can be done wet-chemical or with a plasma etching process.
  • solder layer can be applied before or after the removal of the lacquer webs 33 by means of an electroplating step. If the solder layer is applied before removing the lacquer bars, the so-called lacquer stripping, then solder alloys made of Sn / Pb or Sn / Al alloys can be used.
  • FIG. 5 A third methodology for applying the contact surfaces 11 and further metal surfaces 13 is shown in FIG. 5.
  • the barrier layer 17 and the metal layer 18 are successively sputtered through a shadow mask 34 or thermally evaporated.
  • the shadow mask has webs 35 which are located at the points at which the later isolation trenches are provided.
  • the barrier layer 17 should be sputtered for better adhesion. In this method, care must be taken to maintain a small distance between the shadow mask 34 and the base chip 10. Care must also be taken to ensure sufficient collimation of the atomized materials.
  • a fourth variant for producing the contact surfaces 11 and the further metal surfaces 13 is shown in FIG. 6.
  • a lacquer mask 33 is produced on the base chip 10 and covers the later isolation trenches.
  • the paint mask should have overhanging paint edges or negatively undercut flanks. This can be achieved by a suitable exposure dose, by a two-layer lacquer technique or by hardening the upper surface of the lacquer.
  • the metal layers 17, 18 are then deposited by sputtering and thermal evaporation. The parts of the layer that grow on the paint mask are also washed away when the paint mask is removed. The method described with reference to FIG. 6 is called "lift-off".
  • solder alloys can also be produced by the metal layers 17, 18 in suitable thickness are applied to each other, provided that they then participate in the phase formation and mix during the later contacting process of the semiconductor chip and the base chip.
  • the barrier layer could also initially be applied over the entire area.
  • the areas of the barrier layer 17 which come to rest within the isolation trenches after the removal of the resist mask 33 must then be removed by wet chemical means or by means of plasma etching.
  • the description of the figures was based on several examples, in which exactly one semiconductor chip 20 is applied to a base chip 10. It is also within the scope of the invention to apply a plurality of semiconductor chips 20 next to one another on a base chip 10.
  • the semiconductor chips 20 can, but need not, be thinned on their rear side.
  • the backside thinning can be carried out by a grinding process after the semiconductor chips 20 have been applied to the base chip 10.
  • the semiconductor chip 20 could also be designed as a two-layer or multi-layer chip stack, the chip stack being designed as a three-dimensionally integrated system.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Thermistors And Varistors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un composant à semi-conducteur comportant au moins une puce de semi-conducteur (20) placée sur une puce de base (10) servant de substrat, la ou les puce(s) de semi-conducteur (20) et la puce de base (10) comportant des surfaces de contact (11, 21) en métal. La puce de semi-conducteur (20) et la puce de base (10) sont alignées l'une sur l'autre de telle sorte que des surfaces de contact associées l'une à l'autre de la ou des puce(s) de semi-conducteur (20) et de la puce de base (10) se font face et que ces surfaces de contact (11, 21) se faisant face sont reliées l'une à l'autre de façon électroconductrice. L'écart entre une surface de contact de la ou des puce(s) de semi-conducteur (20) et la surface de contact, connectée à celle-ci, de la puce de base (10) est inférieure à 10 µm. La puce de base (20) comporte des composants fabriqués selon une première technique, tandis que la ou les puce(s) contient des composants qui sont fabriqués selon une seconde technique.
PCT/DE2002/001783 2001-05-21 2002-05-17 Composant a semi-conducteur comportant au moins une puce de semi-conducteur placee sur une puce de base servant de substrat, et son procede de production WO2002095817A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE10124774.5 2001-05-21
DE10124774.5A DE10124774B4 (de) 2001-05-21 2001-05-21 Halbleiterbauelement mit zumindest einem Halbleiterchip auf einem als Substrat dienenden Basischip und Verfahren zu dessen Herstellung

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WO2002095817A2 true WO2002095817A2 (fr) 2002-11-28
WO2002095817A3 WO2002095817A3 (fr) 2003-06-19

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WO2004064139A2 (fr) * 2003-01-10 2004-07-29 Infineon Technologies Ag Empilement de puces a semiconducteur et procede de passivation d'un empilement de puces a semiconducteur
EP1617473A1 (fr) * 2004-07-13 2006-01-18 Koninklijke Philips Electronics N.V. Dispositif électronique avec dispositif ESD

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DE10303588B3 (de) * 2003-01-29 2004-08-26 Infineon Technologies Ag Verfahren zur vertikalen Montage von Halbleiterbauelementen
DE10313047B3 (de) * 2003-03-24 2004-08-12 Infineon Technologies Ag Verfahren zur Herstellung von Chipstapeln
DE102004055677A1 (de) * 2004-11-18 2006-06-01 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Chipträgerverbund und Verfahren zum Herstellen eines Chipträgerverbunds

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WO2004064139A2 (fr) * 2003-01-10 2004-07-29 Infineon Technologies Ag Empilement de puces a semiconducteur et procede de passivation d'un empilement de puces a semiconducteur
WO2004064139A3 (fr) * 2003-01-10 2005-04-21 Infineon Technologies Ag Empilement de puces a semiconducteur et procede de passivation d'un empilement de puces a semiconducteur
US7229851B2 (en) 2003-01-10 2007-06-12 Infineon Technologies Ag Semiconductor chip stack
EP1617473A1 (fr) * 2004-07-13 2006-01-18 Koninklijke Philips Electronics N.V. Dispositif électronique avec dispositif ESD
WO2006008680A1 (fr) * 2004-07-13 2006-01-26 Koninklijke Philips Electronics N.V. Dispositif electronique comprenant un dispositif esd
US8159032B2 (en) 2004-07-13 2012-04-17 Nxp B.V. Electronic device comprising an ESD device

Also Published As

Publication number Publication date
TW544903B (en) 2003-08-01
DE10124774A1 (de) 2002-12-12
CN1539163A (zh) 2004-10-20
CN100461356C (zh) 2009-02-11
DE10124774B4 (de) 2016-05-25
WO2002095817A3 (fr) 2003-06-19

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