WO2002023714A1 - Melangeur resistif - Google Patents

Melangeur resistif Download PDF

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Publication number
WO2002023714A1
WO2002023714A1 PCT/JP2001/007819 JP0107819W WO0223714A1 WO 2002023714 A1 WO2002023714 A1 WO 2002023714A1 JP 0107819 W JP0107819 W JP 0107819W WO 0223714 A1 WO0223714 A1 WO 0223714A1
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WIPO (PCT)
Prior art keywords
fet
signal
drain
circuit
source
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Application number
PCT/JP2001/007819
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English (en)
Japanese (ja)
Inventor
Koji Takinami
Makoto Sakakura
Toshiaki Nakamura
Hideki Namba
Original Assignee
Matsushita Electric Industrial Co., Ltd.
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Publication of WO2002023714A1 publication Critical patent/WO2002023714A1/fr

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/12—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
    • H03D7/125—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes with field effect transistors

Definitions

  • the present invention relates to a mixer using an FET, particularly a resistive mixer that is a low distortion mixer suitable for a semiconductor integrated circuit, a bias circuit that supplies a bias power supply voltage to the resistive mixer, a high-frequency amplifier, and communication equipment.
  • a mixer is a frequency conversion circuit that receives two signals and generates a sum or difference between the two frequencies. Such frequency conversion is realized by actively utilizing the non-linearity of the element, but high linearity is required for the input / output characteristics in order not to generate unnecessary frequency components. As a mixer having high linearity, there is a method of performing frequency conversion using a change in resistance between a drain and a source of an FET.
  • This type of mixer is referred to as a resistive mixer and examples are described in IE T ran s a c ct io n s s o n M i c o o w a v e T e o r y a n d T e c h n i q u e s, Vo l. MTT-35, No. 4, A r i l 1987.
  • FIGS. 101 is an RF signal input terminal (RF: transmission frequency or reception frequency)
  • 102 is an LO signal input terminal (LO ⁇ local oscillation frequency)
  • 1 ⁇ 3 is an IF signal output terminal (IF: intermediate frequency)
  • 107 is a bias 154 is a bias supply terminal
  • 100 is a mixer FET.
  • 104, 105, and 106 are matching circuits
  • the RF matching circuit 104 is an HPF (high-pass filter) and an IF matching circuit.
  • Circuit 106 is designed as an LPF (low pass filter) type.
  • Figure 14 shows the change in the drain-source resistance versus the gate voltage of a FET with no drain bias.
  • the horizontal axis shows the gate-source voltage V gs, and the vertical axis shows the drain-source resistance.
  • the threshold value V th of the FET in this example is about 0.3 V.
  • a FET that is not biased to the drain operates as a variable resistor controlled by the gate bias. Therefore, if the resistance between the drain and source is varied by the LO signal, mixing of the RF signal and the LO signal is performed.
  • the LPF extracts only the difference frequency component between the RF frequency and the LO frequency from the frequency component generated by mixing the RF signal and the LO signal, and outputs the IF frequency component from the IF signal terminal.
  • setting the gate bias near the threshold voltage increases the rate of change of the resistance value and reduces the conversion loss. Is set to
  • MES FETs Metal Sem i c o n d u c t o r F i e l d E f f e c t T r a n s i s t o r
  • HEM T H i g h h
  • Elec tron Mob ily tyTransistor usually has a negative threshold. Therefore, when a conventional resistive mixer is incorporated in a circuit that uses only a positive power supply, a negative power supply is required to set the gate voltage of the resistive mixer FET near the threshold. That is, in order to set the gate voltage of the resistive mixer near the threshold value, a negative power supply is required, and the circuit scale is increased.
  • the mixer There is also a problem that the conversion loss fluctuates.
  • the present invention provides a resistive mixer, a bias circuit, a high-frequency amplifier, and a communication device, which are operated with a single power supply, have low conversion loss, and have low characteristic variation and low distortion.
  • the purpose is to provide a simple configuration.
  • a first aspect of the present invention includes at least a FET of a degradation type (having a negative threshold voltage), and a gate of the FET.
  • Ground means one of which is connected to the FET's gut and the other is grounded;
  • One is connected to the source of the FET and the other is grounded;
  • a bias supply terminal connected to a source or a drain of the FET and to which a positive voltage is applied;
  • the mixer as an example of the first present invention connects the source of the FET constituting the mixer via the capacitor and the bias terminal.
  • a configuration is provided in which the gate bias of the FET can be biased near the threshold value with a single power supply.
  • capacitors there are two capacitors, one is a first grounding capacitor for an RF signal and an LO signal, and the other is a second grounding capacitor for an IF signal.
  • the resistive mixer according to the first aspect of the present invention wherein the first grounding capacitor is formed inside the semiconductor integrated circuit, and the second grounding capacitor is formed outside the semiconductor integrated circuit.
  • an RF matching circuit is provided on the RF signal input / output side of the FET, and the RF signal input / output side of the FET is provided on the IF signal input / output side.
  • IF matching circuit is provided,
  • a third DC cut capacitor provided between the drain of the FET and the RF matching circuit
  • a resistive mixer according to the first or second aspect of the present invention further comprising a fourth capacitor for DC cut provided between the drain of the FET and the IF matching circuit.
  • a fourth aspect of the present invention includes at least a first FET and a second FET, wherein the first FET and the second FET are of a decimation type (negative type).
  • An L F signal is input to the gates of the first FET and the second FET, and the drains of the first FET and the second FET are A single-parallel resistive mixer to which an RF signal or an IF signal is input and an IF signal or an RF signal is extracted from drains of the first FET and the second FET;
  • Ground means one of which is connected to the gate of the first FET and the gut of the second FET, and the other is grounded;
  • a bias supply terminal connected to a source or a drain of the first FET and the second FET, to which a positive voltage is applied; and a gate of the first FET and the gate of the second FET.
  • This is a resistive mixer in which the potential is biased negative with respect to each source potential.
  • a fifth aspect of the present invention includes at least first to fourth FETs, wherein the first to fourth FETs have a depletion type (having a negative threshold voltage). ), Wherein the first to fourth FETs are connected in a ring shape, and further, two opposing gates of the FET are connected to each other, and the two sets of connected gates have L ⁇ A signal is input, an RF signal is input to one drain or source connection point of a pair of FETs opposed to each other in the first to fourth FETs, and an IF signal is input from the other drain or source connection point.
  • a double-balanced resistive mixer to be taken out,
  • Ground means one of which is connected to the gates of the first to fourth FETs and the other is grounded;
  • a bias supply terminal connected to a drain or a source of the first to fourth FEs and to which a positive voltage is applied;
  • a resistive mixer in which the gate potentials of the first to fourth FETs are biased to a negative potential with respect to the respective source potentials.
  • a sixth invention is the resistive mixer according to any one of the first, fourth, and fifth inventions, wherein the grounding means is a resistor and / or an inductor.
  • a seventh aspect of the present invention is the resistive mixer according to any one of the first, fourth and fifth aspects of the present invention formed together with an amplifier circuit on the same semiconductor substrate.
  • An eighth aspect of the present invention includes at least a FET, an LO signal is input to a gate of the FET, an RF signal or an IF signal is input to a drain of the FET, A resistive mixer that extracts an IF or RF signal from the drain of a FET,
  • One of which is connected to the gate or the source or the drain of the FET, further comprising a bias supply terminal to which a voltage is applied,
  • a circuit that cuts off the IF signal is provided on the RF signal input / output side
  • a circuit that cuts off the RF signal is provided on the IF signal input / output side
  • the input impedance seen from the drain end of the FET is Is a resistive mixer that is set to be substantially equal to the input impedance of the IF port at the IF frequency.
  • a ninth aspect of the present invention includes at least a first FET and a second FET, and an LO signal is input to gates of the first FET and the second FET.
  • An RF signal or an IF signal is input to the drains of the first FET and the second FET, and an IF signal or an RF signal is extracted from the drains of the first FET and the second FET.
  • a single-resistor resistive mixer includes at least a first FET and a second FET, and an LO signal is input to gates of the first FET and the second FET.
  • An RF signal or an IF signal is input to the drains of the first FET and the second FET, and an IF signal or an RF signal is extracted from the drains of the first FET and the second FET.
  • a source of the first FET and a source of the second FET are connected;
  • a bias supply terminal connected to a gate, a source, or a drain of the first FET and the second FET, to which a voltage is applied;
  • a circuit that cuts off the IF signal is provided on the RF signal input / output side
  • a circuit that cuts off the RF signal is provided on the IF signal input / output side
  • the first FET and the second Input impedance seen from the drain end of the FET Is a resistive mixer.
  • a tenth aspect of the present invention includes at least first to fourth FETs, wherein the first to fourth FETs are connected in a ring shape, and further comprises two pairs of opposed FETs.
  • the gates of the FETs are connected to each other, an LO signal is input to the two sets of connected gates, and the connection of one drain or source of one set of the FETs opposed to each other in the first to fourth FETs
  • a point-to-point RF signal is input, and an IF signal is extracted from the other drain or source connection point.
  • a bias supply terminal connected to a gate, a drain, or a source of the first to fourth FETs and to which a voltage is applied,
  • a circuit for interrupting the IF signal is provided on the RF signal input / output side, a circuit for interrupting the RF signal is provided on the IF signal input / output side, and the drains of the first to fourth FETs are further provided.
  • This is a resistive mixer whose input impedance viewed from the end is set to be substantially equal to the input impedance of the IF port at the IF frequency.
  • the eleventh invention depends on the temperature of the FET of the resistive mixer according to any one of the first, second, fourth, fifth, eighth, ninth and tenth inventions.
  • a fifth FET a second resistor connected directly or indirectly to the source of the fifth FET and the other grounded,
  • a power supply voltage is supplied to the drain of the fifth FET
  • a gate of the fifth FET is directly or indirectly connected to one of the second resistors, and a bias supply terminal of the resistive mixer is connected to one of the second resistors.
  • the 12th present invention (corresponding to claim 12) is a bias circuit which is a bias circuit that One is indirectly connected to the source of the fifth FET, one is connected to one of the second resistors, and the other is connected to the source of the fifth FET.
  • 11 is a diagram illustrating a bias circuit according to an eleventh aspect of the present invention including a third resistor.
  • the fifth FET is formed on the same semiconductor substrate as the resistive mixer F ⁇ .
  • 3 is a bias circuit according to the invention.
  • the fourteenth invention depends on the temperature of the FET of the resistive mixer according to any one of the first, second, fourth, fifth, eighth, ninth and tenth inventions.
  • a diode and a second resistor connected directly or indirectly to the cathode of the diode, the other being grounded,
  • a power supply voltage is supplied to an anode of the diode
  • a bias circuit in which a bias supply terminal of the resistive mixer is connected to one of the second resistors.
  • a fifteenth aspect of the present invention is the bias circuit according to the fifteenth aspect of the present invention, wherein the diode is formed on the same semiconductor substrate as the resistive mixer. It is.
  • a sixteenth invention (corresponding to claim 16) is characterized in that the conversion loss is adjusted by changing the positive voltage applied to the bias supply terminal.
  • the resistive mixer according to any one of 5, 8, 9, and 10 of the present invention.
  • a seventeenth invention (corresponding to claim 17) is a bias circuit for adjusting the conversion loss of the resistive mixer according to the sixteenth invention
  • a fifth FET one directly or indirectly with the source of its fifth F'ET And a second resistor, the other of which is connected to ground,
  • a power supply voltage is supplied to a drain of the fifth FET
  • a bias supply terminal of the resistive mixer is connected to one of the second resistors
  • a bias circuit to which a gain control voltage for changing the conversion loss by changing a voltage is supplied to a gate of the fifth FET.
  • the eighteenth invention depends on the temperature of the FET of the resistive mixer according to any one of the first, second, fourth, fifth, eighth, ninth and tenth inventions.
  • a high-frequency amplifier that can adjust the potential difference between the drain and the source of the FET according to the fluctuation of the threshold value.
  • a fifth FET at least one of which is directly or indirectly connected to a source of the fifth FET and the other of which is grounded, and a second resistor connected to the gate of the fifth FET; IF signal from the resistive mixer is input,
  • a high-frequency amplifier in which a bias supply terminal of the resistive mixer is connected to one of the second resistors.
  • a nineteenth aspect of the present invention (corresponding to claim 19) further comprises at least a FET, an LO signal is input to a gate of the FET, an RF signal is input to a drain of the FET, .
  • a twentieth invention includes at least a FET, a LO signal is input to a gate of the FET, and a drain of the FET is connected to a drain of the FET.
  • a resistive mixer to which an RF signal is input and an IF signal is extracted from a drain of the FET;
  • a resonant circuit one of which is connected to the drain of the FE and the other is grounded;
  • a twenty-first invention (corresponding to claim 21) is a transmission circuit that outputs a transmission signal
  • a communication device using the resistive mixer according to any one of the first, second, fourth, fifth, eighth, ninth, tenth, eighteenth, and nineteenth aspects of the present invention for the transmitting circuit and the Z or the receiving circuit. It is. '' Brief description of the drawings
  • FIG. 1 is a circuit diagram showing a configuration of the resistive mixer according to Embodiment 1 of the present invention.
  • FIG. 2 is an explanatory diagram illustrating the operation principle of the bias circuit according to the first embodiment of the present invention.
  • FIG. 2A is a circuit diagram illustrating another configuration of the bias circuit according to the first embodiment of the present invention.
  • FIG. 3B is a circuit diagram showing another configuration of the bias circuit according to the first embodiment of the present invention. -
  • FIG. 3C is a circuit diagram illustrating another configuration of the bias circuit according to the first embodiment of the present invention.
  • FIG. 4 is a circuit diagram of a bias circuit using a diode instead of FET according to the first embodiment of the present invention.
  • FIG. 5 is a circuit diagram showing a configuration of the single-parallel resistive mixer according to Embodiment 1 of the present invention.
  • FIG. 6 is a circuit diagram showing a configuration of the double-parallax resistive mixer according to the first embodiment of the present invention.
  • FIG. 7 is a circuit diagram showing a configuration of the resistive mixer according to Embodiment 2 of the present invention.
  • FIG. 8 is a circuit diagram showing a configuration of a resonance circuit according to Embodiment 2 of the present invention.
  • FIG. 9 is a circuit diagram showing a configuration of the resistive mixer according to Embodiment 2 of the present invention.
  • FIG. 10 is a circuit diagram showing a configuration of the resistive mixer according to Embodiment 3 of the present invention.
  • FIG. 11 is a circuit diagram showing a configuration of a resistive mixer according to Embodiment 4 of the present invention.
  • FIG. 12 is a circuit diagram showing a configuration of the resistive mixer according to the fifth embodiment of the present invention.
  • FIG. 13 is a circuit diagram showing a configuration of a conventional resistive mixer.
  • FIG. 14 is a characteristic diagram showing a change in drain-source resistance with respect to the FET gate bias.
  • - Figure 15 is a characteristic diagram showing the change in conversion loss with respect to the gate bias of the resistive mixer. Explanation of reference numerals F ET for 100 mixer
  • FIG. 1 shows a configuration of a resistive mixer according to Embodiment 1 of the present invention, where 100 is a mixer £ 1 ⁇ 101 is 1 terminal, 102 is 1 ⁇ 0 terminal, 103 is IF terminal, and 104 is 1 is a matching circuit, 105 is a 1 ⁇ 0 matching circuit, and 106 is an IF matching circuit.
  • the gate of the mixer FET 100 is grounded via a bias resistor 107.
  • the mixer FET 100 is a depletion-type (having a negative threshold voltage) FET.
  • Reference numeral 108 denotes a high-frequency bypass capacitor having a capacitance value that sufficiently reduces the impedance with respect to the RF frequency and the LO frequency
  • reference numeral 109 denotes a capacitance value with which the T impedance is sufficiently reduced with respect to the IF frequency.
  • One is an IF bypass capacitor.
  • 110 and 111 are DC cut capacitors
  • 112 is a bias resistor
  • 154 is a bias supply terminal.
  • a portion surrounded by a dashed line 16 1 constitutes a mixer.
  • the bias supply terminal 154 is connected to a bias circuit composed of a bias circuit FET 150, a drain bias terminal 151, and source resistors 152 and 153.
  • the portion surrounded by a broken line 160 is integrated by a semiconductor process, and only the IF bypass capacitor 109, the IF DC cut capacitor 111, and the matching circuit 106 are formed by external chip components. .
  • the portion surrounded by the wavy line 160 is formed on the semiconductor substrate.
  • the basic operating principle of the resistive mixer according to the first embodiment is the same as that of the conventional resistive mixer, and the resistance between the drain and the source of the mixer FET 100 is changed by the LO signal input from the gate terminal: F signal Then, the low IF frequency is extracted from the IF terminal by the IF matching circuit designed as LPF type.
  • the gate of the mixer FET 100 is grounded via the bias resistor 107, and the source of the mixer FET 100 is grounded via the bypass capacitors 108 and 109. Further, the bias circuit positively biases the bias supply terminal 154 connected to the source of the mixer FET 100, thereby setting the gate bias of the mixer FET 100 to a negative voltage. That is, the gate potential of the mixer FET 100 is biased to a negative potential with respect to the source potential.
  • the gate bias of the mixer FET 100 is biased near the threshold voltage with a single power supply, and the operating point of the FET can be set in a region where the rate of change of the drain-source resistance is large, so that the conversion loss can be reduced.
  • a bypass capacitor 108 for the RF and LO frequencies is formed inside the semiconductor integrated circuit.
  • the bypass capacitor 109 for the IF frequency outside the semiconductor integrated circuit semiconductor integration with a limited chip area can be easily obtained.
  • the high-frequency bypass capacitor can be realized at 30 pF and the IF bypass capacitor can be realized at 1000 pF.
  • the high-frequency bypass capacitor 30 pF is a capacitance value that can be built into a semiconductor integrated circuit.
  • the bias supply terminal 154 is connected to the source of the mixer FET 100, but the same effect can be obtained by connecting to the drain side. Further, in FIG. 1, it goes without saying that the DC cut capacitors 110 and 111 may be incorporated in a part of the RF matching circuit 104 and a part of the IF matching circuit 111, respectively.
  • the gate voltage vs. drain current characteristics of a FET have the characteristics shown by the solid line in Fig. 2. If the FET is biased in the saturation region, the drain current will not change even if the drain bias changes. Small and negligible. Therefore, the drain current of the bias circuit FET 150 is I ds, the voltage between the gate and the source is V gs, the potential of the bias supply terminal is V bias, and the bias resistor that constitutes the pi. Letting the resistance values of 152 and 153 be Ra and Rb, respectively, Vgs is expressed by (Equation 1), Vbias is expressed by (Equation 2), and the gate voltage vs. drain current characteristic of FET 100 The intersection point A of (Equation 1) becomes the bias point.
  • Vg s -R aId s
  • V bias circuit for example, when the threshold value of FET becomes shallow, the operating point moves to point B as shown in FIG. 2 and Ids decreases, and as a result, Vbias also decreases. Conversely, when the FET threshold value becomes deeper, the bias point moves to the C point, so I ds increases, and as a result, Vbias increases.
  • the gate bias of the resistive mixer also fluctuates in accordance with the threshold and the change of the value so as to suppress the fluctuation of the characteristic of the resistive mixer caused by the change of the threshold value.
  • the child can be suppressed.
  • the bias circuit FET 150 and the mixer FET 100 are formed on the same substrate, they have the same temperature characteristics. Therefore, if the above operation is performed, the threshold fluctuation due to the temperature of the mixer FET 100 can be suppressed.
  • the bias circuit is not limited to the circuit shown in FIG. 1, but may be a circuit as shown in FIG. That is, (a) of FIG. 3 shows that the gut of the bias circuit FET 150 and the bias supply terminal 154 are connected via the resistor 171.
  • FIG. 3B shows the case where the drain of the bias circuit FET 150 and the drain bias terminal 15 1 are connected via a resistor 172.
  • FIG. 3C the gate of the bias circuit FET 150 and the bias supply terminal 154 are connected via the resistor 171, and the drain and drain of the bias circuit FET 150 are connected. 1 and 1 are connected via a resistor 172.
  • FIG. 3D shows the connection between the gate and the source of the FET 150 for the bias circuit. They are directly connected.
  • an inductor may be used instead of the resistor 171, and an inductor may be used instead of the resistor 172.
  • a circuit as shown in FIG. 4 may be used.
  • the circuit in FIG. 4 uses a diode 173 in place of the bias circuit FET 150 in the bias circuit portion of FIG. That is, the power source of the diode 173 is connected to one end of the resistor 152, and the anode of the diode 173 is connected to the drain bias terminal 155. Further, in the circuit of FIG. 4, a resistor and / or an inductor may be inserted between the diode 173 and the drain bias terminal 15 1.
  • FIG. 5 shows a configuration example in which the resistive mixer 161 in FIG. 1 is a single-balanced type.
  • the same or similar parts as those in the above-described circuit are denoted by the same reference numerals, and description thereof is omitted.
  • the sources of the two mixer FETs 100a and 100b are commonly connected and connected to a bias supply terminal 154 via a bias resistor 112.
  • connection point of the FET 100a. And 100b sources for the mixer operates as a virtual ground, so a grounding capacitor is not necessary, but it is actually grounded through the grounding capacitor. You may. According to this configuration, in addition to the same effects as the resistive mixer shown in FIG. 1, a resistive mixer having the characteristics of a single balance mixer can be realized.
  • the phase difference between the signals input to the RF terminals 101a and 101b is ⁇ 1
  • the phase difference between the signals input to the 0 terminals 1023 and 102b is ⁇ 2
  • the phase difference between the signals input to the IF terminals 103a and 104b is ⁇ 2.
  • the (m, n) -order harmonic signal generated by the two mixer FETs 100a and 100b is expressed by (Equation 3) at the IF end. It is synthesized with a phase difference ⁇ ⁇ (m, n). (Equation 3)
  • FIG. 6 shows an example of a configuration in which the resistive mixer 16 1 in FIG. 1 is a double-balanced type, and the same or similar parts as those in the above-described circuit are denoted by the same reference numerals. Is omitted.
  • the RF terminals 1 O la, 101, 0 terminals 102 &, 102 & b are input with balance signals 180 degrees out of phase with each other, and the IF terminals 103 a, 103 b A balance signal is output.
  • the four mixer FETs 100a, 100b, 100c, and 100d are connected in a ring, and one of the drain and source connection points is biased via the bias resistor 1 1 2 Connected to supply terminal 154.
  • a resistive mixer having the characteristics of a double balance mixer can be realized. In other words, isolation between the LO port, RF port, and IF port can be ensured, and signal wraparound between ports can be suppressed.
  • an up mixer that inputs an IF signal and outputs an RF signal can also be realized by a similar configuration.
  • the gate of the FET 100 has been described as being grounded via the bias resistor 107, but the present invention is not limited to this, and the gate of the FET 100 may be grounded via an inductor. .
  • the gate of the FET 100 may be grounded via a circuit in which the bias resistor 107 and the inductor are connected in series. Further, the gate of the FET 100 may be grounded via a circuit in which the bias resistor 107 and the inductor are connected in parallel. Also, a plurality of bias resistors and a plurality of inductors may be grounded via a circuit connected in series or in parallel. In short, it suffices that the gate of the FET 100 be grounded via a circuit that can make the bias voltage of the gate of the FET 100 an appropriate voltage. Note that the appropriate voltage in this case means, for example, a voltage near the threshold value of the FET 100 or a voltage at which the resistive mixer 161 of the present embodiment can operate.
  • circuits described above may be used instead of the piezo resistors 107a and 107 of the single-parallel resistive mixer shown in FIG. Further, the above circuits may be used instead of the bias resistors 107a and 197b of the dub-balanced resistive mixer shown in FIG.
  • FIG. 7 shows a configuration according to the second embodiment of the present invention.
  • the same or similar parts as in the above-described circuit are denoted by the same reference numerals, and description thereof will be omitted.
  • reference numeral 200 denotes a resonance circuit, which has a low impedance characteristic at IF frequency, LO frequency, and RF frequency, and has a high impedance characteristic at half the IF frequency.
  • the interference wave f UD represented by (Equation 4) is called a half IF spurious, and the interference wave falls into the IF frequency Therefore, it becomes a cause of deterioration of reception characteristics. (Equation 4)
  • the impedance of the resonance circuit is high impedance at the 1/2 IF frequency, so that the mixer F ET 100 has 1/2 f IF The components are suppressed. Therefore, since the interference wave falling into the IF frequency due to mixing with the 1 2 IF frequency component itself and other signal components is reduced, the reception characteristics can be improved.
  • Fig. 8 shows a configuration example of the resonance circuit.
  • 108 is a high frequency bypass capacitor
  • 201 is an IF bypass capacitor
  • 200 is a resonance circuit capacitor
  • 202 is a resonance circuit inductor.
  • the inductance of the resonance circuit inductor 202 is L1
  • the capacitance of the resonance circuit capacitor is C1
  • the capacitance of the high-frequency bypass capacitor 108 is C2
  • the capacitance of the IF bypass capacitor 201 is C3.
  • Zr (j ⁇ L1 + 1 / j ⁇ C1) / j ⁇ C4 / (j ⁇ L1 + 1 / j ⁇ C1 + 1 / j ⁇ C4)
  • the impedance Zr of the resonant circuit with respect to the IF frequency and the RF frequency and the LO frequency can be reduced by appropriately selecting a combination of Ll, Cl, and C4 that satisfies (Equation 6). It can be set to impedance.
  • RF frequency is 525 OMHz
  • LO frequency is 4680 MHz
  • IF frequency is 57 OMHz
  • L l 3.4 nH
  • C l 100 pF
  • C 2 30 pF
  • C 3 1000 pF
  • C4 1 100 pF satisfies the characteristics described above.
  • the resonance circuit is connected to the drain side of the mixer FET 100, and the impedance of the resonance circuit is configured to be high impedance for IF frequency and low impedance for 1/21 F frequency. The same effect can be obtained even if it does.
  • the resonance circuit is composed of a series LC resonance circuit and a parallel capacitor.
  • the resonance circuit has the above-described impedance characteristics with respect to the IF frequency and the 1Z2 IF frequency. It goes without saying that the same effect can be obtained by using the resonance circuit of FIG.
  • FIG. 10 shows a configuration according to the third embodiment of the present invention.
  • 301 indicates a source resistance
  • 302 indicates a gain control terminal
  • 303a and 303b indicate bias resistors.
  • the resistance values of the bias resistors 303a and 303b are expressed as Ra, Rb, Assuming that the resistance value of the resistor 301 is R c, the drain current of the bias circuit FET 150 is I ds, and the potential of the drain bias terminal 151 b is Vdd, the gate bias V bias of the mixer FET is Equation 7) can be expressed.
  • Vb ia s V d db / (R a + R b) One R cI d s
  • a function of a variable attenuator or a switch can be added to the mixer, and the circuit scale can be reduced.
  • FIG. 11 shows a configuration of the fourth embodiment of the present invention.
  • the same or similar parts as those in the above-described circuit are denoted by the same reference numerals and description thereof will be omitted.
  • reference numeral 400 denotes an IF blocking capacitor which exhibits high impedance characteristics with respect to the IF frequency and prevents leakage of the IF signal.
  • 401 is an RF blocking inductor which exhibits high impedance characteristics with respect to RF frequency and prevents RF signal leakage.
  • the input impedance of the IF port is 50 ⁇ .
  • the gate bias of the mixer FET 100 is biased such that the drain-source resistance with respect to the IF frequency is close to 50 ⁇ .
  • the impedance of each port is equal to the input impedance of the mixer FET 100.
  • the IF matching circuit which cannot be built-in because the occupied area is large is usually increased. Can be built in.
  • the input impedance of the FET is close to the impedance of each port, a resistive mixer with broadband matching can be realized.
  • the IF blocking capacitor 400 and the RF blocking inductor 410 if the RF frequency 5 25 O.MHz, LO frequency 4680 MHz, and IF frequency 57 7 MHz, the IF This can be realized with a locking capacitor 4 F and an RF blocking inductor 2.5 nH, which are values that can be built into a semiconductor integrated circuit.
  • one capacitor is used for IF blocking and one inductor is used for RF blocking.
  • the capacitors have sufficiently large impedances with respect to each other's frequency. It goes without saying that the same effect can be obtained by using the circuit having the above configuration.
  • FIG. 12 shows a configuration according to the fifth embodiment of the present invention.
  • 500 is a high-frequency amplifier
  • 501 is a source resistor
  • 502 is a bypass capacitor
  • 503 is a choke inductor
  • 504 is an IF matching circuit
  • 506 is a bias resistor.
  • the portion 505 surrounded by the dashed line constitutes a self-device-type high-frequency amplifier.
  • a transmission circuit that outputs a transmission signal and a reception circuit that inputs a reception signal The present invention also includes a communication device in which the resistive mixer of the present invention is used in the transmitting circuit and / or the receiving circuit.
  • the communication device of the present invention includes, for example, a mobile phone terminal, a base station device of a mobile phone terminal, a PHS terminal, a base station device of a PHS terminal, a car phone terminal, and the like.
  • the present invention enables the gate of the FET constituting the mixer with a single power supply to be biased in the vicinity of the threshold value, and further includes a bias circuit for absorbing the variation in the threshold value of the FET. Accordingly, it is possible to provide a low-distortion resistive mixer, a bias circuit, a high-frequency amplifier, and a communication device with small conversion loss and small characteristic variation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Superheterodyne Receivers (AREA)
  • Amplifiers (AREA)

Abstract

L'invention concerne un mélangeur à faible distorsion pouvant fonctionner avec une seule source d'alimentation en courant, et présentant une faible perte de conversion ainsi que des caractéristiques de faible variation. Le mélangeur présenté comporte un circuit de polarisation dans lequel la source d'un transistor à effet de champ (100) constituant le mélangeur est mise à la masse par l'intermédiaire de condensateurs (108, 109) est relié à une borne de polarisation (154), la grille dudit transistor à effet de champ (100) est mise à la masse par l'intermédiaire d'une résistance (107), et la polarisation de la grille dudit transistor à effet de champ (100) se fait à proximité du seuil, par une seule source de courant.
PCT/JP2001/007819 2000-09-13 2001-09-10 Melangeur resistif WO2002023714A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2000-278738 2000-09-13
JP2000278738 2000-09-13

Publications (1)

Publication Number Publication Date
WO2002023714A1 true WO2002023714A1 (fr) 2002-03-21

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Application Number Title Priority Date Filing Date
PCT/JP2001/007819 WO2002023714A1 (fr) 2000-09-13 2001-09-10 Melangeur resistif

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Country Link
WO (1) WO2002023714A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110800209A (zh) * 2017-06-29 2020-02-14 Hrl实验室有限责任公司 具有串联的有源器件的混频器

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129842A (ja) * 1991-11-06 1993-05-25 Sharp Corp Ｆｅｔミキサ
JPH05167352A (ja) * 1991-12-16 1993-07-02 Sharp Corp 周波数変換装置
JPH06276029A (ja) * 1993-03-18 1994-09-30 Sony Corp マイクロ波半導体集積回路
JPH10303651A (ja) * 1997-04-22 1998-11-13 New Japan Radio Co Ltd 周波数変換用半導体集積回路
JPH11330865A (ja) * 1998-05-18 1999-11-30 Mitsubishi Electric Corp ミクサ、バラン、送信装置および受信装置
JP2000188516A (ja) * 1998-12-21 2000-07-04 Mitsubishi Electric Corp ミキサ回路

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05129842A (ja) * 1991-11-06 1993-05-25 Sharp Corp Ｆｅｔミキサ
JPH05167352A (ja) * 1991-12-16 1993-07-02 Sharp Corp 周波数変換装置
JPH06276029A (ja) * 1993-03-18 1994-09-30 Sony Corp マイクロ波半導体集積回路
JPH10303651A (ja) * 1997-04-22 1998-11-13 New Japan Radio Co Ltd 周波数変換用半導体集積回路
JPH11330865A (ja) * 1998-05-18 1999-11-30 Mitsubishi Electric Corp ミクサ、バラン、送信装置および受信装置
JP2000188516A (ja) * 1998-12-21 2000-07-04 Mitsubishi Electric Corp ミキサ回路

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110800209A (zh) * 2017-06-29 2020-02-14 Hrl实验室有限责任公司 具有串联的有源器件的混频器
CN110800209B (zh) * 2017-06-29 2023-06-30 Hrl实验室有限责任公司 具有串联的有源器件的混频器

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