WO2001008458A1 - Structure de tableau de cablage a traversees superposees - Google Patents

Structure de tableau de cablage a traversees superposees Download PDF

Info

Publication number
WO2001008458A1
WO2001008458A1 PCT/JP2000/004880 JP0004880W WO0108458A1 WO 2001008458 A1 WO2001008458 A1 WO 2001008458A1 JP 0004880 W JP0004880 W JP 0004880W WO 0108458 A1 WO0108458 A1 WO 0108458A1
Authority
WO
WIPO (PCT)
Prior art keywords
layer
wiring board
wiring pattern
land
layer via
Prior art date
Application number
PCT/JP2000/004880
Other languages
English (en)
Japanese (ja)
Inventor
Masakazu Aoyama
Original Assignee
Ibiden Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP21012999A external-priority patent/JP4330713B2/ja
Priority claimed from JP21012899A external-priority patent/JP4330712B2/ja
Application filed by Ibiden Co., Ltd. filed Critical Ibiden Co., Ltd.
Publication of WO2001008458A1 publication Critical patent/WO2001008458A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0203—Fillers and particles
    • H05K2201/0206—Materials
    • H05K2201/0215—Metallic fillers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09536—Buried plated through-holes, i.e. plated through-holes formed in a core before lamination
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/0959—Plated through-holes or plated blind vias filled with insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/096—Vertically aligned vias, holes or stacked vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom

Definitions

  • the present invention relates to a wiring formed by alternately stacking conductor layers and insulating layers. More specifically, the present invention relates to a via-on-via structure in which a via for connecting a conductive layer to a conductive layer and a via in an upper layer are arranged close to each other.
  • Examples of conventional via-on-via structures include the full offset type shown in Fig. 7 and the lid-mounted type shown in Fig. 8.
  • the full offset type has a structure in which the upper via 102 is offset from the inner via 101. This ensures reliable conduction between the conductor layers 104 and 105 by contacting the upper vias 102 with the land portions 106 of the inner vias 101.
  • the resin part 113 and the land part 116 of the inner via 111 are covered with the covered layer 117, and the upper via 112 is provided directly above it. It has a structure. This is done by covering the resin part 113 with a conductive lidding layer 117 so that the conductor layer 114 and the conductor layer 115 can be reliably connected at the upper layer 112. It was done.
  • the conventional via-on-via structures described above have problems.
  • the overall size in the horizontal direction in the figure becomes considerably large. This is an obstacle to finer wiring patterns.
  • the lid-covered structure although there is no problem in terms of size, the number of processes for forming the lid-covered layer 117 increases.
  • the lid-covered layer 1 17 is easy to peel off, conduction is not so good in practice. This is due to the thermal effect when laser processing the insulating layer 118 to form the upper via 112. Since the resin portion 113 is usually 100% resin, the volatile components form bubbles between the lid layer and the lid layer by the heat of the laser. Is slightly lifted.
  • the present invention has been made to solve the above-mentioned problems of the conventional via-on-via structure. It is. In other words, the goal is to provide a wiring board with a via-on-via structure that is excellent in size, manufacturing process, and conductivity.
  • the present invention made for the purpose of solving this problem,
  • [Configuration 1] A first conductive layer, a second conductive layer, a first insulating layer between them, a second m deposited on the second conductive layer, and a second conductive layer on the second conductive layer.
  • the first conductor layer and the second conductor layer are electrically connected to each other, and the first via filled with the inside, the second conductor layer and the second conductor layer are formed.
  • the second via has a larger diameter than the first via, and is formed so as to cover at least 1 Z 2 of an outer periphery of the first via. Via-on-via structure of the printed wiring board.
  • the second via which is the upper via, covers the land of the first via, which is the lower via. For this reason, conduction between the second conductor layer and the third conductor layer is assured without forming a cover layer. Therefore, the number of steps required for forming the lid-coating layer is reduced. Specifically, the number of steps is the same as in the case of the full offset type structure.
  • the second via extends over the part of the first via. For this reason, the amount of the second via protruding from the inside of the first via is not so large. Therefore, the size problem can be minimized.
  • a part of the first via is filled with a conductive paste. It is desirable that it be packed. This is because if the inside of the first via is merely a resin, this resin will be largely removed when the second insulating layer is laser-processed to form the second via.
  • the conductive paste is a dispersion of conductive powder such as metal in resin, and is more resistant to the effects of laser than a simple resin. For this reason, by using a conductive paste for the filling material in part (1) of the first via, scouring due to laser processing can be prevented. Further, the resistance between the second conductor layer and the third conductor layer in the second via can be further reduced.
  • the second via is formed so as not to protrude from the land portion of the first via. If the second via protrudes from the land of the first via to the outside, when the second insulating layer is laser-processed to form the second via, the first insulating layer is also processed at the protruding part. Because. For this purpose, the land portion of the first via should be slightly widened toward the direction where the second via is formed.
  • FIG. 1 is a cross-sectional view of a wiring board having a via-on-via structure according to the first embodiment
  • FIG. 2 is a perspective plan view thereof
  • FIG. 3 is a cross-sectional view showing a state in which an interphase insulating layer is applied
  • FIG. FIG. 4 is a cross-sectional view showing a state in which laser processing for forming a hole has been performed.
  • FIG. 5 is a cross-sectional view of a wiring board having a via-on-via structure according to the second embodiment
  • FIG. 6 is a plan perspective view thereof.
  • FIG. 7 is a cross-sectional view showing a conventional full offset type via-on-via structure
  • FIG. 8 is a cross-sectional view showing a conventional lid-mounted via-on-via structure.
  • the wiring board according to the present embodiment has a via-on-via structure shown in FIG.
  • This wiring board is composed of a core insulating layer 10, wiring pattern layers 11, 12 on the front and back surfaces thereof, an interlayer insulating layer 13 deposited on the wiring pattern layer 11, and an interlayer insulating layer 13. And a wiring pattern layer 14 formed thereon.
  • an inner layer via 15 is provided for making the wiring pattern layer 11 and the wiring pattern layer 12 conductive.
  • the inner via 15 forms a drill hole in the core insulating layer 10 and forms a plating layer 16 extending from the wall surface to the front and back surfaces to establish conduction between the wiring pattern layer 11 and the wiring pattern layer 12. , And the inside was filled with silver paste 17.
  • the portion of the wiring pattern layer 11 near the inner layer via 15 is called a land 19.
  • An upper via 18 is provided at the position immediately above and to the left of the ⁇ layer via 15 in the figure.
  • the upper via 18 is formed by drilling a hole in the interlayer insulating layer 13 by laser processing to partially expose the wiring pattern layer 11 and the silver paste 17 to form a plating layer extending inside and outside the hole. is there. As a result, the continuity between the wiring pattern layer 11 and the wiring pattern layer 14 is established.
  • the thickness of the core insulating layer 10 is 500 / im, and the thickness of the interlayer insulating layer 13 is 50 ⁇ .
  • the thickness of the plating layer 16 of the inner via 15 is 15 ⁇ .
  • the thickness of the wiring pattern layers 11 and 12 is 27 ⁇ m, which is the total of 12 ⁇ of copper foil and 15 ⁇ of plating. ⁇
  • the diameter (drill hole diameter) of the upper layer via 15 is 300 / xm, and the diameter (laser processing diameter) of the upper layer via 18 is 100 ⁇ .
  • the thickness of the wiring pattern layer 14 is 15 / zm.
  • FIG. 2 shows the upper layer via 15, its land 19, and the upper layer via 18.
  • the land 19 is provided around the upper layer via 15, but is slightly extended toward the upper layer via 18.
  • the maximum dimension D, in FIG. 2, extending between the inner via 15 and the upper via 18, is smaller than the sum of the respective diameters of the inner via 15 and the upper via 18 by the amount of overlap. It is about. If the width of land 19 is 150 ⁇ , the land diameter 0 2 in the horizontal direction in Fig. 2 is 65 ⁇ . Note that the vertical direction of the land diameter D 3 in FIG. 2 is a 6 0 0 ⁇ ⁇ . If a full offset type structure is adopted, it is necessary to have about 550 ⁇ and D 2 about 850 ⁇ m. In the present embodiment, by overlapping the upper via 18 and the inner via 15, an obstacle to fine wiring pattern is eliminated.
  • Figure 3 shows a state in which the inner via 15 is filled with a silver paste 17 to flatten its surface, and an interlayer insulating layer 13 is applied. Steps until this state is obtained are a combination of known techniques, and thus description thereof is omitted.
  • FIG. 4 shows a state in which a hole 18 has been formed in the interlayer insulating layer 13 by laser processing.
  • the laser ripening affects the silver paste 17 filling the vias 15 at the end of processing.
  • silver paste 17 is much more heat-resistant than mere resin, it hardly deforms.
  • the area where the hole 18 is formed does not protrude from the land 19 of the inner via 15. If it protrudes, not only the interlayer insulating layer 13 but also the core insulating layer 10 may be processed at the protruding portion. In the present embodiment, there is no such fear.
  • a plating layer is formed on the inside and outside of the hole 18 in the state of Fig. 4 and pattern processing is performed, a wiring pattern 14 is obtained as shown in Fig. 1.
  • the wiring board according to the present embodiment has a via-on-via structure shown in FIG.
  • This wiring board includes a core insulating layer 10, wiring pattern layers 11 and 12 on the front and back surfaces thereof, an interlayer insulating layer 13 applied on the wiring pattern layer 11, and an interlayer insulating layer 13. And a wiring pattern layer 14 formed thereon.
  • an inner layer via 15 is provided for making the wiring pattern layer 11 and the wiring pattern layer 12 conductive.
  • the inner via 15 forms a drill hole in the core insulating layer 10 and forms a plating layer 16 extending from the wall surface to the front and back surfaces to establish conduction between the wiring pattern layer 11 and the wiring pattern layer 12. , And the inside was filled with silver paste 17.
  • the portion of the wiring pattern layer 11 near the inner layer via 15 is called a land 19.
  • an upper via 18 having a diameter larger than the upper via 15 is provided.
  • the upper via 18 is formed by drilling a hole in the interlayer insulating layer 13 by laser processing to partially expose the wiring pattern layer 11 and the silver paste 17 to form a plating layer extending inside and outside the hole. .
  • conduction between the wiring pattern layer 11 and the wiring pattern layer 14 is established.
  • the thickness of the core insulating layer 10 is 50 O / zm
  • the thickness of the interlayer insulating layer 13 is Thick
  • the height is 50 ⁇ .
  • the thickness of the plating layer 16 of the inner via 15 is 15 / zm.
  • the thickness of the wiring pattern layers 11, 12 is 27 ⁇ , which is the total of 12 ⁇ of copper foil and 15 ⁇ of plating.
  • the diameter of the inner via 15 (drill hole diameter) is 300 ⁇ , and the diameter of the upper via 18 (laser processing diameter) is 350 ⁇ .
  • the thickness of the wiring pattern layer 14 is 15 ⁇ .
  • the upper via 18 is provided so as to cover the entire inner via 15. This is shown in the perspective plan view of Fig. 6.
  • Figure 6 shows the inner via 15, its land 19, and the upper via 18.
  • the land 19 is provided around the inner via 15 with a width of 15 ⁇ .
  • the diameter Di of the via-on-via structure is equal to the diameter of the upper via 18, and is 350 / m.
  • the diameter D 2 of land 19 is 600 ⁇ . If a full offset type structure is used, the maximum diameter of the via-on-via structure needs to be about 550 ⁇ and the maximum diameter of the land needs to be about 850 ⁇ as described above. In the present embodiment, increasing the size of the upper-layer via 18 eventually contributes to finer wiring patterns.
  • the manufacturing process of the wiring board of the present embodiment is the same as that of the above-described first embodiment, and a description thereof will be omitted.
  • the upper via 18 having a larger diameter is provided immediately above the inner via 15.
  • the in-plane dimensions of the via-on-via structure are consequently kept small.
  • the wiring pattern 14 is in direct contact with the land 19 (wiring pattern 11) of the inner via 15, so that conduction is ensured.
  • the manufacturing process is simple.
  • the filler of the inner via 15 is silver paste 17
  • damage to the inside of the inner via 15 during laser processing for forming the upper via 18 is minimized.
  • the contact resistance between the wiring pattern 14 and the wiring pattern 11 is reduced by the silver paste 17 having conductivity.
  • the upper via 18 does not protrude from the land 19, the possibility that the core insulating layer 10 is processed during laser processing for forming the upper via 18 is eliminated. .
  • a via-on-via structure for a wiring board with excellent size, process, and conductivity has been realized.
  • the filling material for the inner via 15 is silver pace.
  • a material using another metal such as a copper paste may be employed.
  • a wiring board having a via-on-via structure excellent in all of size, manufacturing process, and conductivity is provided.

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Cette invention concerne un tableau de câblage dont la structure à traversées superposées est remarquable en termes de dimensions, de procédé de fabrication et de liaison électrique. Pour la fabrication de cette structure, on remplit l'intérieur d'une traversée de couche intérieure (15) avec une pâte d'argent (17) et l'on forme par usinage au faisceau laser une traversée de une couche supérieure (18) qui touche à la fois l'intérieur de la traversée de la couche intérieure et un cordon (19). Par voie de conséquence, cette structure à traversées superposées se caractérise par de faibles dimensions intérieures. De plus, la liaison électrique est garantie du fait qu'un motif de câblage (14) est directement en contact avec le cordon (19) [motif de câblage (11)] de la traversée de la couche intérieure (15) alors même que ladite couche ne comporte pas de revêtement supérieur. Par ailleurs, le procédé de fabrication se distingue par sa simplicité. Enfin, comme le matériau de remplissage utilisé pour la traversée de la couche intérieure (15) est constitué par de la pâte d'argent (17), les dégâts infligés à l'intérieur de la traversée (15) lors de l'usinage par faisceau laser de la traversée de couche supérieure (18) sont réduits au minimum.
PCT/JP2000/004880 1999-07-26 2000-07-19 Structure de tableau de cablage a traversees superposees WO2001008458A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP11/210129 1999-07-26
JP21012999A JP4330713B2 (ja) 1999-07-26 1999-07-26 配線基板のビアオンビア構造およびその製造方法
JP21012899A JP4330712B2 (ja) 1999-07-26 1999-07-26 配線基板のビアオンビア構造
JP11/210128 1999-07-26

Publications (1)

Publication Number Publication Date
WO2001008458A1 true WO2001008458A1 (fr) 2001-02-01

Family

ID=26517877

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/004880 WO2001008458A1 (fr) 1999-07-26 2000-07-19 Structure de tableau de cablage a traversees superposees

Country Status (1)

Country Link
WO (1) WO2001008458A1 (fr)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677663A (ja) * 1992-08-28 1994-03-18 Ibiden Co Ltd 多層プリント配線板の製造方法
JPH07283538A (ja) * 1994-04-14 1995-10-27 Ibiden Co Ltd 多層プリント配線板の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0677663A (ja) * 1992-08-28 1994-03-18 Ibiden Co Ltd 多層プリント配線板の製造方法
JPH07283538A (ja) * 1994-04-14 1995-10-27 Ibiden Co Ltd 多層プリント配線板の製造方法

Similar Documents

Publication Publication Date Title
JP4614278B2 (ja) 電子回路ユニット、及びその製造方法
CN106409700B (zh) 介电材凹穴内设有电性元件的可堆叠式线路板制作方法
KR100213857B1 (ko) 반도체장치의 제조방법 및 반도체장치의 패키지
CN102111952B (zh) 多层布线基板
TWI500361B (zh) 多層配線板
CN105702649B (zh) 具有整合双布线结构的线路板及其制作方法
KR20000057331A (ko) 땜납 볼 본드 사이트로부터 측면으로 오프셋된 비아를 갖는 ｔａｂ 테이프 볼 그리드 어레이 패키지
CN103460820A (zh) 布线板及其制造方法
TW200913804A (en) Wiring substrate and the method of manufacturing the same
CN108882500A (zh) 柔性电路板及其制作方法
CN104244582A (zh) 埋入式高密度互连印刷电路板及其制作方法
WO2007139076A1 (fr) tableau de connexions
CN107305848A (zh) 封装基板、封装结构及其制作方法
TW201703592A (zh) 印刷電路板及製造印刷電路板之方法
CN113474853A (zh) 印刷配线板及印刷配线板的制造方法
JP5066461B2 (ja) 配線構造及び多層プリント配線板。
CN103716992A (zh) 具有内嵌元件、内建定位件、及电磁屏障的线路板
WO2001008458A1 (fr) Structure de tableau de cablage a traversees superposees
JP2000068322A (ja) 半導体装置及びその製造方法
JP4330713B2 (ja) 配線基板のビアオンビア構造およびその製造方法
TWI395521B (zh) 埋入式結構及其製法
JP4330712B2 (ja) 配線基板のビアオンビア構造
CN110072326B (zh) 多层电路板及其制造方法
CN107230640A (zh) 具散热座及双增层电路的散热增益型半导体组件及其制法
JP5910163B2 (ja) 部品内蔵樹脂多層基板およびその製造方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
122 Ep: pct application non-entry in european phase