WO1999052152A1 - Dispositif semi-conducteur et convertisseur de puissance - Google Patents

Dispositif semi-conducteur et convertisseur de puissance Download PDF

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Publication number
WO1999052152A1
WO1999052152A1 PCT/JP1999/000866 JP9900866W WO9952152A1 WO 1999052152 A1 WO1999052152 A1 WO 1999052152A1 JP 9900866 W JP9900866 W JP 9900866W WO 9952152 A1 WO9952152 A1 WO 9952152A1
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Prior art keywords
semiconductor layer
semiconductor
conductivity type
layer
semiconductor device
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PCT/JP1999/000866
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English (en)
Japanese (ja)
Inventor
Katsunori Asano
Yoshitaka Sugawara
Takayuki Iwasaki
Toshiyuki Ohno
Tsutomu Yatsuo
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Hitachi, Ltd.
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Publication of WO1999052152A1 publication Critical patent/WO1999052152A1/fr

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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
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    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
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    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/407—Recessed field plates, e.g. trench field plates, buried field plates

Definitions

  • the present invention relates to a high withstand voltage semiconductor device and a power converter using the same.
  • High-breakdown-voltage / high-current structures using silicon as the element material have been adopted as high-breakdown-voltage semiconductor devices for large-capacity power conversion.
  • SiC silicon force—bond
  • diamond diamond
  • the critical electric field of these materials is more than 10 times that of silicon and extremely large. . Therefore, the thickness of the drift layer of the semiconductor device can be reduced to about 1/10 or less, and the carrier concentration can be increased to 10 times or more.
  • the electrical resistance can be reduced to about 1/100 or less, so that semiconductor devices using these materials are expected to be able to achieve a significant reduction in loss.
  • a semiconductor device formed of a high critical electric field material such as SiC
  • an electric field that is 10 times or more higher than that of a silicon semiconductor device is generated inside a semiconductor device in an off state, so that breakdown due to electric field concentration occurs.
  • evening portion refers to various semiconductor layers provided around the main junction to reduce electric field concentration near the main junction of the semiconductor device.
  • Termination Extension Uses evening mitigation technology such as FLR (Field Limiting Ring) or FMR (Floating Metal Rings) to provide evening mitigation parts.
  • FLR Field Limiting Ring
  • FMR Floating Metal Rings
  • the electric field at the The conventional evening mining technique described above is not suitable.
  • the reason is that the width of the depletion layer spread over the drift layer is small in the above-mentioned termination technology, and the electric field cannot be sufficiently reduced.
  • a JTE region is formed around the end of the main junction and a depletion layer is spread over the entire JTE region when a high voltage is applied.
  • the depletion layer is also extended in the depth direction of the n-drift layer in the outer peripheral direction of the main junction, and the electric field at the end of the main junction is reduced.
  • the concentration of the JTE region is increased, the depletion layer spreads in the n-drift layer, but the width of the depletion layer at the end of the JTE region decreases. If the concentration of the JTE region is too low, the depletion layer does not expand, the electric field at the end of the main junction increases, and the breakdown voltage decreases.
  • a depletion layer is extended into a drift layer between the FLR layers by using a plurality of FLR layers as an evening luminescence portion.
  • the depletion layer does not need to be fully extended in the FLR layer, so that the FLR layer only needs to have a high concentration of a certain concentration or more, which is easy to realize.
  • the occupied area increases. That is, since a plurality of FLR layers are formed so as to surround the outer periphery of the active region, even if the width is small, it occupies a large area. Therefore, in a limited area of the semiconductor device, the area of the active region must be reduced by an amount corresponding to the area of the FLR layer, which causes a problem in that a current capacity is reduced and an on-resistance is increased.
  • a plurality of grooves (hereinafter referred to as trenches) are formed so as to surround the periphery of the main junction, and a drift layer at the bottom of each trench is formed.
  • An evening minion portion having a semiconductor layer of a conductivity type different from the conductivity type of the drift layer is formed therein.
  • a plurality of trenches are formed in the drift layer so as to surround the periphery of the main junction, and a short-circuit junction (hereinafter referred to as a Schottky contact) is formed at the bottom of each trench. ) Is provided. Due to the electric field effect of the conductive layer, the depletion layer expands in the drift layer and reduces the electric field, so that electric field concentration near the main junction is avoided and the withstand voltage of the semiconductor device is improved.
  • the electric field is reduced by expanding the depletion layer mainly in the drift layer between the trench bottom and the trench. Since the depletion layer hardly spreads in the semiconductor layer for termination between the bottom of the trench and the trench, the concentration only needs to be higher than a certain concentration, and no special high precision is required for the concentration control. Easy to manufacture.
  • the power converter of the present invention is a power converter using the high-voltage semiconductor device of the first mode or the second mode as a switching element.
  • the high withstand voltage, large current capacity, and low on-resistance characteristic of the high withstand voltage semiconductor device of the present invention can realize a high withstand voltage, large current, and low loss power converter.
  • FIG. 1 is a plan view of a trench type MOSFET having an evenly spaced trench type minute portion, which is a semiconductor device according to a first embodiment of the present invention.
  • FIG. 2 is a sectional view taken along the line II-II of FIG.
  • FIG. 3A is a cross-sectional view of main parts of the semiconductor device of the first embodiment
  • FIG. 3B is a cross-sectional view of main parts of a semiconductor device having a conventional FLR (Field Limiting Ring).
  • FLR Field Limiting Ring
  • FIG. 4 is a cross-sectional view of a trench-type MOSFET having unevenly-spaced trench-type light-emitting portions, which is a semiconductor device according to a second embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of a trench-type MOS FET having an auxiliary electrode (field plate) and an equally-spaced trench-type light-emitting portion, which is a semiconductor device according to a third embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of a trench type MOSFET having an auxiliary electrode (field plate) and an equally spaced trench type minute luminescent portion, which is a semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of a trench type MOS FET having a shallow equally-spaced trench type minute portion, which is a semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 8 is a cross-sectional view of a MOSFET having a torch type evening luminescence type portion having a Schottky contact, which is a semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 9 is a sectional view of a MOS FET having a trench type termination portion having a Schottky contact, which is a semiconductor device according to a seventh embodiment of the present invention.
  • FIG. 10 is a cross-sectional view of a MOSFET having a trench type termination type portion having a Schottky contact, which is a semiconductor device according to an eighth embodiment of the present invention.
  • FIG. 11 is a configuration diagram of a ninth embodiment of a semiconductor device according to the present invention, and is a cross-sectional view of an evening luminescence region in the semiconductor device.
  • FIG. 12 is a configuration diagram of a semiconductor device according to a tenth embodiment of the present invention, and is a cross-sectional view of a semiconductor device in a sunset region.
  • FIG. 13 is a configuration diagram of a first embodiment of a semiconductor device according to the present invention, and is a cross-sectional view of a semiconductor device in a light-emitting region.
  • FIG. 14 is a block diagram of a twelfth embodiment of a semiconductor device according to the present invention. -It is sectional drawing of a termination area.
  • FIG. 15 is a circuit diagram of an inverter device using the semiconductor device of the present invention.
  • FIG. 16 is a circuit diagram of a rectifier using the semiconductor device of the present invention. BEST MODE FOR CARRYING OUT THE INVENTION
  • FIG. 1 is a plan view of a trench-type MOSFET provided with equally spaced trench-type minute portions according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view taken along the line II-II of FIG. is there.
  • the trench type emission portion 39 is formed in an annular shape so as to surround the main junction 1.
  • the dimensions of each part in the specific example of this semiconductor device are as follows.
  • the thickness of the n-drift layer 6 is 50 m
  • the thickness of the n + drain layer 7 is 30 ⁇ zm.
  • the thickness of p + body layer 5 is 2.
  • the junction depth of n + source layer provided in p + body layer 5 is 0.5 m.
  • the depth and width of each wrench 9 is 4 m.
  • the thickness of the gate insulator layer 35 is 1 ⁇ m at the bottom of the trench and 0.1 ⁇ m at the side of the trench.
  • the thickness of the insulating layer 36 on the bottom and side surfaces of the trench 9 in the evening and minute portion 39 is 1 m.
  • the distance between adjacent trenches 9 in the evening part 39 is 4 m.
  • the thickness of the insulating layer 35 on the bottom and side surfaces of the trench gate 10 may both be about 0.4 ⁇ m.
  • the distance between the surface of the main junction 1 and the bottom of the trench 9 may be 4 ⁇ m or less, preferably 1.5 / m or less.
  • the gate electrode 13 has a stripe shape, but the shape may be, for example, a circle or a square.
  • the gate electrode 13 may be, for example, 10 or more stripes.
  • the manufacturing process of the semiconductor device of the present embodiment is as follows. First, an n + type SiC (carbon silicon nitride) substrate having an impurity concentration of 10 18 to 10 2 () atm / cm 3 functioning as the drain layer 7 is prepared. 14 to 10 16 atm / cm 3 impurity concentration of S i C n- drift layer 6 It is formed by a vapor phase growth method or the like. Next, an S i C p + layer having an impurity concentration of about 10 16 to 10 18 atm / cm 3 is formed on the ⁇ -drift layer 6 by a vapor phase growth method or the like.
  • an n + region having an impurity concentration of about 10 18 atm / cm 3 is selectively formed in a desired region by ion implantation of nitrogen, phosphorus, or the like.
  • the substrate having undergone the above-described steps is anisotropically etched to form a trench gate 10 and a bottom portion 39 through which the p + layer penetrates and the bottom enters the n- drift layer 6 by a predetermined distance.
  • a trench 9 is formed.
  • ap + layer 2 having an impurity concentration of about 10 16 to 10 18 atm / cm 3 is formed in a range of 0.5 m from the bottom of the trench 9 by ion implantation of boron, aluminum, or the like. I do.
  • insulator layers 35 and 36 of Si 02 are formed on the inner wall of the trench gate 10 and the inner wall of the trench 9 for the evening luminescence portion 39.
  • the thickness of the insulating layer 35 on the inner wall of the trench gate 10 is about 0.1 ⁇ m, but the thickness of the insulating layer on the inner wall of the trench 9 for the evening and minute portion 39 is as follows. It may be as thick as 0.5 to 1 / m.
  • polysilicon containing a high concentration of phosphorus is deposited and buried in the trench portion 9 and the trench gate 10.
  • the gate electrode 13 is formed by leaving the polysilicon in the trench gate 10 and removing the polysilicon in other portions.
  • a source electrode 12 is formed on the surface of the p + layer 5 with aluminum, nickel, or the like.
  • the drain electrode 11 is formed on the surface of the drain layer 7 of the substrate to complete the process.
  • the p + layers 3 and 5 are formed by an epitaxy method, they can also be formed by an ion implantation method.
  • the first feature of the structure is that the p + layer 2 used as FLR is at the bottom of the trench 9 and the p + layer 3 is between adjacent trenches 9.
  • the depletion layer 30 shown by the dotted line becomes the main part between the p + body layer 5 and the n ′′ ′′ drift layer 6. It spreads from the junction 1 in the direction of the drain electrode 11 and the source electrode 12 to block the voltage.
  • the depletion layer 30 mainly extends to the trench bottom p + layer 2 and the trench between the trenches p + layer 3 and the n_ layer 4, and the main junction at the end of the active region 1 A Relax the electric field of 1.
  • the impurity concentration of the p + layer 3 between the trench bottom p + layer 2 and the trench is increased to a high concentration of 1016 atm / cm3 or more. You do not need to precisely control the concentration. Since the accuracy of the concentration control technique may be low, the production is easy and easy to realize.
  • the inter-trench n "" layer 4 is formed along the wall surface of the trench 9 between the inter-trench P + layer 3 and the trench bottom p + layer 2 in the depth direction of the drift layer 6 (the direction perpendicular to the surface of the semiconductor device). Since it forms between them, it does not affect the increase in surface area.
  • the area of the active region 1A can be increased by an amount corresponding to the dimension in the depth direction of the n-layer 4 between the trenches, and the current capacity can be increased and the on-resistance can be reduced.
  • the process can be simplified because the trench 9 for the minute portion 39 can be formed at the same time.
  • the interior of the trench 9 and the trench gate 10 with polysilicon, Si 2, or the like, contamination of the surface of the semiconductor device can be prevented, and high reliability can be realized.
  • FIG. 3A shows an example of the dimensions of each part of the trench type portion 39 of this embodiment.
  • the conventional OS with FLR has the same breakdown voltage as this semiconductor device.
  • Figure 3 (b) shows the dimensions of the FET at sunset.
  • the horizontal dimension of the trench bottom P + layer 2 and the trench p + layer 3 is 2 / m, respectively, and the total dimension is 4 ⁇ m.
  • the horizontal dimension of the two p + layers 2A and 2B is 2 mm each, and the total dimension is 4 mm.
  • the distance of n—layer 4B between two p + layers 2 A and 2 B is 1 m
  • the distance of n_ layer 4 A between p + layer 2 A and p + body layer 5 is l ⁇ m. Therefore, the total size is 6 ⁇ m.
  • the ⁇ between the trenches corresponding to the n-layers 4 A and 4 B in FIG. 3B is the ⁇ + between the trenches in the depth direction of the drift layer 6. Since it is formed between the layer 3 and the ⁇ + layer at the bottom of the trench, the ⁇ -layer 4 between the trenches is irrelevant to the increase in the area of the evening luminescence portion 39. Surface area is reduced. As a result, the area of the termination section 39 of this embodiment is two thirds that of the conventional FLR, and the semiconductor device of the same size increases the area of the active region 1 mm by that much. To increase current capacity and reduce on-resistance. W
  • a semiconductor device having three trench-type light-emitting portions 39 as shown in FIG. 1 has been described.
  • more trench-type light-emitting portions 39 are provided.
  • a higher withstand voltage can be realized.
  • the withstand voltage of 4800 V in the case of providing the evening light portion 39 having three trenches increased to 5300 V in the case of providing the terminal portion 39 having five trenches.
  • the process is simplified by setting the impurity concentration of the p + layer 2 at the bottom of the trench and the P + layer 3 between the trenches to be almost the same.
  • the on-characteristics of the M ⁇ SFET are changed by individually changing the impurity concentrations.
  • the breakdown voltage can be independently improved, so that higher performance can be achieved. Further, the on-characteristics and breakdown voltage are further improved by setting the impurity concentration of the p + layer 2 at the bottom of the plurality of trenches to a predetermined value and setting the impurity concentration of the p + layer 3 between the plurality of trenches to a predetermined value. be able to.
  • the impurity concentration of the P + layer 2 at the bottom of the trench is 3 ⁇ 10 17 atm / cm 3 and the impurity concentration of the p + layer 3 between the trenches is 10 18 atm / cm 3
  • the breakdown voltage is 4800 V, but The on-resistance was reduced from 35 ⁇ cm 2 to 28 mQcm 2 .
  • the impurity concentration of the bottom p + layer 2 and the p + layer 3 between the trenches the impurity concentration of the innermost one is highest, and the impurity concentration of the outermost one is higher toward the outer circumference. It may be formed so as to gradually decrease.
  • the impurity concentration of the p + layer 2 at the bottom of the innermost trench 9 and the p + layer 3 between the trenches is 10 19 atm / cm 3
  • the p + layer 2 at the bottom of the nine trenches 9 and the p + layer 3 between the trenches were formed so that the impurity concentration was gradually reduced from 5 ⁇ 10 18 to 10 16 atm / cm 3 .
  • the breakdown voltage could be increased to 20 KV.
  • FIG. 4 is a sectional view of a semiconductor device according to a second embodiment of the present invention.
  • the semiconductor device of this embodiment is a trench MOSFET having a termination portion 39 having unequally spaced trenches.
  • the width of the trench 9A of the first-stage trench-type minute portion 39A adjacent to the active region 1A is larger than the width of the other trenches 9B.
  • Tren A p + electric field relaxation layer 40 is formed at the bottom of the gate 10.
  • the other configuration is the same as that of the first embodiment, and the description is omitted.
  • the depletion layer is further away from the main junction 1 by the trench bottom p + layer 2 A formed at the bottom of the first wide trench 9 A. Can be expanded.
  • the electric field at the end of the main junction 1 is further reduced, and a semiconductor device with a high breakdown voltage can be realized.
  • the withstand voltage could be set to 580V.
  • the breakdown voltage was able to be increased by about 25% as compared with a semiconductor device having a trench-type light-emitting portion in which trenches 9 having a width of 4 ⁇ m were formed at equal intervals.
  • the withstand voltage was further increased to 600 V. In this case, the on-resistance was 35 mQ / cm 2 , which was equivalent to that of the first embodiment.
  • FIG. 5 is a sectional view of a semiconductor device according to a third embodiment of the present invention.
  • the semiconductor device of the present embodiment is a trench MOSFET provided with an evenly spaced trench type minute portion having an auxiliary electrode (field plate) 14.
  • insulating layers 15 A and 15 such as SiO 2 are formed on the bottom and side surfaces of the trench 9 of the evening luminescence portion 39, respectively.
  • an auxiliary electrode 14 having one end in contact with the insulator layer 15 A on the bottom surface of the trench 9 is formed.
  • the other end of the auxiliary electrode 14 is brought into contact with a connection portion 3 A at the top of the p + layer 3 between the trenches.
  • the depletion layer 30 near the p + layer 2 at the bottom of the trench and the p + layer 3 between the trenches was further expanded in the direction of the drain electrode 11.
  • the depletion layer further expands on the outer periphery of the active region 1 A, and the electric field near the main junction 1 is further reduced.
  • the breakdown voltage was higher than that of the first embodiment by 35% or more.
  • the area occupied by the evening mining section could be reduced to about two-thirds of that of the conventional evening mining section.
  • FIG. 6 is a sectional view of a semiconductor device according to a fourth embodiment of the present invention, in which a trench type MOS SFET having an auxiliary electrode 14 (field plate) and an equally spaced trench type portion 39 is provided.
  • FIG. Forming an insulator layer 1 5 such as S I_ ⁇ 2 on the side and upper surface of the train Chi between the P + layer 3 of the trench 9 evening monomodal one Chillon 3 9 in the fourth embodiment.
  • the fourth embodiment is different from the third embodiment in that an auxiliary electrode 14 A having one end in contact with the insulator layer 15 on the upper surface of the inter-trench P + layer 3 and the other end in contact with the trench bottom p + layer 2 is formed. Different from the embodiment.
  • the electric field of the insulator layer 15 in the trench 9 is reduced.
  • the electric field near the main junction 1 was relaxed, and the breakdown voltage was increased by 35% or more as compared with the first embodiment.
  • the area occupied by the evening and mining section 39 was reduced to about two-thirds of that of the conventional evening and mining section.
  • FIG. 7 is a cross-sectional view of a trench type MOS FET in which a semiconductor device according to a fifth embodiment of the present invention includes a shallow-emission portion 39 having shallow, equally-spaced trenches 9.
  • the distance between the main surface 46 of the active region 1A and the surface of the junction 43 between the n-layer 4 and the p + layer 3 between the trenches in the evening portion 39 and the p + layer 3 between the trenches in the first embodiment is It is larger, but closer to the drain electrode 11 side than the position of the main junction 1.
  • the point that the thickness of the p + layer 3 between the trenches is smaller than that of the p + layer 2 at the bottom of the trench is also different from the first embodiment.
  • the depletion layer 30 is more likely to expand in the direction of the s drain electrode 11, and as a result, a high breakdown voltage semiconductor device can be realized. Also, the area occupied by the evening and mining section 39 can be reduced to two thirds as compared with the conventional one, as in the first embodiment.
  • FIG. 8 is a cross-sectional view of a trench MOSFET of a semiconductor device according to a sixth embodiment of the present invention, the trench MOSFET having a trench-type minute portion 39 having a Schottky junction (hereinafter referred to as a Schottky contact). is there.
  • a Schottky contact without forming the trench bottom p + layer 2 and the inter-trench p + layer 3 provided in the evening luminescence portion 39 of each of the above embodiments, a thin film of gold or platinum is used.
  • Schottky contacts 17 A, 17 B, 17 C, 17 D, 17 E and 17 F are formed on the surface of the drift layer 6.
  • Adjacent Schottky contacts for example, Schottky contacts 17 A and 17 B are provided on the n-drift layer 6 having a step, and each Schottky contact 17 A to 17 F defines an active region 1 A. Made into a ring to surround I have.
  • a Schottky contact 17 G is also formed on the surface of the ⁇ + layer 16 on the outermost periphery of the terminal portion 39 with gold, platinum, etc., and the inner edge of the short contact 17 G is the field limit. Evening n + layer 16 is further inside than the inner edge.
  • the Schottky contacts 17 A, 17 C, 17 E at the bottom of the trench and the Schottky contacts 17 B, 17 D, 17 F, and 17 G between the trenches cause the depletion layer 30 to become the drain electrode 1 1 Spread in the direction of.
  • the electric field in the vicinity of the main junction 1 is reduced, and the same withstand voltage characteristics as those of the first embodiment are exhibited.
  • the field limiter n + layer 16 prevents the depletion layer 30 from spreading to the end along the surface of the n ⁇ drift layer 6 even when the surface of the semiconductor device is contaminated, thereby preventing a reduction in withstand voltage.
  • the extension of the depletion layer 30 formed along the surface is reduced not only by the field limiter n + layer 16 but also by the short-circuit It is also suppressed by the 17 G field effect. As a result, it is possible to prevent the electric field strength from increasing in the field limiter n + layer 16 and prevent the withstand voltage from decreasing.
  • the withstand voltage becomes 450 V.
  • the semiconductor device of the sixth example it is 480 V. I was able to keep it. It is needless to say that if surface contamination can be prevented by means of packaging or the like, the intended effect can be achieved without providing the Schottky contact 17 G of the field limit n + layer 16.
  • FIG. 9 is a sectional view of a semiconductor device according to a seventh embodiment of the present invention.
  • the seventh embodiment is different from the sixth embodiment in that a P + layer 53 between trenches is formed by ion implantation instead of the Schottky contacts 17B and 17D17F between trenches in the sixth embodiment. This is different from the sixth embodiment.
  • An insulator layer 15 is formed on the side surface of each trench 9 of the evening light portion 39 and on the surface of the p + layer 53 between the trenches.
  • Schottky contacts 17 A, 17 C, and 17 E are provided in portions sandwiched between the insulating layers 15 on the bottom surface of the trench 9.
  • the semiconductor device of the seventh embodiment shows high pressure resistance, and the occupation area of the termination portion 39 is small.
  • Eighth embodiment >>
  • FIG. 10 is a sectional view of a semiconductor device according to an eighth embodiment of the present invention.
  • the eighth embodiment differs from the seventh embodiment in that Schottky contacts 17 A, 17 C, and 17 E are formed on the entire bottom surface of the trench 9 in the evening termination portion 39. And different.
  • Schottky connectors 17 A, 17 C and 17 E are formed on the entire bottom surface of the trench 9, the bottom end of the trench 9 in the evening metal part 39 when the semiconductor device is off.
  • the depletion layer also extends from the portion, the electric field in the n-layer 4 between the trenches near the side surface at the bottom of the trench 9 is further alleviated, and a high breakdown voltage can be achieved.
  • the gate G can be connected to the source S to function as a two-pole semiconductor device of the source S and the drain D, that is, a diode. Also in the diode configured in this manner, a high breakdown voltage can be achieved as in the case of the MOS FET described in each of the above embodiments, and a diode having a low loss and a large current capacity can be obtained.
  • FIG. 11 is a sectional view of a ninth example of a semiconductor device according to the present invention, which is a cross-sectional view of a termination region in the semiconductor device, wherein the semiconductor device is made of silicon carbide (SiC). (Insulated gate bipolar transistor) chip (SiC type IGBT chip).
  • SiC silicon carbide
  • IGBT chip Insulated gate bipolar transistor
  • FIG. 11 corresponds to a cross-sectional view of a known light-emitting region of this type of semiconductor device (IGBT chip).
  • 65 is a first semiconductor region having an n-type low impurity concentration (n ⁇ )
  • 64 is a second semiconductor region having a p-type high impurity concentration (P +)
  • 66 is a p-type high impurity concentration.
  • 67 is a fourth semiconductor region having an n-type high impurity concentration (n +)
  • 62 is an emitter electrode (first main electrode)
  • 61 is a collector electrode (
  • 70 is a junction region between the first semiconductor region 1 and the second semiconductor region 64
  • 63 is a ring-shaped metal region (auxiliary electrode) made of Schottky metal
  • 68 is a groove.
  • a second semiconductor region 64 is formed and arranged in a region slightly inside from the peripheral portion, and a fourth semiconductor region 67 is formed and arranged in the peripheral portion.
  • the third semiconductor region 66 is disposed in contact with the peripheral portion.
  • the emitter electrode 62 is formed and arranged on the exposed surface of the second semiconductor region 64, and is in low contact with the exposed surface of the second semiconductor region 64.
  • Collector electrode 61 is formed and arranged on the other main surface of third semiconductor region 66, and is in low-resistance contact with the other main surface of third semiconductor region 66.
  • a plurality of grooves 68 are formed between the second semiconductor region 64 and the fourth semiconductor region 67 on one main surface of the first semiconductor region 65.
  • a plurality of grooves 68 in the example shown in FIG. 11, four grooves 68 are formed.
  • a portion outside the junction portion 70 between the first semiconductor region 65 and the second semiconductor region 64 is a evening metallization region, where four ring-shaped metal regions 63 and grooves 6 are provided.
  • the FMR consists of eight parts.
  • the SiC type IGBT chip of the ninth embodiment having the above-described configuration operates as follows.
  • the gate electrode (Fig. (Not shown)
  • the SiC IGBT chip is cut off, a difference voltage between the emitter voltage and the collector voltage is applied to the first semiconductor region 65, and the difference is applied.
  • An electric field corresponding to the voltage is formed in the first semiconductor region 65.
  • This electric field forms a depletion layer (not shown in FIG. 11) in a region extending from the junction 70 between the first semiconductor region 65 and the second semiconductor region 64 to the inside of the first semiconductor region 65. This depletion layer extends in the direction in which the FMR is formed in the first semiconductor region 65.
  • the initial withstand voltage of the SiC type IGBT chip can be increased.
  • the SiC type IGBT chip Due to the long-term use of the SiC type IGBT chip, a positive charge is formed on the upper surface of the first semiconductor region 65 in the FMR forming portion. Even if electrons are induced inside the surface of the first semiconductor region 65 in the MR forming portion and a storage layer is formed, the four ring-shaped metal regions 63 forming the FMR are different from each other. It is arranged on the bottom of the groove 68 so as to make a Schottky junction with the first semiconductor region 65, and is adjacent to the first semiconductor region 65.
  • the ring-shaped metal The region 63 is less affected by the positive charge formed on the upper surface of the first semiconductor region 65, the interval between the ring-shaped metal regions 63 does not expand equivalently, and the SiC type IGBT chip is not formed.
  • the initial withstand voltage of the pump does not decrease. Further, by adopting the above structure, the voltage of the storage layer is shared between the ring-shaped metal regions 63 inside the surface of the first semiconductor region 65, and the voltage of the storage layer is hardly affected by the formation of the storage layer.
  • the depletion layer in the first semiconductor region 65 also extends in the direction in which the FMR is formed, regardless of the formation of the accumulation layer, and the decrease in breakdown voltage due to aging of the SiC type IGBT chip is almost nil. Does not occur.
  • FIG. 12 is a configuration diagram of a tenth embodiment of a semiconductor device according to the present invention, which is a cross-sectional view of an evening-minion region in the semiconductor device, wherein the semiconductor device is an SIC type IGBT chip.
  • the semiconductor device is an SIC type IGBT chip.
  • the structure shown in FIG. 12 also corresponds to a cross-sectional view of an evening luminescence region in a known semiconductor device (IGBT chip) of this type.
  • reference numeral 72 denotes an insulator, and the same components as those shown in FIG. 11 are denoted by the same reference numerals.
  • the ninth embodiment is configured such that the ring-shaped metal region 63 forming the FMR is Schottky-bonded to the bottom of the groove 68.
  • the ring-shaped metal region 63 is arranged so as to be Schottky-bonded to the bottom of the groove 68 while the upper surface of the ring-shaped metal region 63 is exposed.
  • the only difference is that the insulator 72 is filled in the groove 68 in which the ring-shaped mail region 63 is arranged, and in addition, the gap between the tenth embodiment and the ninth embodiment is different. There is no difference in configuration. For this reason, further description of the configuration of the tenth embodiment will be omitted.
  • the operation and the obtained effect of the tenth embodiment are substantially the same as the operation and the obtained effect of the ninth embodiment, further detailed description will be omitted. Since the groove 72 is filled with the insulator 72, the influence of the positive charge formed on the upper surface of the first semiconductor region 65 is limited to only the surface region of the first semiconductor region 65. Induced on the sides inside the groove 6-8 The number of electrons to be reduced, the adjacent ring-shaped metal region 6 inside the first semiconductor region 65
  • the spread of the depletion layer at the shortest position of the interval of 3 is not affected by the formed positive charge, and the interval of the ring-shaped metal regions 63 does not expand equivalently.
  • FIG. 13 is a configuration diagram of a first embodiment of a semiconductor device according to the present invention, which is a cross-sectional view of an evening luminescence region in the semiconductor device, wherein the semiconductor device is a SiC type IGBT chip. This shows an example.
  • FIG. 13 also corresponds to a sectional view of the evening-mine region in a known semiconductor device (IGBT chip) of this type.
  • IGBT chip semiconductor device
  • reference numeral 73 denotes a ring-shaped metal region (auxiliary electrode) made of Schottky metal
  • reference numeral 11 denotes an insulating layer, and other components identical to those shown in FIG. I have.
  • the ninth embodiment differs from the ninth embodiment in that the entirety of the ring-shaped metal region 63 forming the FMR is joined to the bottom of the groove 68 by a shot key.
  • a part of the ring-shaped metal region 73 is arranged so as to be short-circuited to the bottom of the groove 68 by the first embodiment.
  • the remainder of 3 is arranged on the side and top surfaces of the groove 68 via the insulating layer 11 so as to form a so-called field blade structure.
  • the eleventh embodiment and the ninth embodiment There is no difference between the two. Therefore, further description of the configuration of the eleventh embodiment is omitted.
  • the operation and the effect obtained in the eleventh embodiment are also substantially the same as the operation and the effect obtained in the ninth embodiment, so that the detailed description is omitted here. Since the ring-shaped metal region 73 has a field plate structure, it is possible to effectively reduce the electric field at the corners of the groove 68 where the electric field is easily concentrated.
  • FIG. 14 is a sectional view of a semiconductor device according to a 12th embodiment of the present invention.
  • FIG. 14 is a cross-sectional view of the semiconductor device in the evening luminescence region. This is an example of a T chip.
  • FIG. 14 also corresponds to a cross-sectional view of the evening luminescence region of a known semiconductor device (IGBT chip) of this type.
  • IGBT chip a semiconductor device of this type.
  • reference numerals 81, 82, 83, and 84 denote grooves, and the same components as those shown in FIG. 11 are denoted by the same reference numerals.
  • the ninth embodiment is different from the twelfth embodiment in that a groove 68 which forms an FMR and is arranged so that a ring-shaped metal region 63 is short-circuited to the bottom surface.
  • the twelfth embodiment increases the depth of the groove 81 closest to the first semiconductor region 65 and the depth of the groove 82 adjacent to the groove 81.
  • the depth of the groove 83 adjacent to the groove 82 is made the third deepest, and the depth of the groove 84 closest to the fourth semiconductor region 67 is made the shallowest, There is no difference between the twelfth embodiment and the ninth embodiment.
  • the initial withstand voltage of the SiC type IGBT chip of the twelfth embodiment is larger than that of the SiC type IGBT chip of the ninth embodiment. It becomes larger than the initial withstand voltage.
  • FIG. 15 is a circuit diagram showing an example of a three-phase inverter using a MOSFET and a diode to which the present invention is applied.
  • MOSFET SW11 ⁇ SW32 is a switching element with a high switching speed.
  • the switching element can have a high withstand voltage.
  • MOSFETs using SiC the on-resistance of semiconductor devices with a high breakdown voltage of 500 V or more increases, making it difficult to achieve high performance over a high breakdown voltage member.
  • the semiconductor device according to each of the embodiments of the present invention it is possible to achieve high performance of the high breakdown voltage invar device, that is, compactness, low loss, and low noise. As a result, the cost and efficiency of the system using the inverter can be reduced.
  • FIG. 16 is a circuit diagram showing a rectifier configured using a MOSFET and a diode to which the present invention is applied.
  • AC is converted to DC by four bridge-connected MOSFETs SW11, SW12, SW21, SW22 and diodes D11, D12, D21, D22.
  • the MOSFET is an element having a high switching speed, and by applying the present invention to the element and the diode, effects such as compactness, low loss, and low noise of the high-voltage rectifier can be obtained. Therefore, low cost and high efficiency of the system using the rectifier can be achieved.
  • the impurity concentration of the innermost periphery of each of the plurality of trench bottom p + layers 2 and the inter-trench p + layer 3 is maximized, Those located on the outer periphery may be formed so that the impurity concentration gradually decreases toward the outer periphery.
  • the impurity concentrations of both may be set to arbitrary values.
  • the present invention can be applied to other semiconductor materials such as silicon and gallium arsenide.
  • it is effective for wide gap semiconductor materials such as diamond and gallium nitride.
  • the drift layer 6 is an n-type element.
  • the n-type layer is changed to the p-type layer and the p-type layer is changed.
  • the structure of the present invention can be applied.
  • the applicable elements are IGBT, GTO, SI transistor, SI thyristor, diode, thyristor, etc.
  • the active region or main junction structure can be any of planar type, trench type, buried type etc. It can be applied to the case.
  • a plurality of trenches are provided so as to surround the main junction of the semiconductor device, and a semiconductor layer of a conductivity type opposite to that of the drift layer is formed at the bottom of each trench and between adjacent trenches.
  • the area of the active region must be increased Therefore, the current capacity can be increased and the on-resistance can be reduced. As a result, a high breakdown voltage semiconductor device having a terminal structure with a small occupied area can be realized without the need for ultra-high-accuracy concentration control technology.

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Abstract

L'invention concerne un dispositif semi-conducteur haute tension qu'on obtient en réduisant la zone consacrée à la terminaison. Dans la zone de terminaison d'un dispositif semi-conducteur, une pluralité de tranchées (9) sont formées autour d'une section (1) de jonction principale. Une couche p+ ou un contact de Schottky sont formés au fond de chaque tranchée (9). Une couche (4) n- est formée entre les tranchées de manière qu'une zone de déplétion s'étende entre la couche p+ située au fond des tranchées et la couche p+ située entre les tranchées.
PCT/JP1999/000866 1998-04-07 1999-02-24 Dispositif semi-conducteur et convertisseur de puissance WO1999052152A1 (fr)

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WO2005036650A2 (fr) * 2003-10-08 2005-04-21 Toyota Jidosha Kabushiki Kaisha Dispositif a semiconducteur du type a grille isolee et procede de fabrication
WO2005109514A2 (fr) * 2004-05-12 2005-11-17 Toyota Jidosha Kabushiki Kaisha Dispositif semi-conducteur à grille isolée
WO2006046388A1 (fr) * 2004-10-29 2006-05-04 Toyota Jidosha Kabushiki Kaisha Composant a semi-conducteur a grille isolee et son procede de fabrication
JP2007173319A (ja) * 2005-12-19 2007-07-05 Toyota Motor Corp 絶縁ゲート型半導体装置およびその製造方法
KR100830389B1 (ko) * 2004-05-12 2008-05-20 도요다 지도샤 가부시끼가이샤 절연 게이트형 반도체 장치
JP2012504335A (ja) * 2008-09-30 2012-02-16 ノースロップ グラマン システムズ コーポレーション ガードリング構造およびその製造方法
WO2015145939A1 (fr) * 2014-03-25 2015-10-01 Toyota Jidosha Kabushiki Kaisha Dispositif semi-conducteur du type à grille isolée
WO2021089808A1 (fr) * 2019-11-08 2021-05-14 Abb Power Grids Switzerland Ag Transistor bipolaire à grille isolée

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JP2003069045A (ja) * 2001-08-22 2003-03-07 Mitsubishi Electric Corp 半導体装置
JP5531620B2 (ja) * 2010-01-05 2014-06-25 富士電機株式会社 半導体装置
CN103390654B (zh) * 2012-05-10 2017-02-15 朱江 一种多沟槽终端肖特基器件及其制备方法
JP6277623B2 (ja) * 2013-08-01 2018-02-14 住友電気工業株式会社 ワイドバンドギャップ半導体装置

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WO2005036650A3 (fr) * 2003-10-08 2005-09-01 Toyota Motor Co Ltd Dispositif a semiconducteur du type a grille isolee et procede de fabrication
WO2005036650A2 (fr) * 2003-10-08 2005-04-21 Toyota Jidosha Kabushiki Kaisha Dispositif a semiconducteur du type a grille isolee et procede de fabrication
US7470953B2 (en) 2003-10-08 2008-12-30 Toyota Jidosha Kabushiki Kaisha Insulated gate type semiconductor device and manufacturing method thereof
US7586151B2 (en) 2004-05-12 2009-09-08 Toyota Jidosha Kabushiki Kaisha Insulated gate semiconductor device
WO2005109514A2 (fr) * 2004-05-12 2005-11-17 Toyota Jidosha Kabushiki Kaisha Dispositif semi-conducteur à grille isolée
JP2005327762A (ja) * 2004-05-12 2005-11-24 Toyota Motor Corp 絶縁ゲート型半導体装置
WO2005109514A3 (fr) * 2004-05-12 2006-06-29 Toyota Motor Co Ltd Dispositif semi-conducteur à grille isolée
JP4721653B2 (ja) * 2004-05-12 2011-07-13 トヨタ自動車株式会社 絶縁ゲート型半導体装置
KR100830389B1 (ko) * 2004-05-12 2008-05-20 도요다 지도샤 가부시끼가이샤 절연 게이트형 반도체 장치
WO2006046388A1 (fr) * 2004-10-29 2006-05-04 Toyota Jidosha Kabushiki Kaisha Composant a semi-conducteur a grille isolee et son procede de fabrication
KR100879327B1 (ko) * 2004-10-29 2009-01-19 도요타 지도샤（주） 절연 게이트 반도체 장치 및 그 제조방법
US8076718B2 (en) 2004-10-29 2011-12-13 Toyota Jidosha Kabushiki Kaisha Insulated gate semiconductor device and method for producing the same
JP2007173319A (ja) * 2005-12-19 2007-07-05 Toyota Motor Corp 絶縁ゲート型半導体装置およびその製造方法
JP4735235B2 (ja) * 2005-12-19 2011-07-27 トヨタ自動車株式会社 絶縁ゲート型半導体装置およびその製造方法
JP2012504335A (ja) * 2008-09-30 2012-02-16 ノースロップ グラマン システムズ コーポレーション ガードリング構造およびその製造方法
WO2015145939A1 (fr) * 2014-03-25 2015-10-01 Toyota Jidosha Kabushiki Kaisha Dispositif semi-conducteur du type à grille isolée
WO2021089808A1 (fr) * 2019-11-08 2021-05-14 Abb Power Grids Switzerland Ag Transistor bipolaire à grille isolée

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