WO1999017352A1 - Procede et compositions permettant de metalliser des traversees et des interconnexions haute densite dans des dielectriques photodefinis - Google Patents

Procede et compositions permettant de metalliser des traversees et des interconnexions haute densite dans des dielectriques photodefinis Download PDF

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Publication number
WO1999017352A1
WO1999017352A1 PCT/US1998/020495 US9820495W WO9917352A1 WO 1999017352 A1 WO1999017352 A1 WO 1999017352A1 US 9820495 W US9820495 W US 9820495W WO 9917352 A1 WO9917352 A1 WO 9917352A1
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WIPO (PCT)
Prior art keywords
pattern
metal
additional
dielectric
dielectric layer
Prior art date
Application number
PCT/US1998/020495
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English (en)
Inventor
Paul H. Kydd
Original Assignee
Partnerships Limited, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Partnerships Limited, Inc. filed Critical Partnerships Limited, Inc.
Priority to AU95932/98A priority Critical patent/AU9593298A/en
Publication of WO1999017352A1 publication Critical patent/WO1999017352A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/5328—Conductive materials containing conductive organic materials or pastes, e.g. conductive adhesives, inks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • Manufacturing electronic devices such as printed circuit boards and semiconductor devices requires the placement of high density, patterned layers of conductive material on a substrate.
  • the method of placement must be suitable for high production rates and it must produce precise patterns. These requirements have become increasingly important with the recent development of surface mounting technology used to mount components on a substrate.
  • One method is to etch the patterns on copper-clad laminates using well known negative photo-resist procedures. This process is complex, slow, expensive, and produces hazardous solvents and other waste materials.
  • Another method is the process of applying a pattern of conductive ink or paste directly onto the surface of a non-conductive substrate and then curing it.
  • the curing operation of some conductive inks and pastes requires curing at elevated temperature above 450 °C before they becomes conductive.
  • Another type of ink includes epoxy resin, which is unsuitable for high performance circuits because of their poor electrical conductivity. They are also unsuitable for high speed, mass production because of long cure times.
  • Yet another known method uses a radiation curable ink containing particles of electrically conductive metal and organic resins curable with radiation. This ink cures rapidly, resulting in higher production rates.
  • the metal particles in it must have a certain predetermined shape for the ink to cure satisfactorily, and because the metal particles are not welded together, their electrical conductivity is still poor.
  • a conventional method of interconnecting the conductive layers of multi-layer printed circuit boards and of adding conductors to the surface of semiconductor devices consists of forming a via through the conductive layers, catalyzing the walls of the via, electroless plating the interior of the hole, masking the surface copper foil with a resist, exposing and developing the resist, and electroplating the walls of the hole with an electrically conductive material. The plating connects the exposed edges of the conductive layers and creates the circuit connections between them. Finally the resist is stripped and the unwanted copper foil is etched away. This operation can take considerable time.
  • the presently disclosed technology uses photo sensitive dielectric materials in combination with low temperature curable, metal forming compositions to produce the high density circuit patterns and filled vias in multi layered devices.
  • a photosensitive dielectric is applied to the surface of the circuit and exposed to the desired pattern of microvias, interconnect traces and conductor traces, which can be very fine.
  • the negative image is developed in the usual way by washing the unpolymerized, unexposed material away.
  • the composition of the present disclosure is applied by printing or doctor blading it into the microvias and interconnect traces.
  • the circuit is heat treated in an oven which consolidates the composition into pure metal conductors and completely polymerizes the photo imageable dielectric into an infusible, insoluble resin.
  • An additional layer of solder mask or potting compound can be applied to protect the finished circuit in the usual way or one or more additional layers of dielectric with microvias and traces can be placed on the previous existing layer.
  • PARMODTM mixtures contain a Reactive Organic Medium and metal flakes and/or metal powders.
  • the ROM consists of either a Metallo-Organic Decomposition (MOD) compound or an organic reagent which can form such a compound upon heating in the presence of the metal constituents.
  • the ingredients can be blended together with rheology modifying organic vehicles well known in the art, if necessary, to produce printing inks or pastes. These inks can be printed on a temperature sensitive substrate and cured to well-consolidated, well-bonded electrical conductors at a temperature low enough so that the substrate is not damaged. The curing process occurs in seconds at temperatures far below those used for conventional sintering of thick film inks and pastes.
  • the fast, low temperature curing capability of PARMODTM compositions, as well as their ready application by printing, makes it possible to use them to metallize high density interconnects and microvias using a very simple and low-cost process.
  • the process is particularly applicable to processes using photoimageable dielectrics in which the dielectric material remains as part of the finished product, rather than being stripped and discarded, as with conventional resists. Examples of such photoimageable products are Pyralin® from DuPont, Probelec® from Ciba Geigy and Probimide® from Olin Microelectronic Materials.
  • the process comprises forming a layer of a dielectric on an existing printed circuit or semiconductor device.
  • Microvias are formed in the dielectric in alignment with circuit traces and pads of the underlying printed circuit or semiconductor device.
  • Interconnect traces can also be formed in either by printing PJARMODTM traces directly on the surface of the photodielectric or by filling photo-defined trenches in a subsequently applied layer of the dielectric between the microvias underlying circuit traces and pads for mounting circuit components by soldering.
  • PJARMODTM is then applied to fill the microvias and interconnect traces.
  • the PARMODTM can be applied by any suitable method, including screening, printing, stenciling, and doctor blading or using a squeegee.
  • the PARMODTM is cured with heat, forming a solid metal conductor in the microvias and interconnect traces.
  • a next layer of dielectric can be formed over the existing dielectric layer.
  • Microvias and interconnect traces are formed in this next dielectric layer in alignment with microvias and interconnect traces in the underlying dielectric layer.
  • the microvias and interconnect traces are filled with PARMODTM and the PJARMODTM is cured.
  • the steps of forming a next dielectric layer with microvias and interconnect traces; filling the microvias and interconnect traces with PARMODTM; and curing the PARMODTM, can be repeated indefinitely as necessary to produce complex, multi- layered circuit boards or semiconductor devices.
  • Figure 1 is an illustration of an electronic device produced by the method of this invention having metallized microvias and printed circuit traces.
  • Figure 2 is an illustration of an electronic device produced by the method of this invention having metallized microvias and interconnects.
  • FIG. 3 is an illustration of a multi-layered device produced by the method of this invention. Detailed Description of the Invention
  • compositions useful for filling the vias and forming the traces are comprised of a metal mixture and a Reactive Organic Medium (ROM). These compositions can be applied to thermally stable substrates and cured to well- consolidated, pure metal vias, interconnects and circuit traces by heat treatment.
  • the compositions exhibit a critical temperature above which they undergo a transformation to well-consolidated electrical conductors with a resistivity only two to four times the bulk resistivity of the metal in question.
  • the electrical conductivity is equal to that obtained by conventional high temperature metal powder sintering in conventional thick film compositions on ceramic substrates.
  • this consolidation process takes place at temperatures 400 to 500 degrees Celsius lower than with compounds conventionally used in thick film technology, and in times which are an order of magnitude shorter than are required for sintering.
  • Suitable metals include copper, silver, gold, zinc, cadmium, palladium, iridium, ruthenium, osmium, rhodium, platinum, iron, cobalt, nickel, indium, tin, antimony, lead, bismuth and mixtures thereof.
  • Examples of typical proportions of PJARMODTM mixtures containing an organic acid as the ROM and both metal flakes and colloidal metal powder are illustrated in Table 1 as follows:
  • the metal mixture contains metal flake and colloidal or semi-colloidal metal powder where the total of flake plus powder is preferred to be 60-85%) of the total mixture, and the powder is preferred to be 30-50% of the total metal. Larger amounts of organic vehicle may be added to reduce viscosity for certain applications.
  • the metal flakes have a major dimension between 2 to 10 micrometers, preferably about 5 micrometers, and a thickness of less than 1 micrometer. They can be produced by techniques well known in the art by milling the corresponding metal powder with a lubricant, which is frequently a fatty acid or fatty acid soap. The starting powders are usually produced by chemical precipitation to obtain the desired particle size and degree of purity. The flakes are sold for electronic applications as constituents of thick film inks and silver-loaded conductive epoxies.
  • the flakes perform several functions. They form a skeleton structure in the printed image which holds the other ingredients together and prevents loss of resolution when the mixture is heated to cure it.
  • the flakes naturally assume a lamellar structure like a stone wall which provides electrical conductivity in the direction parallel to the surface of the substrate and provides a framework to lessen the amount of metal transport necessary to achieve the well-consolidated pure metal conductors which are the objective of this invention. They also provide low surface energy, flat surfaces to which the other constituents of the composition can bond.
  • the other metallic powder mixture constituent of the present invention are preferably colloidal or semi-colloidal powders with individual particle diameters below about 100 nanometers, preferably less than about 50 nanometers.
  • the colloidal or semi-colloidal powder is preferably present in about 40% by weight of the total weight of the metal powder mixture.
  • a primary function of these powders is to lower the temperature at which the compositions will consolidate to nearly solid pure metal conductors.
  • the presence of fine metal powder has been found to be helpful in advancing this low temperature process with silver and essential to the consolidation of copper mixtures. It is important that they be present as individual particles. Metal particles this small have a strong tendency to agglomerate into aggregates with an open skeletal structure.
  • Colloidal silver particles with a nominal diameter of 20 nanometers were shown to have an excellent state of dispersion and have been used in silver compositions and lowered the critical consolidation temperature from 300 to 260 degrees C.
  • Suitable surfactants include carboxylic acids and metal soaps of carboxylic acids. This favors chemical precipitation as a means of producing the powders, since they can be exposed to an environment which promotes stabilization from formation to final consolidation.
  • the Reactive Organic Medium provides the environment in which the metal mixture is bonded together to form well-consolidated conductors.
  • Many classes of organic compounds can function as the ROM.
  • the common characteristic which they share and which renders them effective is that they have, or can form, a bond to the metal via a hetero-atom.
  • the hetero-atoms can be oxygen, nitrogen, sulfur, phosphorous, arsenic, selenium or other nonmetallic elements, preferably oxygen, nitrogen or sulfur.
  • This bond is weaker than the bonds holding the organic moiety together, and can be thermally broken to deposit the metal. In most cases the reaction is reversible, so that the acid or other organic residue can react with metal to reform the metallo-organic compound, as shown schematically below:
  • R is a reactive organic compound and M is the metal.
  • M is the metal.
  • the effect is to consume the small particles and weld together the big ones to create macroscopic circuit conductors of pure metal.
  • some other active organic reagent which will produce an easily decomposed metallo-organic compound from either the oxide or the metal could be used.
  • An example would be the use of sulfur compounds to make mercaptides or nitrogen ligands to produce decomposable complexes.
  • Examples of useful compounds are soaps of carboxylic acids, in which the hetero-atom is oxygen; amino compounds, in which the hetero-atom is nitrogen; and mercapto compounds, in which the hetero-atom is sulfur.
  • ROM constituents are the carboxylic acids and the corresponding metallic soaps of neodecanoic acid and 2-ethyl hexanoic acid with silver and copper, such as. silver neodecanoate illustrated by the formula:
  • Gold amine 2-ethyl hexanoate is an example of a nitrogen compound.
  • Gold t-dodecyl mercaptide is an example of a sulfur compound:
  • Ri + R 2 + R3 Ci 1H23
  • These ROM compositions can be made by methods well known in the art. All of the above compounds are capable of decomposition to the respective metals at relatively low temperatures.
  • the decomposition temperature is between 200 and 250°C .
  • the corresponding copper compounds it is between 300 and 315 C.
  • Gold sulfides decompose at very low temperatures in the neighborhood of 150°C .
  • Gold amine octoate decomposes between 300 and 500°C .
  • the copper and silver compounds can be reformed from the corresponding acids at the same temperature, so the reaction is reversible, as mentioned above.
  • Alpha-terpineol has been used to reduce the viscosity of copper and silver compositions to facilitate screen printing.
  • Alpha-terpineol also participates in the consolidation reaction by virtue of the acid character of the OH group bonded to an unsaturated ring.
  • the following steps are used to utilize PARMODTM compositions for metallizing high density microvias and interconnects:
  • An existing printed circuit or semiconductor device is coated with a photoimageable dielectric and then prebaked to drive off solvent and produce a dry film.
  • the desired pattern of microvias is photoimaged on the surface in alignment with the underlying pads or traces of the printed circuit or semiconductor device to which connections are to be made.
  • the image of the pattern is developed, for example, with a solvent or alkaline stripping agent, to remove the dielectric in the microvias.
  • PARMODTM mixture is applied into the microvias.
  • the PARMODTM can just fill the microvias or it can be extended to connect some or all of them with printed circuit traces, by one of several methods.
  • a preferred method for applying the PARMODTM is simply to spread the PARMODTM with a doctor blade to fill the microvias and leave the surface clean.
  • the PARMODTM material can also be applied by any acceptable printing method, for example, screening, stenciling, gravure printing, impression printing, offset printing, ink jet printing or electrostatic printing.
  • the printed image may just fill the microvias or it can be extended to connect some or all of them with printed circuit traces. Electrostatic printing is a preferred method because a high resolution PARMODTM image can be transferred to the uneven surface containing open microvias.
  • the circuit is heated in an appropriate atmosphere to a temperature required to cure the photoimageable dielectric.
  • a temperature required to cure the photoimageable dielectric For polyimide materials this temperature is 350 °C for one hour. This is more than enough to cure any PARMOD TM composition including, specifically, copper
  • the normal cure cycle is 150 °C for one hour. This would have to be increased to roughly 200 °C to cure silver PARMODTM, but the time could be shortened correspondingly to six minutes or less.At this point, the circuit has an added layer of dielectric with metallized microvias leading to the surface and, optionally, some printed circuit traces connecting them or connecting to pads defined by the printed image, as shown in Figure 1.
  • the fine interconnects are metallized with PARMODTM and cured as in 4) and 5) above to provide a plane of very high density circuitry, as illustrated in figure 2.
  • the process can then be repeated with layers of microvias, interconnects and circuitry, and so on, to build up a multi layered, high density structure of whatever complexity is needed to redistribute the I/O from increasingly large and fine pitch semiconductors, as illustrated in figure 3.
  • the PARMODTM is not cured after each layer is filled.
  • the PARMODTM is applied and heat cured after a layer of microvias and a layer of interconnects have been formed in the dielectric. Thereby metallizing the structure, as shown in figure 2, in one operation; decreasing the number of curing steps required and the number of curing ovens required.
  • the advantages of using PARMODTM in this application include: ease of applicability; the ability to make circuit connections simultaneously with metallizing microvias; the production of high quality, well-consolidated, well-bonded metal traces; the fact that the metallization process adds almost nothing in processing complexity and time to the application of the photodefmed dielectrics themselves. This is in sharp contrast to the conventional catalyze, electroless plate, electroplate, etch, metallization process now used.
  • a silver PARMODTM screen ink was prepared by mixing together 12.0 grams of Degussa silver flake, 3.0 grams of silver neodecanoate, and 1.35 grams of neodecanoic acid using a spatula. The resulting mixture was then milled for 30 minutes on a roll mill to give a homogeneous paste. Damascene type silver metallization using the silver PARMODTM ink was used to create a fan-out pattern of 100 micron lines with contacts to a copper surface. Ciba Specialty Chemicals' Probelec ® epoxy-based photoimageable dielectric was used to create the image to be metallized. A Probelec ® film was formed on the copper surface of a copper clad FR-4 board.
  • the film was heat treated to remove solvents in accordance with the manufacturers instructions.
  • the film was then photoimaged using a mask to create a line of vias on the copper surface and developed to remove the material from the imaged vias.
  • the dielectric film covered the copper surface except in the imaged areas where the material was removed.
  • jAnother film of Probelec ® was formed on this imaged surface and processed as above to create a fan-out pattern of 100 micron lines leading from an array of 25 100 micron lines separated by 50 micron spaces to the previously imaged vias.
  • the image was complete with the lower surface of the vias being the copper substrate and the lower surface of the lines leading from the vias being the first layer of Probelec ® .
  • the PJARMODTM silver screen ink was then applied to the Probelec ® imaged circuit.
  • the ink was squeegeed across the surface of the circuit, filling in the conductive lines and vias with the ink. Excess ink on the surface was removed with wiping, and the circuit was thermally treated at 260°C for 255 seconds. The thermal treatment cured the silver ink giving pure silver and simultaneously cured the dielectric. remaining traces of silver on the surface were removed with abrasion using 1200 grit sandpaper.
  • the resulting silver metallized image contained conductive, electrically isolated 100 micron lines with connections to the copper substrate through the vias which were separated by 50 microns of Probelec ® dielectric at the point of closest approach.
  • a copper PARMOD ink was prepared by mixing 47 grams of copper flake, 29 grams of nanometer sized spherical copper powder mixed with neodecanoic acid (-77 wt% metal) and 15 grams of neodecanoic acid in a glove box. This premix was than further mixed on a 2-roll mill for 30 minutes in air. The gap setting on the mill was 0.006" - 0.008". After milling, the ink was removed from the mill and stored in a plastic syringe from which it also was dispensed.
  • the copper PARMOD mk was applied to microvia holes (125 microns diameter, 5 microns deep) which had been created using DuPont Pyralin ® , a photoimageable polyimide deposited onto a copper foil.
  • the holes were filled with ink using a squeegee. No adhesive was used in the holes prior to filling with the copper
  • a copper PARMOD ink was prepared by mixing 30 grams of copper flake, 27 grams of 3 micron diameter spherical copper powder, and 25 grams nanometer sized spherical copper powder mixed with neodecanoic acid ( ⁇ 77 wt% metal) and 9 grams of neodecanoic acid in a glove box. This premix was than further mixed on a 2- roll mill for 30 minutes in air. The gap setting on the mill was 0.006" - 0.008". After milling, the ink was removed from the mill and stored in a plastic syringe from which it also was dispensed.
  • the copper PARMOD ink was applied to microvia holes (128 microns in diameter, 64 microns deep) which had been "drilled" into a double sided copper/Kapton laminate using a laser.
  • TM holes prior to filling with the copper PARMOD ink.
  • the heat treating conditions for both passes was 245°C for 10 minutes in a N 2 -H 2 O-H 2 gas mix.
  • the resulting filled holes were bright copper and conductive.
  • a copper PARMOD ink was prepared by mixing 49 grams of copper flake, 31 grams of nanometer sized spherical copper powder mixed with neodecanoic acid (-77 wt% metal) and 11 grams of neodecanoic acid in a glove box. This premix was than further mixed on a 2-roll mill for 30 minutes in air. The gap setting on the mill was 0.006" - 0.008". After milling, the ink was removed from the mill and stored in a plastic syringe from which is also was dispensed.
  • the copper PARMOD ink was applied to a circuit fan pattern recited in example 1 which had been created using DuPont Pyralin ® photoimageable polyimide deposited onto a copper foil.
  • the fan pattern was filled with ink using a squeegee.
  • TM adhesive was used in the holes prior to filling with the copper PARMOD ink.
  • the copper foil with the filled fan pattern was heat treated at 375°C for 90 seconds in a N -H 2 O-H2 gas mix.
  • the resulting filled trenches were bright copper and conductive.
  • the copper metal was firmly adherent to the polyimide as demonstrated by tape testing.

Abstract

La présente concerne un procédé permettant de métalliser des micro-traversées et des interconnexion haute densité dans des diélectriques photodéfinis à l'aide de nouveaux composés organo-métalliques à durcissement rapide, à basse température. Les matières sont appliquées sur la photoimage développée par un procédé d'impression quelconque adapté et sont durcies thermiquement en conducteurs de métal pur bien consolidés au même moment et dans les mêmes conditions que le durcissage et la réticulation des diélectriques en résines infusibles, insolubles.
PCT/US1998/020495 1997-09-30 1998-09-30 Procede et compositions permettant de metalliser des traversees et des interconnexions haute densite dans des dielectriques photodefinis WO1999017352A1 (fr)

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Application Number Priority Date Filing Date Title
AU95932/98A AU9593298A (en) 1997-09-30 1998-09-30 Method and compositions for metallizing microvias and high density interconnectsin photodefined dielectrics

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Application Number Priority Date Filing Date Title
US6052197P 1997-09-30 1997-09-30
US60/060,521 1997-09-30

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WO1999017352A1 true WO1999017352A1 (fr) 1999-04-08

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Cited By (7)

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WO2001033649A1 (fr) 1999-11-02 2001-05-10 Koninklijke Philips Electronics N.V. Procede permettant de produire des interconnexions verticales entre des dispositifs micro-electroniques a film mince, et produits comprenant ces interconnexions verticales
GB2362031B (en) * 1999-11-04 2002-11-27 Nippon Electric Co Flip-chip type semiconductor device with stress-absorbing layer made of thermosetting resin, and its manufacturing method
EP1289013A1 (fr) * 2001-08-15 2003-03-05 Datamars SA Procédé pour appliquer une puce semiconductrice sur un substrat et assemblage ainsi obtneu
GB2385466A (en) * 1999-11-04 2003-08-20 Nec Corp Flip-chip device having stress absorbing layers and contacts
EP1622435A1 (fr) * 2004-07-28 2006-02-01 ATOTECH Deutschland GmbH Méthode de fabrication d'un dispositif par des techniques d'écriture directe
US7141185B2 (en) 2003-01-29 2006-11-28 Parelec, Inc. High conductivity inks with low minimum curing temperatures
US7211205B2 (en) 2003-01-29 2007-05-01 Parelec, Inc. High conductivity inks with improved adhesion

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US5728626A (en) * 1993-07-26 1998-03-17 At&T Global Information Solutions Company Spin-on conductor process for integrated circuits

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2001033649A1 (fr) 1999-11-02 2001-05-10 Koninklijke Philips Electronics N.V. Procede permettant de produire des interconnexions verticales entre des dispositifs micro-electroniques a film mince, et produits comprenant ces interconnexions verticales
US6635406B1 (en) 1999-11-02 2003-10-21 Koninklijke Philips Electronics N.V. Method of producing vertical interconnects between thin film microelectronic devices and products comprising such vertical interconnects
GB2362031B (en) * 1999-11-04 2002-11-27 Nippon Electric Co Flip-chip type semiconductor device with stress-absorbing layer made of thermosetting resin, and its manufacturing method
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