WO1991014015A1 - Procede et materiau de formation de circuits multicouches selon une technique d'addition - Google Patents

Procede et materiau de formation de circuits multicouches selon une technique d'addition Download PDF

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Publication number
WO1991014015A1
WO1991014015A1 PCT/US1991/000875 US9100875W WO9114015A1 WO 1991014015 A1 WO1991014015 A1 WO 1991014015A1 US 9100875 W US9100875 W US 9100875W WO 9114015 A1 WO9114015 A1 WO 9114015A1
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WO
WIPO (PCT)
Prior art keywords
dielectric
conductive
effective amount
thermosetting
circuit
Prior art date
Application number
PCT/US1991/000875
Other languages
English (en)
Inventor
Keith O. Wilbourn
Thomas A. Armer
Jeffrey S. Braden
Kin-Shiung Chang
Michael A. Raftery
Original Assignee
Olin Corporation
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Filing date
Publication date
Application filed by Olin Corporation filed Critical Olin Corporation
Publication of WO1991014015A1 publication Critical patent/WO1991014015A1/fr

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4664—Adding a circuit layer by thick film methods, e.g. printing techniques or by other techniques for making conductive patterns by using pastes, inks or powders
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
    • H01L21/481—Insulating layers on insulating parts, with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49894—Materials of the insulating layers or coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4685—Manufacturing of cross-over conductors

Definitions

  • This invention relates to printed circuits having a plurality of interconnected conductive layers separated by a dielectric. More particularly, the invention relates to a process for forming flexible circuits having a high density of signal plane circuit traces selectively electrically interconnected to ground and/or power planes.
  • Electronic circuits contain a plurality of conductive circuit traces supported by a dielectric substrate.
  • a printed circuit board or other rigid type of circuit assembly usually has a glass-filled epoxy substrate on the order of about .25mm (10 mils) thick.
  • Flexible circuits are generally supported by a thin, on the order of about .051mm (2 mils) thick, polyimide substrate. Both types of circuitry may be formed by the same general procedure.
  • Conventional circuit assembly processes employ photolithography.
  • a layer of a conductive metal, such as copper foil, is bonded to the dielectric substrate by lamination.
  • the conductive layer is then patterned into circuit traces. Patterning is usually a subtractive process entailing resist patterning followed by etching.
  • the conductive surface of the laminate is coated with a photoresist.
  • the photoresist is then exposed by a radiation appropriate to the resist type. Exposure takes place through a photomask so that the resist is developed in the desired circuit design. After resist patterning, a suitable solvent removes the unexposed resist. A suitable acid etch then removes the conductive layers from the exposed regions. After etching, the remaining resist is removed resulting in a desired pattern of circuit traces.
  • the circuit traces are formed by removing metal from the circuit board. While dissolved metal may be recovered by an electrolytic process, recovery is time consuming and expensive.
  • the solvents used to remove resist and the dissolved resists are based on organic chemicals which may pose a hazard both to the environment and to people exposed to them.
  • the vias are conventionally formed by a subtractive process similar to that used to pattern the circuit traces.
  • a layer of a photosensitive dielectric is deposited over the circuit traces.
  • a mask containing the desired pattern of vias is placed over the resist. The resist is exposed and only the sites of the vias remain soluble. After dissolution, a second conductive layer is laminated to the resist.
  • a screenable dielectric having improved flow and thermal characteristics. It is another object of the invention to provide a process to manufacture multi-metal layer circuits by an additive process. It is a feature of the invention that dielectric layers and conductive layers are applied by screen printing or by the direct writing. It is another feature of the invention that the vias are formed directly in the dielectric layer as applied. It is an advantage of the additive process that precise alignment is obtained. Yet another advantage of the invention is the flow characteristics of the dielectric are carefully controlled minimizing via collapse. It is a further advantage that no subtractive removal of material is required. It is an advantage of the invention that the amount of material dissolved which must be reclaimed or disposed is minimized. It is a further advantage that the requirement for organic solvents is minimized reducing the environmental hazard.
  • a screenable dielectric and an additive process to electrically interconnect selected traces of a circuit containing a plurality of traces has a composition by weight of from about 35 to about 60% thermosetting polyimide, from about 35 to about 60% of a solvent, an effective amount of a flow enhancer and an effective amount of a viscosity increasing agent.
  • the plurality of traces are selectively insulated by coating -3-
  • the photolithographic process is subtractive. Metal loss and disposal of solvents is also problem.
  • the multitude of photolithographic steps makes alignment between the plurality of layers difficult. Alignment is not as severe a problem with rigid boards. Individual traces may have a width of up to about .38mm (15 mils). However, on flexible circuits with circuit trace widths down to about .051mm (2 mils), mask alignment is difficult.
  • U.S. Patent No. 3,904,783 to Nara discloses printing a circuit pattern on an insulating substrate with a synthetic resin ink containing 1 to 10 percent by weight of a fine metal powder by silk screening. Conductivity is improved by electroless plating on the screened metal powder.
  • Another method disclosed in the Nara patent uses an organometallic. Certain metal salts of organic acids liberate metal ions when irradiated with ultra-violet rays.
  • the metal salt is applied to the substrate as a solution. Irradiation through a mask containing the desired circuit pattern forms conductive lines of the metallic salt.
  • the salt is chemically converted to base metal and plated to form circuit patterns.
  • the unexposed organometallic is removed by dissolution. with the dielectric. A portion of those traces which are to be electrically interconnected is left conductive. Each conductive portion is then electrically connected either to another conductive portion or to a ground or power plane.
  • Figures 1A-1C illustrate in cross-sectional representation a sequence of steps to electrically interconnect circuit traces by an additive process in accordance with a first embodiment of the invention.
  • Figures 2A-2C illustrate in cross-sectional representation a sequence of steps to electrically interconnect signal plane circuit traces to ground and power planes in accordance with an embodiment of the invention.
  • Figure 3 illustrates in top planar view a signal plane containing circuit traces and plurality of annuli as known in the prior art.
  • Figure 4 illustrates in top planar view the additive process of the invention as applied to the signal plane of the prior art.
  • Figure 5 illustrates in top planar view an improved annulus in accordance with an embodiment of the invention.
  • Figures 6A-6C illustrate in cross-sectional representation an additive process - to electrically interconnect select traces by direct writing in accordance with an embodiment of the invention.
  • Figure 7 illustrates in top planar view the interconnection of selected traces by direct writing in accordance with the invention.
  • FIG. 1 illustrates in cross-sectional representation a method of forming a multi-metal layer printed circuit in accordance with the invention.
  • the process employs a conventional printed circuit 10 as known from the art.
  • the printed circuit 10 comprises a dielectric substrate 12, which may be a rigid board such as FR-4 (a flame retardant, glass-filled epoxy) or a flexible dielectric such as polyimide.
  • a plurality of conductive circuit traces 14 which may have been patterned by subtractive photolithography are supported by the substrate 12.
  • a screenable dielectric 16 is selectively applied over the circuit traces 14 and dielectric substrate 12 as illustrated in Figure IB. Certain circuit traces 14' are coated with the screenable dielectric 16 and insulated. Portions of certain circuit traces 14'' are not coated and remain conductive.
  • the screenable dielectric is chemically non-reactive to both the conductive circuit traces 14 and the substrate 12.
  • the conductive circuit traces 14 are usually copper or a copper based alloy.
  • the screenable dielectric should be resistant to copper catalyzed degradation.
  • the screenable dielectric should further be environmentally stable and non-hydroscopic so the circuit does not break down upon exposure to sunlight or moisture.
  • Other requirements of the screenable dielectric include a coefficient of thermal expansion close to that of the dielectric substrate 12. This requirement is most stringent in the case of a flexible dielectric substrate 12. A severe coefficient of thermal expansion mismatch may lead to flexure of the circuit during heating and cooling. A rigid substrate may not flex. However, the mismatch may generate stresses at the interface of the screenable dielectric and the substrate and cause delamination of the circuit traces 14.
  • the screenable dielectric should also exhibit high temperature stability. During wire bonding or tape automated bonding to a semiconductor device, the temperature of the circuit traces is elevated to about 150°C.
  • the circuit may be subjected to harsh operating environments, such as under the hood of an automobile or outer space.
  • thermosetting polyimide is preferred.
  • the screenable dielectrics of the invention comprise a mixture of a thermosetting polyimide, a solvent, a flow enhancer and a viscosity enhancer. In the preferred embodiments, a co-solvent is included.
  • the thermosetting polyimide is preferably a preimidized polyimide. These compounds are preferred over polyamic acids since they do not eliminate water during curing. It has been found the elimination of water causes the polyamic acid to shrink leading to via collapse.
  • a most preferred preimidized polyimide is polyisoimide.
  • a thermosetting polyisoimide is preferred due to its thermal stability, chemical non-reactivity and good adhesion to other polyimides and metals. For flexible circuits, the coefficient of thermal expansion matches that of the polyimide substrate 12 preventing thermally induced flexure.
  • a thermosetting polyimide is manufactured by National Starch & Chemical Corporation (Bridgewater, New Jersey, USA) under the trademark "THERMIDTM" .
  • the second component of the screenable dielectric is a solvent capable of dissolving the polyimide for screen printing. A most preferred solvent is butyrolactone for screen printing.
  • a flow enhancer is added in a quantity effective to enhance the flow of the screenable dielectric through the screen and to minimize the formation of bubbles in the deposited dielectric.
  • One preferred flow enhancer is siloxane (R ⁇ Si-O-Si ⁇ R) .
  • An effective amount of flow enhancer will permit bubbles formed in the screened dielectric to escape without increasing significantly the flow. Too much flow enhancer will lead to a loss of feature integrity. Too little will result in entrapped pockets of gas in the cured dielectric.
  • the fourth component of the the screenable dielectric is a viscosity enhancer.
  • the viscosity enhancer increases the thixotropic index of the screenable dielectric. When subjected to a shear stress, such as during screening, the dielectric flows readily. Unlike conventional filled dielectrics, little clogging of the screens is detected. Once the shear stress is removed, the viscosity increases rapidly so that the dielectric does not flow much after deposition. An effective amount of viscosity enhancer allows the dielectric to flow through the screen and then minimize flow on the substrate. Too much viscosity enhancer will result in a dielectric which can not pass through the screen. Too little will result in a loss of feature integrity on the screen.
  • One evaluation of the viscosity index of a screened substance is to compare feature dimensions on the screen to feature dimensions of the substance on a substrate. While conventional photoresists and inks have a feature reduction approaching 100% on small dimension vias, the dielectric of the invention exhibited only about a 35% feature reduction.
  • One suitable viscosity enhancer is a fumed silica. The particles are quite small, preferably less than about 5 microns in diameter. Preferably a hydrophobic fumed silica is selected to minimize water retention in the dielectric.
  • a co-solvent is preferred.
  • the co-solvent is any solvent which dissolves the polymer more readily than the solvent. Suitable co-solvents when the solvent is butyrolactone include dimethylsulfoxide (DMSO) and tetragly e.
  • the ratio of components is selected to produce a viscous liquid having a high thixotropic index.
  • the liquid is screen printable using conventional screen printing equipment.
  • the post screening viscosity increases rapidly to a value sufficiently high to minimize bleed out when deposited on circuit 10.
  • the viscosity of the screenable dielectric is from about 10,000 to about 100,000 centipoise. More preferably, the viscosity of the screenable dielectric is from about 30,000 to 50,000 centipoise.
  • the screenable dielectric has a composition by weight of: from about 35 to about 60% thermosetting polyimide from about 35 to about 60% solvent an effective amount of flow enhancer an effective amount of viscosity enhancer.
  • the composition of the screenable dielectric is: from about 40 to about 50% thermosetting polyimide from about 40 to about 50% solvent an effective amount up about to 1% flow enhancer from about 3 to about 5% viscosity enhancer from about 1 to about 3% co-solvent
  • a most preferred screenable dielectric has the composition by weight: from about 40 to about 50% polyisoimide from about 40 to about 50% butyrolactone an effective amount up about to 1% siloxane from about 3 to about 5% hydrophobic fumed silica from about 1 to about 3% dimethylsulfoxide
  • An advantage of the screenable dielectric is the flow rate is highly controlled due to a tightly balanced mixture of flow enhancers and viscosity increasers. Without the tightly balanced thixotropic index of the invention, features less than about .25mm (10 mils) with .25mm (10 mil) spacings are not obtainable by screening. With the balanced dielectric, features as small as .076mm (3 mils) have been printed by screening and by direct writing. The dielectric should also be amenable to application by stenciling (contact printing) .
  • Vias 18 are formed over those traces 14' ' to be electrically interconnected to either other circuit traces or to a ground or power plane.
  • the circuit traces 14 in a flexible circuit are on the order of about .051mm (2 mils) wide with .051mm (2 mil) spacing. Vias on the order of .051mm to .076mm (2 to 3 mils) in diameter are required. At these dimensions, vias formed from conventional dielectrics are prone to collapse after screening and are not suitable.
  • the features are readily obtained with the thermosetting screenable dielectric of the invention. After screening, the dielectric is cured by heating to a temperature of from about 230°C to about 350°C and more preferably in the range of from about 280°C to about 300°C.
  • the cure time varies dependent upon the cure time. At 230°C, approximately four hours are required. At 320°C, the cure time is about 30 minutes. During the cure, the dimensions of the vias formed in the dielectric of the invention change by less than about 3 percent. After curing, the thermoset fluorinated polyimide is stable to intermittent temperatures of over 300°C and continuous operation at temperatures over 200°C.
  • the multi-layer circuit is completed by electrically interconnecting conductive portions of the circuit traces 14'' with a conductive paste 20 as illustrated in Fig 1-C.
  • the conductive paste is applied over the entire surface 22 of the screenable dielectric 16. Screen printing or other techniques which are capable of applying a layer of paste having a uniform thickness may be used. A sufficient amount of paste is used so vias 18 are filled.
  • the conductive paste makes contact with the conductive circuit traces 14''.
  • the conductive paste 20 may be any commercially available paste.
  • One preferred paste comprises a fluorinated polyimide in a butyrolactone vehicle.
  • a fine metal powder is dispersed through the paste to provide electrical conductivity.
  • a preferred metal is silver.
  • the paste is mixed so that after curing it has a composition of about 80 percent by weight silver and 20 percent by weight polyimide.
  • This conductive paste is marketed under the trademark 99R0884 by Olin Hunt Conductive Materials (Ontario, CA., USA).
  • the paste may be electroplated after curing to form a surface 24 which is solderable to another component, such as a heat sink or leadframe.
  • the deposition of a metal overlayer 24 also improves conductivity. All fine features are formed in the thermosetting dielectric. High resolution is not required from the conductive pastes.
  • surface 24 of the conductive paste may be coated a barrier layer 26.
  • the barrier layer 26 may be a polymer or an oxidation resistant metal. The layer prevents moisture, air and ionic contamination from contacting the conductive layer 20. The contaminants may react with the conductive layer and affect electrical properties.
  • a most preferred barrier layer is a polyimide.
  • Figure 2 illustrates in cross sectional representation, an additive process to manufacture a multi-layer circuit in accordance with a second embodiment of the invention.
  • Figure 2A shows a conventional circuit following deposition of screenable dielectric 16.
  • the circuit includes a dielectric substrate 12, insulated circuit traces 14' and conductive circuit traces 14'' and 14'''.
  • a first class of circuit traces 14' is insulated by the screenable dielectric and forms the signal plane for the assembled circuit. These circuit traces transmit electrical signals between an electronic device and external circuitry.
  • a second class of conductive circuit traces 14'' forms ground circuits. These circuit traces provide the electronic device with a ground.
  • a third class of conductive circuit traces 14''' provides a source of power to the electronic device. Power and ground planes which are to be electrically interconnected to the conductive leads 14'', 14''' are formed from the conductive paste.
  • FIG. 2B shows in cross sectional representation the circuit of Figure 2A with the addition of a first conductive portion constituting a ground plane 28 and a second conductive portion constituting a power plane 30. Since, in accordance with the invention, the vias 18 were formed in the thermosetting screenable dielectric 16, very fine features are obtained.
  • the gap 32 which separates the ground and power planes does not require precise placement. The 10 mil resolution obtainable with a filled conductive ink is satisfactory for locating gap 32.
  • the gap 32 is preferably filled with a dielectric material 34 such as a polymer as illustrated in Figure 2C.
  • a dielectric material 34 such as a polymer as illustrated in Figure 2C.
  • the gap 32 if left unfilled may trap moisture or other contaminants and form an electrical short circuit between ground plane 28 and signal plane 30.
  • One preferred dielectric for coating 34 is a polyimide.
  • the process of the invention is particularly suited for manufacturing circuits for a pin grid array type electronic package.
  • a pin grid array circuit a generally rectangular array of terminal pins is electrically interconnected to an electronic device by conductive circuit traces. The terminal pins are then inserted into external circuitry such as a printed circuit board.
  • Figure 3 illustrates a conventional circuit 10 for a pin grid array circuit.
  • a molded plastic pin grid array type package incorporating a circuit 10 is illustrated in United States Patent No. 4,816,426 to Bridges et al.
  • the circuit 10 is supported by a dielectric substrate 12.
  • a first end 35 of circuit traces 14 terminates at a generally rectangular aperture 36.
  • the electronic device (not shown) is centered within the rectangular aperture 36 and electrically interconnected to the first ends 35 of circuit traces 14 by wire bonds, tape automotive bonding means or other forms of electrical interconnection.
  • the opposing end 37 of circuit traces 14 terminates at a conductive annulus 38.
  • the conductive annulus 38 is formed by photolithographic techniques when the circuit traces 14 are formed.
  • the conductive annulus is formed from the conductive metal layer which forms the circuit traces.
  • a circular aperture 40 is circumscribed by the conductive annulus 38.
  • the head of a terminal pin (not shown) passes through each circular aperture 40 and is electrically interconnected to annulus 38.
  • Electrical interconnection may be by mechanical contact, soldering, or other techniques such as brazing or riveting. Soldering is preferred for low cost reliable electrical interconnections.
  • a low melting temperature solder such as a lead-tin alloy is mixed in powder form with an appropriate vehicle such as terpineol to form a solder paste. The paste is applied to each conductive annulus by a process such as screen printing. Any suitable solder may be employed.
  • the melting temperature of the solder should be below the temperature at which thermal degradation of the dielectric substrate is encountered. Generally the solder will be selected to melt at a temperature below about 300°C.
  • Lead-tin alloys such as 60% tin / 40% lead are exemplary.
  • the terminal pins are inserted through circular apertures 40 and supported by a fixture. The assembly is passed through a furnace in an appropriate atmosphere. The solder melts and bonds the terminal pins to the circuit 10.
  • Figure 4 illustrates in top planar view a portion of the circuit 10 illustrating a problem with conventional annuli.
  • the screenable dielectric 16 When the screenable dielectric 16 is selectively applied over the circuit traces 14 (shown in phantom when coated with the screenable dielectric and as solid lines when visible through vias 18) surface tension causes the dielectric to creep along circuit traces 14 and impinge the annuli 38.
  • the screenable dielectric interferes with soldering.
  • the solder does not adhere to the screenable dielectric.
  • a gap in the solder forms and the integrity of the solder joint is impacted.
  • a teardrop shaped annulus 38' is formed during photolithography.
  • the teardrop 42 is aligned so the circuit trace 14 is expanded prior to reaching the annulus 38'.
  • FIG. 6 illustrates in top planar view such a circuit. It is desired to interconnect circuit traces labeled 14 a and also the traces labeled 14 . The circuits 14 a and 14 are to remain electrically isolated. The circuits are spaced close together. The separation between vias 44 exposing the circuit traces 14 and vias 46 exposing the circuit traces 14 is less than about .15mm (6 mils).
  • a direct writing process makes the vias 44, 46 electrically conductive.
  • the process can also be used to interconnect the vias by conductive lines 48.
  • the process of forming the conductive vias and conductive lines by direct writing is illustrated in cross sectional representation in Figure 7.
  • a circuit 10 comprising a dielectric substrate 12 and conductive circuit traces 14 is coated with a screenable dielectric 16.
  • Vias 46 are formed in the screenable dielectric 16 to form conductive portions of the circuit traces 14 at appropriate locations.
  • the vias 46 are made electrically conductive and interconnected by conductive lines 48.
  • Conductive lines are formed by a process such as additive direct writing.
  • additive direct writing a fluid material is extruded from a pen tip onto a substrate resulting in an image.
  • the features are produced directly from computer generated data without the need for hard tooling.
  • .031mm (1.2 mil) lines having .006mm (0.25 mil) spacings have been achieved.
  • Using a precision X-Y table resolution up to .003mm (.1 mil) is repeatability obtained.
  • a direct writing system is available from Micropen, Inc. (Pittsford, New York, USA).
  • Organometallics are organic salts comprised of an organic acid and a metal ion.
  • One group of organometallics employ glutamic acid. Silver glutamate, copper glutamate and palladium glutamate were formed.
  • organometallic salts are preferred for highest conductivity.
  • One particularly favored organometallic salt is gold mercaptide.
  • the salts decompose in the presence of heat or other energy source.
  • One commercial source of organometallic gels is Engelhard Corporation (Newark, New Jersey, USA) .
  • Organometallics have been used to write circuit lines on ceramic substrates. The process has not been used with polymer substrates since the prior art screenable dielectrics thermally degrade at about 300°C.
  • the screenable polyimide of the invention is thermally stable at the elevated temperatures required to decompose the organometallics.
  • Applicants flexible circuits are capable of withstanding the decomposition temperature and organometallics may be used.
  • Thin conductive lines 48 on the order of about 1000 angstroms can be formed by this process.
  • the base of vias 46 is also made conductive by direct writing. The lines are quite thin and electrical conductivity is low.
  • a conductive layer 50 as illustrated in Figure 7C, is preferably deposited on conductive line 48.
  • the conductive layer 50 may be copper, gold or other highly conductive metal.
  • a barrier layer 26 is preferably employed to minimize surface contamination.
  • Direct writing is capable of producing lines having a width below about .051mm (2 mils). Spreading of the lines is minimal so electrical short circuits between adjoining lines are not likely.
  • the resolution with direct writing is about +/- .006mm (0.25 mils) with a pitch of .013mm (0.5 mils).
  • Extraordinarily small vias 46 may be formed in the screenable dielectric layer 16. These vias are then filled with a precise amount of material.
  • circuit traces 14 and conductive annuli 38 may be formed by direct writing. .051mm (2 mil) circuit traces may be written using an organometallic ink. The traces are then plated with copper or other conductive metal to a thickness which gives a desired conductivity. While the multi-layer circuits of the invention have been described in terms of two conductive layers, it should be apparent to those skilled in the art that a second layer of screenable dielectric may be deposited on the conductive paste. The second layer of screenable dielectric may also contain vias which are filled with a second layer of conductive paste. This process may be repeated multiple times to form multi-layer circuitry. Direct writing techniques with improved resolution is particularly suitable for a plurality of conductive layers.
  • circuits formed by the process of the invention are not limited to pin grid array circuits, any multilayer circuitry requiring a high density of interconnects may be formed. Among other applications of the circuits are multi-chip modules and hybrid packages.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Diélectrique pouvant être sérigraphié (16) et procédé de fabrication de circuits multicouches (10) selon une technique d'addition. Une pluralité de couches conductrices sont séparées par le diélectrique pouvant être sérigraphié (16). Pendant l'impression sérigraphique des interconnexions entre couches (46) sont formées dans le diélectrique (16) de manière qu'une partie sélective de traces de circuits sous-jacentes (14b) reste conductrice. Le diélectrique pouvant être sérigraphié (16) a un indice thixotrope élevé de manière qu'il s'écoule facilement dans la trame puis augmente rapidement en viscosité afin de réduire au minimum l'affaissement. Les parties conductrices (14b) sont interconnectées électriquement par une pâte conductrice (48) pouvant être déposée par impression sérigraphique ou par écriture directe.
PCT/US1991/000875 1990-03-05 1991-02-11 Procede et materiau de formation de circuits multicouches selon une technique d'addition WO1991014015A1 (fr)

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Application Number Priority Date Filing Date Title
US48855190A 1990-03-05 1990-03-05
US488,551 1990-03-05

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WO1991014015A1 true WO1991014015A1 (fr) 1991-09-19

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Cited By (45)

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US8970031B2 (en) 2009-06-16 2015-03-03 Hsio Technologies, Llc Semiconductor die terminal
US8981809B2 (en) 2009-06-29 2015-03-17 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US8981568B2 (en) 2009-06-16 2015-03-17 Hsio Technologies, Llc Simulated wirebond semiconductor package
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
US8987886B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
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US9076884B2 (en) 2009-06-02 2015-07-07 Hsio Technologies, Llc Compliant printed circuit semiconductor package
US9093767B2 (en) 2009-06-02 2015-07-28 Hsio Technologies, Llc High performance surface mount electrical interconnect
WO2015083160A3 (fr) * 2013-12-02 2015-10-08 Clearjet Ltd Procédé de commande de caractéristiques de mouillabilité
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US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US9231328B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc Resilient conductive electrical interconnect
US9232654B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc High performance electrical circuit structure
US9277654B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9320133B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Electrical interconnect IC device socket
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US9414500B2 (en) 2009-06-02 2016-08-09 Hsio Technologies, Llc Compliant printed flexible circuit
US9536815B2 (en) 2009-05-28 2017-01-03 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
US9559447B2 (en) 2015-03-18 2017-01-31 Hsio Technologies, Llc Mechanical contact retention within an electrical connector
WO2017027449A1 (fr) * 2015-08-12 2017-02-16 E. I. Du Pont De Nemours And Company Procédé de formation d'un conducteur à film épais de polymère à base de polyimide soudable
US9603249B2 (en) 2009-06-02 2017-03-21 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US9699906B2 (en) 2009-06-02 2017-07-04 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
WO2017171787A1 (fr) * 2016-03-31 2017-10-05 Intel Corporation Procédés pour favoriser l'adhérence entre des matériaux diélectriques et conducteurs dans des structures d'emballage
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
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US5879761A (en) * 1989-12-18 1999-03-09 Polymer Flip Chip Corporation Method for forming electrically conductive polymer interconnects on electrical substrates
CN1094655C (zh) * 1994-12-16 2002-11-20 住友电木株式会社 用丝网印刷的方法形成聚酰亚胺涂层
WO1996019012A1 (fr) * 1994-12-16 1996-06-20 Occidental Chemical Corporation Formation de revetements en polyimide par impression en surface
US7713578B2 (en) 2003-05-30 2010-05-11 Seiko Epson Corporation Method for fabricating thin film pattern, method for fabricating device, electro-optical apparatus, and electronic apparatus
US8955215B2 (en) 2009-05-28 2015-02-17 Hsio Technologies, Llc High performance surface mount electrical interconnect
US9536815B2 (en) 2009-05-28 2017-01-03 Hsio Technologies, Llc Semiconductor socket with direct selective metalization
US9276336B2 (en) 2009-05-28 2016-03-01 Hsio Technologies, Llc Metalized pad to electrical contact interface
US9660368B2 (en) 2009-05-28 2017-05-23 Hsio Technologies, Llc High performance surface mount electrical interconnect
US8987886B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US9136196B2 (en) * 2009-06-02 2015-09-15 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US8955216B2 (en) 2009-06-02 2015-02-17 Hsio Technologies, Llc Method of making a compliant printed circuit peripheral lead semiconductor package
US8912812B2 (en) 2009-06-02 2014-12-16 Hsio Technologies, Llc Compliant printed circuit wafer probe diagnostic tool
US9699906B2 (en) 2009-06-02 2017-07-04 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US9930775B2 (en) 2009-06-02 2018-03-27 Hsio Technologies, Llc Copper pillar full metal via electrical circuit structure
US10609819B2 (en) 2009-06-02 2020-03-31 Hsio Technologies, Llc Hybrid printed circuit assembly with low density main core and embedded high density circuit regions
US8988093B2 (en) 2009-06-02 2015-03-24 Hsio Technologies, Llc Bumped semiconductor wafer or die level electrical interconnect
US9414500B2 (en) 2009-06-02 2016-08-09 Hsio Technologies, Llc Compliant printed flexible circuit
US9613841B2 (en) 2009-06-02 2017-04-04 Hsio Technologies, Llc Area array semiconductor device package interconnect structure with optional package-to-package or flexible circuit to package connection
US9054097B2 (en) 2009-06-02 2015-06-09 Hsio Technologies, Llc Compliant printed circuit area array semiconductor device package
US9076884B2 (en) 2009-06-02 2015-07-07 Hsio Technologies, Llc Compliant printed circuit semiconductor package
US9093767B2 (en) 2009-06-02 2015-07-28 Hsio Technologies, Llc High performance surface mount electrical interconnect
US8928344B2 (en) 2009-06-02 2015-01-06 Hsio Technologies, Llc Compliant printed circuit socket diagnostic tool
US9603249B2 (en) 2009-06-02 2017-03-21 Hsio Technologies, Llc Direct metalization of electrical circuit structures
US9184145B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Semiconductor device package adapter
US9184527B2 (en) 2009-06-02 2015-11-10 Hsio Technologies, Llc Electrical connector insulator housing
US9196980B2 (en) 2009-06-02 2015-11-24 Hsio Technologies, Llc High performance surface mount electrical interconnect with external biased normal force loading
US9231328B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc Resilient conductive electrical interconnect
US9232654B2 (en) 2009-06-02 2016-01-05 Hsio Technologies, Llc High performance electrical circuit structure
US9277654B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Composite polymer-metal electrical contacts
US9276339B2 (en) 2009-06-02 2016-03-01 Hsio Technologies, Llc Electrical interconnect IC device socket
US20120056332A1 (en) * 2009-06-02 2012-03-08 Hsio Technologies, Llc Compliant printed circuit wafer level semiconductor package
US9318862B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Method of making an electronic interconnect
US9320133B2 (en) 2009-06-02 2016-04-19 Hsio Technologies, Llc Electrical interconnect IC device socket
WO2010141297A1 (fr) * 2009-06-02 2010-12-09 Hsio Technologies, Llc Boîtier de semi-conducteur sur tranche à circuit imprimé adaptable
US8981568B2 (en) 2009-06-16 2015-03-17 Hsio Technologies, Llc Simulated wirebond semiconductor package
US8970031B2 (en) 2009-06-16 2015-03-03 Hsio Technologies, Llc Semiconductor die terminal
US9320144B2 (en) 2009-06-17 2016-04-19 Hsio Technologies, Llc Method of forming a semiconductor socket
US8981809B2 (en) 2009-06-29 2015-03-17 Hsio Technologies, Llc Compliant printed circuit semiconductor tester interface
US8984748B2 (en) 2009-06-29 2015-03-24 Hsio Technologies, Llc Singulated semiconductor device separable electrical interconnect
US9350093B2 (en) 2010-06-03 2016-05-24 Hsio Technologies, Llc Selective metalization of electrical connector or socket housing
US10159154B2 (en) 2010-06-03 2018-12-18 Hsio Technologies, Llc Fusion bonded liquid crystal polymer circuit structure
US9689897B2 (en) 2010-06-03 2017-06-27 Hsio Technologies, Llc Performance enhanced semiconductor socket
US9350124B2 (en) 2010-12-01 2016-05-24 Hsio Technologies, Llc High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly
WO2013029041A2 (fr) * 2011-08-25 2013-02-28 Amphenol Corporation Carte de circuit imprimé haute performance
WO2013029041A3 (fr) * 2011-08-25 2013-06-20 Amphenol Corporation Carte de circuit imprimé haute performance
US9761520B2 (en) 2012-07-10 2017-09-12 Hsio Technologies, Llc Method of making an electrical connector having electrodeposited terminals
US10453789B2 (en) 2012-07-10 2019-10-22 Hsio Technologies, Llc Electrodeposited contact terminal for use as an electrical connector or semiconductor packaging substrate
US10667410B2 (en) 2013-07-11 2020-05-26 Hsio Technologies, Llc Method of making a fusion bonded circuit structure
US10506722B2 (en) 2013-07-11 2019-12-10 Hsio Technologies, Llc Fusion bonded liquid crystal polymer electrical circuit structure
WO2015083160A3 (fr) * 2013-12-02 2015-10-08 Clearjet Ltd Procédé de commande de caractéristiques de mouillabilité
US9755335B2 (en) 2015-03-18 2017-09-05 Hsio Technologies, Llc Low profile electrical interconnect with fusion bonded contact retention and solder wick reduction
US9559447B2 (en) 2015-03-18 2017-01-31 Hsio Technologies, Llc Mechanical contact retention within an electrical connector
WO2017027449A1 (fr) * 2015-08-12 2017-02-16 E. I. Du Pont De Nemours And Company Procédé de formation d'un conducteur à film épais de polymère à base de polyimide soudable
WO2017171787A1 (fr) * 2016-03-31 2017-10-05 Intel Corporation Procédés pour favoriser l'adhérence entre des matériaux diélectriques et conducteurs dans des structures d'emballage

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