WO1995026570A1 - Dispositif a memoire ferro-electrique - Google Patents

Dispositif a memoire ferro-electrique Download PDF

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Publication number
WO1995026570A1
WO1995026570A1 PCT/JP1995/000533 JP9500533W WO9526570A1 WO 1995026570 A1 WO1995026570 A1 WO 1995026570A1 JP 9500533 W JP9500533 W JP 9500533W WO 9526570 A1 WO9526570 A1 WO 9526570A1
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WO
WIPO (PCT)
Prior art keywords
ferroelectric
capacitor
memory device
ferroelectric memory
voltage
Prior art date
Application number
PCT/JP1995/000533
Other languages
English (en)
Japanese (ja)
Inventor
Hiroshi Nakano
Masayoshi Ohmura
Original Assignee
Olympus Optical Co., Ltd.
Symetrix Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP6058397A external-priority patent/JPH1140759A/ja
Priority claimed from JP6222896A external-priority patent/JPH1139860A/ja
Application filed by Olympus Optical Co., Ltd., Symetrix Corporation filed Critical Olympus Optical Co., Ltd.
Publication of WO1995026570A1 publication Critical patent/WO1995026570A1/fr

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5657—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using ferroelectric storage elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors

Definitions

  • the present invention relates to a ferroelectric memory device using a ferroelectric material for an information recording medium, and in particular, to a ferroelectric memory device for performing non-destructive readout using a twisted- ⁇ hysteresis characteristic. Also, the present invention relates to a ferroelectric memory device using a ferroelectric for a recording medium, and more particularly to a ferroelectric memory device capable of reducing a stable polarization value by at least 3 using a twisted-hysteresis characteristic. The present invention relates to a ferroelectric memory device using a ferroelectric memory element exhibiting multiple hysteresis characteristics having more than one device.
  • ferroelectric materials have hysteresis characteristics and can store information as a non-volatile memory using this characteristic.
  • the reading method of these ferroelectric memories has been performed by destructive reading using a domain-inverted current that requires rewriting of a selected cell.
  • ferroelectric memory by the destructive readout method is characterized by the fact that polarization reversal is repeated and ferroelectricity deteriorates, so that the remanent polarization is reduced. It is not only difficult to prolong the service life due to problems such as the problem of rewriting, but also it is necessary to rewrite with a complicated circuit.
  • non-destructive information is read in a read electric field smaller than the coercive electric field by utilizing a capacitance difference controlled by a polarization state. Reading is being performed.
  • the difference in capacitance between recorded and unrecorded states is small, so that the S / N ratio is deteriorated and the cell integration is reduced.
  • MFIS device MFMIS
  • FET field effect transistor
  • Figure 22A shows an example of a conventional MFMIS-type device, — ⁇
  • This is an equivalent circuit composed of a combination of a tower (Sawyer Tower) circuit and a field-effect transistor.
  • the in V in this respect is a positive value
  • in the voltage V eT to M Q point is a negative value.
  • the voltage information stored in the dielectric capacitor ( CL ) 2 is read out by the field-effect transistor 203.
  • the field-effect transistor 203 is an n-type MOSFET, so that at a point, the field-effect transistor 203 is in a conducting state, at a point, a non-conducting state, and The difference in voltage at point Q can be read.
  • the voltage v ei; ( —
  • V FE V FE
  • a memory element having a configuration shown in FIG. 23A has been devised as a memory element capable of nondestructive operation to prevent the deterioration of the strong dielectric thin film.
  • This memory element includes a ferroelectric capacitor 206, a dielectric capacitor 207 connected in series to the ferroelectric capacitor 206, and a resistance element 208 connected in parallel to the dielectric capacitor 207. Consists of Also, this memory The element is provided with a field-effect transistor 209 as a switch element for reading.
  • FIG. 23B shows a hysteresis characteristic in a circuit in which the resistive element 208 is connected in parallel with the dielectric capacitor 207.
  • the storage voltages ⁇ ⁇ , ⁇ ⁇ have two polarizations P 0, P j of the ferroelectric capacitor 206 and electric fields in the directions of the polarizations. Is obtained.
  • the current flowing between the terminal 205 and the ground via the field effect transistor 209 which is ON-OFF controlled by the voltage of the dielectric capacitor 207 Can be detected.
  • the polarity of the stored information is detected as the direction of the read current by using a switch element that is actually turned on by a positive voltage and a conductive switch element that is turned on by a negative voltage.
  • a storage element is used for an arithmetic unit or the like.
  • the readout switch element an element composed of an n-type MOS transistor and a p-type MOS transistor formed on a silicon (Si) substrate is known. It is.
  • each memory element is marked with 1 or 0, and a sequence of these two numerical values is used as stored information.
  • the present invention has been made in view of the above-described points, and can perform non-destructive readout by using the twisted-hysteresis characteristic, has a long life, and is ferroelectric suitable for integration. It is intended to provide a body memory device.
  • the present invention provides a ferroelectric memory device using a ferroelectric memory element having a multiple hysteresis characteristic having at least three or more stable polarization values by utilizing the twisted hysteresis characteristic.
  • the purpose is to provide.
  • a ferroelectric memory device is provided which differs in at least one of the sizes.
  • a plurality of first capacitor units formed by ferroelectric capacitors are formed on the insulator, and a plurality of first capacitor units having different coercive electric fields from the first capacitor unit on the insulator.
  • the second capacitor unit is formed with a lower electrode newly formed on the insulator, a ferroelectric film formed on the lower electrode, and a ferroelectric film formed on the lower electrode. And at least one or more of the first and second capacitor units are electrically connected to each other.
  • a ferroelectric memory device is provided.
  • the multi-hysteresis characteristic having at least three or more stable electrode values is provided, and the multi-valued voltage accompanying the multi-hysteresis characteristic is used as information.
  • a ferroelectric capacitor formed by sandwiching a ferroelectric between electrode materials; a dielectric capacitor connected in series to the ferroelectric capacitor; and the multiple hysteresis stored in the ferroelectric capacitor.
  • a ferroelectric memory device including a voltage-current conversion element for reading out multi-valued voltage information accompanying the lysis characteristic.
  • the electric field strength of the second electrode area is smaller than the electric field strength of the first electrode area. It becomes smaller, and has the same effect as if a ferroelectric capacitor with a different coercive electric field (or film thickness) and area were connected in parallel, and a twisted hysteresis characteristic was obtained.
  • the memory state "0" and memory state "1" of this twisted hysteresis characteristic In these two values, the information stored by the back-switching phenomenon is read non-destructively.
  • the ferroelectric memory device is such that a first ferroelectric capacitor (unit) is sandwiched between electrodes made of a conductor on both sides of a ferroelectric substance on a substrate or an insulator. And a second ferroelectric capacitor (unit) having a different coercive electric field or a different film thickness is formed in parallel or in a stacked configuration. A cis characteristic is obtained.
  • the ferroelectric memory device having the configuration according to the third aspect includes a ferroelectric capacitor having multiple hysteresis characteristics having at least three or more stable polarization values and a serial connection with the ferroelectric capacitor.
  • a ferroelectric memory element consisting of a connected dielectric capacitor and a multi-valued voltage information written using the multiple hysteresis characteristic is read out by a voltage-to-current conversion element. Three or more pieces of voltage information can be obtained when the polarization state changes with a stable polarization value.
  • FIG. 1 is a diagram showing a combined hysteresis characteristic in a ferroelectric memory device according to a first embodiment of the present invention
  • FIG. 2 is a diagram showing a configuration of a ferroelectric capacitor in the ferroelectric memory device of the first embodiment
  • FIG. 3 is a block diagram showing a configuration in which the ferroelectric capacitors shown in FIG. 2 are arranged as a memory cell and peripheral circuits are connected;
  • FIG. 4 is a diagram showing a configuration example of the ferroelectric memory device according to the second embodiment of the present invention in which the shape of the upper electrode of the ferroelectric capacitor is different;
  • FIG. 5 is a view showing a configuration example of a ferroelectric memory device according to a third embodiment of the present invention in which ferroelectric capacitors having different coercive electric fields having the structure shown in FIG. 2 or FIG. 4 are connected in parallel. ;
  • FIG. 6 is a diagram showing a configuration in which ferroelectric capacitors formed of different ferroelectric materials and having different coercive electric fields are connected in parallel in a ferroelectric memory device according to a fourth embodiment of the present invention
  • FIG. 7A and 7B show a ferroelectric capacitor showing a symmetric hysteresis characteristic and a ferroelectric capacitor showing an asymmetric hysteresis characteristic in a ferroelectric memory device according to a fifth embodiment of the present invention.
  • FIGS. 8A to 8E are diagrams showing an example of a laminated structure of a ferroelectric capacitor having an asymmetric hysteresis characteristic in a ferroelectric memory device according to a sixth embodiment of the present invention and the characteristics thereof;
  • FIGS. 9A and 9B are diagrams showing another structural example and characteristics of a ferroelectric capacitor having asymmetric hysteresis characteristics in a ferroelectric memory device according to a seventh embodiment of the present invention.
  • FIG. 10 is a diagram showing an example of a laminated structure of ferroelectric capacitors formed in parallel on a substrate in a ferroelectric memory device according to an eighth embodiment of the present invention.
  • FIG. 11 shows a ferroelectric memory device formed in parallel on a substrate in a ferroelectric memory device according to a ninth embodiment of the present invention. View showing another example of the laminated structure
  • FIG. 12 is a diagram showing an example of a laminated structure of ferroelectric capacitors formed by being laminated on a substrate in a ferroelectric memory device according to a tenth embodiment of the present invention
  • FIGS. 13A, 13B and 13C show the multiple hysteresis characteristics of the ferroelectric memory element used in the ferroelectric memory device according to the eleventh embodiment of the present invention.
  • FIGS. 14A to 14H show the multi-hysteresis characteristics and spontaneous polarization of the ferroelectric memory device shown in FIG. 13B;
  • FIGS. 15A and 15B show the first and second embodiments of the present invention, respectively.
  • FIG. 1 is a diagram showing a configuration of a ferroelectric memory device used in a ferroelectric memory device as an example and a current-voltage characteristic of the ferroelectric memory device;
  • FIGS. 16A to 16C show the configuration of a ferroelectric memory device used in a ferroelectric memory device according to a thirteenth embodiment of the present invention, and multiple hysteresis of the ferroelectric memory device.
  • FIG. 17 is a diagram showing a configuration of a ferroelectric memory device as a 14th embodiment according to the present invention.
  • FIGS. 18A to 18C show the structure and configuration of a ferroelectric memory device according to a fifteenth embodiment of the present invention, respectively;
  • FIGS. 19A and 19B are diagrams showing the structure of a ferroelectric memory element used in a ferroelectric memory device as a 16th embodiment according to the present invention.
  • FIGS. 20A and B show a 17th embodiment according to the present invention, respectively.
  • FIGS. 21A and 21B are diagrams each showing an application example to a matrix calculator for multiply-accumulate operation by a ferroelectric memory device according to an eighteenth embodiment of the present invention.
  • FIGS. 22A and 22B show a circuit example of a conventional MIS element and a hysteresis characteristic of the MIS element, respectively;
  • Figures 23A and B are diagrams showing a configuration example of a conventional non-destructive storage element and a hysteresis characteristic of the storage element, respectively;
  • FIG. 1 shows a first embodiment according to the present invention.
  • 2 shows a composite hysteresis characteristic of the ferroelectric memory device of FIG. Figure 2 shows the configuration of the ferroelectric capacitor.
  • the composite hysteresis characteristic shown in FIG. 1 is such that at least one of the areas of the areas facing the formation and arrangement of the first and second electrodes of the strong dielectric capacitor differs as will be described later. This is the combined hysteresis (hereinafter, referred to as twisted hysteresis) characteristic obtained when the above is obtained.
  • the ferroelectric capacitor 1 is provided with a lower electrode 3 made of a conductor below the ferroelectric 2 and an upper electrode 4 having a smaller electrode area than the lower electrode 3. Is provided above the ferroelectric 2.
  • the thickness d of the ferroelectric material 2 used for the unit memory cell unit arranged in the memory cell array unit of the ferroelectric memory device described later is defined as the area S i of the electrode of the upper electrode 4. Assuming that the diagonal polarization P 2 is generated in the vertical direction P 2 , the diagonal polarization P 2 is generated in the area S 2 of the dipole P i generated in the area S 2 having only the lower electrode without the upper electrode 4 and having only one side electrode part. Direction), it becomes P 2 '. Therefore, it is assumed that the polarization of the memory cell portion is composed of the P i component and the P 2 ′ component.
  • Figure 1 shows the combined hysteresis characteristics of the polarizations P i and ⁇ 2 '.
  • a ferroelectric capacitor as shown in Fig. 2 is considered to be the same as connecting two ferroelectric capacitors with different coercive electric fields in parallel, so the medium of the high-speed hysteresis characteristics as shown in Fig. 1 is obtained. Non-destructive reading by the back switching phenomenon becomes possible in two values of the memory state "0" and the memory state "1". However, state "2" in Fig. 1 is not used as information recording.
  • the ferroelectric capacitor 1 is also arranged as a memory cell array as a unit memory cell, and its peripheral circuits are a write circuit 6, a read circuit 7, a switching circuit 8, and a row switching control.
  • FIG. 2 is a block diagram showing a circuit configuration of the entire ferroelectric memory device to which a unit 9 and a column switching control unit 10 are connected.
  • the writing circuit 6, the row switching control unit 9, and the column switching control unit 10 apply a coercive electric field e c to each cell of the matrix memory 5 or a writing voltage e larger than e.
  • w [e c '> e m > e £ ( Note re state "1"), e ro> e e' ( Note re state "CT)] polarization direction of the information written to each cell by applying a is It is done.
  • the switching circuit 8 is set so that the reading circuit 7 operates. Row et al of the column switching with a control circuit 9, 1 0, large voltage e information of the selected cell Ri by anti electric field e e. (e c '>e.> e c ) and read.
  • the differential dielectric constant slope of the hysteresis
  • the differential dielectric constant is significantly different from the applied read voltage at "0" and "1", so that the output current has a large difference. Then, it is possible to determine the state of "1” and "0” and read out the information in a non-destructive manner.
  • the ferroelectric memory device of the second embodiment is as follows.
  • the use of a ferroelectric capacitor formed with the upper electrode as a strip-shaped upper electrode 11 as shown in Fig. 4 adds a portion to which an oblique electric field is applied, resulting in good twisted hysteresis characteristics. I try to make it easier.
  • the ferroelectric memory device according to this embodiment has the same dielectric constant ⁇ 1, thickness dl, d2, and area SI, S2.
  • Fig. 5 shows a ferroelectric capacitor 1 having a high steered hysteresis characteristic as shown in Fig. 1 and having a different coercive electric field of the structure shown in Fig. 2 or Fig. 4. This is a configuration where they are connected in parallel.
  • ferroelectric Note Re device t this embodiment will be described ferroelectric Note Re device of the fourth embodiment, as shown in FIG. 6, the dielectric constant £ 1, epsilon 2 and area SI, Since S2 is made of a different ferroelectric material, ferroelectric capacitors having different coercive electric fields are connected in parallel.
  • the difference in the differential permittivity during the back switching phenomenon in the memory states "0" and "1" of the twisted hysteresis characteristics as shown in Fig. 1 obtained from such a structure can be used to increase the output current. A difference is created, and the state of "0" and "1" can be read nondestructively.
  • a ferroelectric memory device according to a fifth embodiment will be described.
  • the ferroelectric memory device includes a ferroelectric capacitor A having symmetric hysteresis characteristics and an asymmetric hysteresis as shown in FIG. 7B.
  • a ferroelectric capacitor B exhibiting cis characteristics is connected in parallel as shown in Fig. 7A. With this configuration, a composite hysteresis characteristic of AZZB can be obtained as shown in FIG. 7B.
  • ferroelectric Note Re device t this embodiment will be described ferroelectric Note Re device of the sixth embodiment of the MFMIS having an asymmetric hysteresis characteristic of the laminated structure as shown in FIG. 8A A ferroelectric capacitor is used.
  • an insulator film 22, a conductor film 23, a ferroelectric film 24, and a conductor film 25 are sequentially laminated on an n-type semiconductor substrate 21. .
  • the depletion layer of the MIS type capacitor (21, 22, 23) composed of the lower three layers is controlled by the direction of polarization of the ferroelectric 24. With this effect, an asymmetric hysteresis characteristic as shown in FIG. 8B is obtained.
  • the ferroelectric memory device according to the seventh embodiment has a MFMIS-type ferroelectric memory having an asymmetric hysteresis characteristic of a laminated structure as shown in FIG. 9A.
  • a body capacitor is used.
  • an insulator thin film 27 Sio
  • a ferroelectric film 28 and an upper electrode 29 are sequentially formed on an n-type semiconductor substrate 26.
  • the thickness of the depletion layer on the surface of the n-type semiconductor substrate 26 is controlled by the direction of polarization of the ferroelectric film 28. Because I Ri insulator film 2 7 thickness thereto is changed equivalently, the asymmetric hysteresis characteristic shown in FIG. 9 B obtained £ Then, ferroelectric Note Re apparatus of the eighth embodiment ferroelectric memory device of c explaining this embodiment uses a ferroelectric capacitor formed in parallel form laterally stacked structure as shown in FIG. 1 0.
  • an n-type well region 39 is formed on a P-type semiconductor (Si) substrate 31 and an insulating film 32, a lower electrode 33, a ferroelectric film 34, A unit A having a plurality of asymmetric capacitors formed by an upper electrode 35, a lower electrode 33, a ferroelectric film 38 and an upper electrode 35 on the P-type semiconductor substrate 31.
  • a unit B having a plurality of capacitors having symmetrical hysteresis characteristics is formed.
  • the ferroelectric film 34 included in the unit A has a coercive electric field different from that of the ferroelectric film 38 of the unit B.
  • the ferroelectric Note Re apparatus of the ninth embodiment of the ferroelectric Note for Li apparatus illustrating £ this embodiment is formed in parallel form laterally stacked structure as shown in FIG. 1 1 Use a ferroelectric capacitor.
  • an insulating film 42 is formed on a semiconductor substrate 41, and a lower electrode 43 is further formed. Thereafter, a desired portion of the lower electrode 43 is etched to form a thin portion.
  • a ferroelectric film 44 is formed on the lower electrode so as to have a flat surface by using the Spin On technology, and an upper electrode 46 is further formed.
  • the lower electrode 43 is formed on the thick part.
  • a ferroelectric capacitor comprising a plurality of second electrodes comprising a first electrode and a second electrode, wherein at least one of the formation arrangement of the first electrode and the second electrode is different from the size of the facing electrode area.
  • the first electrode and the second electrode of the ferroelectric capacitor can be formed by changing the arrangement relationship or the size of the opposing electrode area. Since the twisted hysteresis characteristic is obtained, information can be read nondestructively using the twisted hysteresis characteristic.
  • the ferroelectric capacitor of (2) at least one of the first and second electrodes is changed in shape to increase the area of the portion to which the oblique electric field is applied. As a result, good twisted hysteresis characteristics can be easily obtained.
  • the plurality of capacitor units A thus formed have a smaller coercive electric field because the ferroelectric film 44 has a smaller film thickness than the plurality of capacitor units B formed in the portion where the lower electrode 43 is thin.
  • the capacitor units A and B having different coercive electric fields are arbitrarily connected using the wiring electrode 47, and a ferroelectric capacitor having a desired twisted-state hysteresis characteristic is obtained.
  • the ferroelectric memory device of the present embodiment uses a ferroelectric capacitor formed in a vertically-parallel manner with a laminated structure as shown in FIG.
  • an insulating film 52 is formed on a semiconductor substrate 51, and three layers of a lower electrode 53, a ferroelectric film 54, and an upper electrode 55 are further formed.
  • a unit B composed of a plurality of capacitors having a structure, and an interlayer insulating film 56 formed on the unit B, a lower electrode 57, a ferroelectric 58, and an upper electrode 5 9 and a unit A composed of a plurality of capacitors composed of nine capacitors.
  • two ferroelectric capacitors whose coercive fields are more than three times different from each other are formed by using different materials or changing the film thickness with the same material. can do.
  • the capacitors of unit A and unit B are arbitrarily connected using wiring electrode 60, and a ferroelectric capacitor having desired characteristics can be obtained.
  • a ferroelectric capacitor having desired characteristics can be obtained.
  • the values of the coercive electric fields are different from each other, and the capacitance of the ferroelectric capacitor at the time of back switching in several polarization states of the twisted hysteresis.
  • a ferroelectric memory device characterized in that the polarization state is read out nondestructively by using a method.
  • the plurality of ferroelectric capacitors have different values of the coercive electric field of the ferroelectrics, and can be obtained with respect to those ferroelectric capacitors.
  • the polarization state can be read out nondestructively by utilizing the capacitance difference at the time of back switching in some polarization states of the distant hysteresis characteristics.
  • the ferroelectric capacitors having different coercive fields are formed by connecting materials having different relative dielectric constants in parallel to each other, thereby obtaining a high-speed hysteresis.
  • a memory device with characteristics is configured, and the polarization state can be read out nondestructively by utilizing the capacitance difference during back-switching of some polarization states of the twisted hysteresis characteristics.
  • At least one of the plurality of ferroelectric capacitors connected in parallel has asymmetric hysteresis characteristics
  • the polarization state can be read nondestructively by utilizing the capacitance difference at the time of switching of the twisted hysteresis characteristics.
  • the memory state can be read nondestructively by applying the read drive voltage under an electric field larger than the coercive electric field.
  • high density is possible due to large SZN.
  • the ferroelectric capacitor having asymmetric hysteresis according to (5) wherein the ferroelectric memory device has a multilayer structure of a conductor, a ferroelectric, a conductor, an insulator, and a semiconductor. . Therefore, according to the ferroelectric memory device of (7), the ferroelectric capacitor having the asymmetric hysteresis characteristic described in (5) can be a conductor, a ferroelectric, a conductor, an insulator, It has a multi-layer structure of semiconductor.
  • the ferroelectric memory device having the above constitutions (6) and (7), the twisted hysteresis characteristic for realizing the non-destructive read ferroelectric memory having a large SZN can be easily obtained. Will be obtained.
  • a unit ferroelectric capacitor comprising a lower electrode film formed on an insulator, a ferroelectric film formed on the lower electrode film, and an upper electrode film formed on the ferroelectric film
  • a plurality of first capacitor units are formed on the insulator, and a plurality of second capacitor units having different coercive electric fields from the first capacity unit are formed on the insulator.
  • the ferroelectric memory device of (8) when an electric field is applied to the ferroelectric capacitor, the electric field strength of the second electrode area becomes smaller than that of the first electrode area.
  • the ferroelectric capacitor has a smaller area and a different coercive field (or film thickness) and area. This has the same effect as connecting a capacitor in parallel, and a twisted hysteresis characteristic is obtained.
  • the binary state of the memory state "0" and the memory state -1 of this twisted hysteresis characteristic is obtained. In, information stored by the back switching phenomenon can be read out nondestructively.
  • the coercive electric field is different due to the different ferroelectric thicknesses of the plurality of first and second ferroelectric capacitor units, and the twisty field is different.
  • a ferroelectric capacitor having a dehysteresis characteristic is formed.
  • the ferroelectric memory device of (11) the first ferroelectric capacitor unit and the second ferroelectric capacitor unit having different coercive electric fields are laminated and formed three-dimensionally. It is composed.
  • the ferroelectric memory device of (11) is capable of electrically connecting a plurality of ferroelectric capacitor units having different coercive electric fields to provide a ferroelectric device having a desired twisted hysteresis characteristic. Capacitors can be obtained.
  • a first unit formed by arranging a plurality of first unit ferroelectric capacitors each having a laminated structure of a lower electrode film, a ferroelectric film, and an upper electrode film sequentially formed on an insulator.
  • a second capacitor unit having the same laminated structure as the first unit ferroelectric capacitor and having a plurality of second unit ferroelectric capacitors having different coercive electric fields arranged on the insulator;
  • a ferroelectric device characterized in that at least one unit ferroelectric capacitor in each of the capacitor unit and at least one unit ferroelectric capacitor in the second capacitor unit has a storage medium electrically connected in series or in parallel. Body memory device.
  • the stored information can be read out nondestructively, and the ferroelectric memory having a long life and suitable for integration is provided.
  • Providing equipment Can be.
  • a ferroelectric capacitor having a twisted hysteresis characteristic for realizing the non-destructive read ferroelectric memory device having a large SZN.
  • a ferroelectric capacitor having desired twisted hysteresis characteristics can be formed.
  • the ferroelectric memory devices of the first and second embodiments can be applied to multi-valued memory of two or more values by using the same back switching phenomenon in two or more values. .
  • Figure 13A shows the twisted hysteresis characteristic of the ferroelectric used in the ferroelectric memory device, that is, the multiple hysteresis characteristic. Inflection points are shown, and two inflection points are shown for a negative electric field. An example of this ferroelectric memory element will be described below.
  • FIGS. 14A to 14H are diagrams showing the multi-hysteresis characteristic and the spontaneous polarization.
  • Ferroelectric having multiple hysteresis characteristics Equivalently, considered parallel connection of C FE L OW showing the C FE H IgH and low coercive field characteristics showing a high coercive electric field characteristics.
  • a circuit configuration in which a ferroelectric capacitor is directly connected to a dielectric capacitor is used to measure the amount of charge associated with the polarization reversal of the ferroelectric (Soyer-tower method).
  • the soy tower method uses the dielectric capacity to transfer the charge associated with the polarization reversal. This is a method of transferring the data to a computer for observation. At this time, the electric charge stored in the ferroelectric capacitor and the dielectric capacitor is free, and due to the leakage resistance, the charge gradually decreases to zero regardless of the presence or absence of spontaneous polarization of the ferroelectric.
  • X represents a composition ratio and ranges from 0.2 to 1.0
  • y represents a composition ratio and ranges from 0.85 to 1.0.
  • 1 3 voltage-current conversion element 1 3 shown in B is has a good UNA characteristic of FIG. 1 3 C, 0. 7 when the (m A), when the 2 V L 1. 4 (m A ) Is shown.
  • V RE AD a predetermined voltage
  • FIG. 15A a ferroelectric memory element included in a ferroelectric memory device according to a 12th embodiment of the present invention.
  • This ferroelectric memory element is configured as shown in FIG. 15A using the multi-hysteresis ferroelectric capacitor described above.
  • FIG. Referring to A and B, we clarify the relationship between spontaneous polarization and memory voltage.
  • Uni ferroelectric Note Li element by shown in FIG. 23 A is strongly dielectric key Yapashita (C FE) 206, and Soiya Tower circuit consisting of series connection of the dielectric capacitor) 20 7, a ferroelectric capacitor (C FE ) Charge-effect transistor (n Type MO SFET) 209 controlled by charge stored in dielectric capacitor (CL) 207 according to polarization change of 206, and dielectric capacitor (C j ⁇ ) 207 and a resistance element 208 connected in parallel.
  • a voltage signal is input from the input terminal 204, and the memory is input. Write operation to.
  • the voltage applied to the ferroelectric capacitor (C Fr ) 201 is applied to the V F dielectric capacitor (C,) 202 by polarization of the ferroelectric capacitor (C FE ) 201.
  • the pressure V e, and to those graphed is a hysteresis Li cis characteristics shown in FIG. 22 B.
  • FIG. 23A by providing the resistive element 208, the above-described excess charge is removed, and the holding state is the same as the direction of the voltage applied during polarization, as shown in the hysteresis characteristic shown in FIG. 23B. Has been obtained.
  • the second embodiment has the configuration shown in FIG. 15A, and the ferroelectric capacitor (C FE ) 206 of FIG. 23 A is changed to a multi-hysteresis ferroelectric capacitor (C FE ) 31. It is the structure which did.
  • the retained information is O mA, 1.5 mA, and 3 mA, respectively. Determine the current flowing through 24 Can be detected.
  • FIGS. 16A, 16B and 16C a ferroelectric memory element constituting a ferroelectric memory device according to a thirteenth embodiment of the present invention will be described with reference to FIGS. 16A, 16B and 16C.
  • V MP I V MPO by applying ⁇ v 2 becomes the magnitude of the sinusoidal voltage (or pulse)
  • 3 V MP2
  • the characteristics of the voltage-current conversion elements 33 and 34 used for reading are as shown in Fig. 16C with respect to the voltage between terminals 40 and 35 or the voltage between terminals 39 and 35. Is shown. Reading in the ferroelectric memory element of this embodiment is performed by connecting the terminals 37 and 38 to ground, connecting the terminal 39 to a positive power supply, and connecting the terminal 40 to a negative power supply.
  • the voltage-current conversion element 33 is a p-type MOS transistor
  • the voltage-current conversion element 34 is an n-type MOS transistor.
  • the read element composed of the voltage-current conversion element 33 and the voltage-current conversion element 34 has a terminal 39 connected to the positive power supply and a terminal 40 connected to the negative power supply. It is assumed that the relationship between the current I flowing from the terminal 36 and the potential V of 35 is set as shown in FIG. 16C.
  • the resistor is lk ⁇ and the storage state is + V M , a current of -1 mA flows from the output terminal 36, so that the potential difference of --IV can be detected and At v M , the potential difference is + IV.
  • the storage state is 0, a potential difference of 0 V can be detected.
  • the ferroelectric memory device includes a ferroelectric capacitor 41 having a multi-history characteristic, a dielectric capacitor 42 arranged in series with the ferroelectric capacitor 41, and a dielectric capacitor 42. And a reading circuit including voltage-to-current conversion elements 44 and 45.
  • the multi-hysteresis characteristics of this ferroelectric capacitor are assumed to be the same as the characteristics shown in FIGS. 14A to 14H.
  • the voltage between the terminals 46 and 47 is controlled to be in the state 1 (polarization Pi) shown in FIGS. 14A and 14B. Then, the voltage v P1 is held as a voltage of the opposite polarity to the voltage v p2 .
  • the power supply for writing has both positive and negative polarities, and the magnitude is arbitrarily controlled.
  • ⁇ p
  • a positive power supply is connected to the terminal 4S
  • a negative power supply is connected to the terminal 49
  • the potential of the terminal 50 changes from negative to positive with respect to the ground. Then, the characteristics shown in FIG. 16C are shown.
  • FIGS. 18A, B and C An example of a ferroelectric memory device will be described.
  • the ferroelectric memory device of this embodiment includes a ferroelectric capacitor 61, a dielectric capacitor 62, a resistor 63, a p-type MOS, and a n-type MOS formed on a silicon (Si) substrate.
  • Voltage-to-current conversion elements 64 and 65 each formed of a MOS transistor.
  • 66 is an input terminal
  • 67 is an output terminal
  • 68 is a positive power supply terminal
  • 69 is a negative power supply terminal.
  • the voltage-current conversion characteristics as shown in FIG. 16C can be realized by performing the electrical wiring shown in FIG. 18C using the p-M0S, n-MOS transistor.
  • the M0S type transistor is a field-effect type transistor, in which 0 N and 0 FF control of the transistor is performed by an electric field, and current injection is required as in a bipolar type transistor. do not do.
  • the detection can be performed without reducing the charge, and a long-term storage is possible.
  • a parasitic capacitance called Ces is generated between the terminal 72 and the terminal 71 shown in FIG. 19A.
  • This is a parasitic capacitance formed between the PO 1 y Si gate electrode and the P + diffusion layer (source) by using the gate oxide film Si 0 2 as a dielectric. It depends on the thickness d of the oxide film and the overlapped area S of the P o 1 y Si gate electrode and the P + diffusion layer (source). In other words,
  • the capacitance value is increased. Also, if the thickness d is reduced, the capacitance value also increases.
  • the ferroelectric material having a multi-hysteresis characteristic
  • a device was created by controlling only the overlap area so as to have a value 10 times the capacitance value near the V bias.
  • a resistor element is made by separately providing a resistor made of Po1ySi between terminal 71 and terminal 72.
  • the memory element according to the present invention accesses the memory for 10 to 8 sec, and the capacitance of the charge holding capacitor is set to lxl CT 13 (F).
  • the resistance created by was set to 5 ⁇ 10 4 ⁇ .
  • FIG. 2 OA and B a 17th embodiment according to the present invention will be described.
  • a ferroelectric memory device as an example and a ferroelectric memory element used in the ferroelectric memory device will be described.
  • FIG. 2OA shows the configuration of a ferroelectric memory element (unit memory cell) used in the ferroelectric memory device of this embodiment.
  • FIG. 20B shows a ferroelectric memory device configured using this ferroelectric memory element.
  • two unit memory cells are used for ease of explanation.
  • the present invention is not limited to this, and a matrix structure in which many memory cells are arranged is used. Of course, it is preferable.
  • the ferroelectric memory element (unit memory cell) shown in FIG. 20A is the same as the ferroelectric memory element shown in FIG. 13B, and detailed description is omitted here. .
  • the ferroelectric memory device shown in FIG. 20B has two ferroelectric memory elements 81, 1 (hereinafter, referred to as cells 1 and 2) and a write-in device for selecting a cell into which data is to be written.
  • Address decoder 101 bipolar write power supply for writing multi-valued polarization during writing (voltage magnitude varies according to information to be written) 103, read for selecting cell from which data is read It comprises an address decoder 1-2, a read current detection circuit 106 for detecting read current and discriminating information, and a read / write (RZW) control circuit 105.
  • the transistor switch 82 (SW1) or 92 When writing is not being performed, the transistor switch 82 (SW1) or 92 is always connected to the cell transistor 84 (W-SW1) or 94 via the inverter 83 or 92.
  • the grounded part is grounded (when storing and reading out the memory).
  • the read address decoder 102 turns on the transistor 86 (R-SW2) or 96, and the cell is connected to the read power supply 104. At the same time, the transistor 85 (W-SW2) or 95 is turned off (off) by the RZW control circuit 105.
  • the current flowing from the read power supply 104 to the cell 1 or 2 has a value determined by the polarization state of the cell, and this current flows into the read current detection circuit 106.
  • the characteristics of the voltage-to-current conversion element of the cell are the characteristics shown in FIG. 15B, and the multiple hysteresis characteristics are those shown in FIGS. 14A to 14H.
  • Figure 14 A, shown in B, memory voltage polarization state P j of the polarization state of the state 1 is the V M in FIG. 1 5 B, the polarization state P 2 in the state 3 shown FIG. 14 E, the F the Note Li voltage at the time of FIG. 1 5 B - a V M.
  • it shows 0 V in a state equivalent to states 2 and 4 shown in Figs. 14C and 14D and Figs. 14G and 14H.
  • the memory cells M11 to M33 shown in FIG. 21A correspond to the ferroelectric memory element shown in FIG. 17 of the fourteenth embodiment described above. Further, in this embodiment, the arrangement of three rows and three columns is adopted in order to make the explanation easy to understand, but the present invention is not limited to this.
  • memory cells M11 to M33 are arranged in a matrix, and switches S1 to S3 are provided for each row.
  • the current output from the memory element is 0 A.
  • the nonvolatile memory voltage 0.8 V is stored in the dielectric capacitor 42, If the current of 500 / iA and 10.8 V are stored, the current of 500 A is output from the output terminal 51 (see FIG. 17).
  • an n-dimensional matrix operation circuit By expanding this to n dimensions, an n-dimensional matrix operation circuit can be constructed. In addition, as can be seen from such an operation, since it is a parallel operation unit, a very high-speed product-sum operation unit can be realized.
  • a ferroelectric material that has multi-hysteresis characteristics with at least three or more stable polarization values and stores multi-valued voltages associated with the multi-hysteresis characteristics as information
  • a ferroelectric capacitor formed between materials
  • a dielectric capacitor connected in series to the ferroelectric capacitor
  • a voltage-current conversion element for reading multi-valued voltage information associated with the multiple hysteresis characteristics stored in the ferroelectric capacitor
  • the ferroelectric memory device of (1) Since the ferroelectric memory device of (1) has three or more stable polarization values, three or more pieces of voltage information stored when the polarization state changes can be obtained.
  • the information that can be stored in a normal ferroelectric memory device is binary, but the ferroelectric memory device of the present invention has a multi-layered structure.
  • a ferroelectric material having a steeresis characteristic three or more values can be stored.
  • a voltage-to-current conversion element instead of an ON-OFF switch as the readout element, multi-valued storage and multi-valued read-out are possible.
  • a dielectric capacitor connected in series with the ferroelectric capacitor
  • a ferroelectric element capable of multi-value storage comprising: a resistance element connected in parallel to the ferroelectric capacitor; Body memory device.
  • the voltage-current conversion element according to (2) is connected to a continuous portion between the ferroelectric capacitor and the dielectric capacitor.
  • ferroelectric memory devices of (2) and (3) have three or more stable polarization values, three or more pieces of voltage information corresponding to the polarization state can be obtained. Since voltage information can be directly stored, long-term memory is possible, and multi-value storage of three or more values is possible.
  • the voltage-current conversion element for reading multi-valued voltage information is an element whose current is controlled with respect to a positive voltage. And an element whose current is controlled with respect to a negative voltage.
  • the ferroelectric memory device is a storage element capable of storing and reading out multi-valued information of three or more values. Since conversion is possible, voltage information corresponding to the polarization state can be stored for a long period of time in both polarities, and multi-value reading of the information voltage is possible.
  • the voltage-current conversion element described in the above (3) or (4) is constituted by a MOS type transistor.
  • the ferroelectric memory device according to the present invention of (5) is realized as a conventional multi-valued memory S i device (not realized by a device).
  • a ferroelectric memory device can be created in monolithic on a substrate.
  • the dielectric capacitor, a gate capacitance of M 0 ST r, the resistance element is made of polycrystalline silicon.
  • the ferroelectric memory device according to the present invention (6) uses a resistive element technology using a top-down silicon to provide an unprecedented multi-value storage memory element.
  • the structure for realizing such a ferroelectric memory device is simplified, and a separate dielectric capacitor is manufactured by using the gate capacitance of the MOS transistor as a dielectric capacitor.
  • the resistive element is made of polysilicon, which is usually used in the Si process, to prevent the process from becoming complicated.
  • (7) In the ferroelectric memory device described in (1) or (2) above, a plurality of ferroelectric memory elements are arranged, a desired memory element is selected, and writing / reading is performed. Have means to do.
  • Such a ferroelectric memory device of (7) has characteristics of multi-value storage and nonvolatile storage by selecting a desired ferroelectric memory element and performing writing and reading. This is a ferroelectric memory device capable of non-destructive and multi-value storage.
  • a plurality of output terminals of the memory element described in (3) or (4) above are shared, and the vector information input from the input terminal and the vector information stored in the memory element in advance are used.
  • the matrix operation with the torque information is processed in parallel, and the multiplication result is output from the output terminal.
  • Such a ferroelectric memory device of (8) can perform a vector operation of information having three or more values and performs a high-speed matrix operation.
  • a ferroelectric memory element having a multiple hysteresis characteristic having at least three or more stable polarization values is provided.
  • Ferroelectric used A memory device can be provided.
  • the ferroelectric memory device of the present invention has a ferroelectric memory having multiple hysteresis characteristics in the storage medium. by using the body, rests may multilevel storage of three or more values at least 0
  • the ferroelectric memory device according to the present invention as described above can be widely used as a nonvolatile memory.

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Abstract

Un condensateur ferro-électrique, utilisé dans une section de cellule de mémoire d'un dispositif à mémoire ferro-électrique, comprend une région de polarisation P1 d'une épaisseur de couche (d) et de surface S1, ainsi qu'une région de polarisation P2 qui est une composante, en direction de P1, de polarisation oblique, P2 ne présentant qu'une section d'électrode et une surface S2. Les caractéristiques d'hystérésis conbinées des polarisations P1 et P2 englobent une caractéristique d'hystérésis torsadée. Quand l'état de mémoire de cette dernière caractéristique est 'O' et '1', une lecture non destructrive est possible par un phénomène de commutation inverse. Un dispositif à mémoire ferro-électrique, constituant une variante de l'invention, comprend un condensateur ferro-électrique (11) qui présente une caractéristique d'hystérésis multiplex à trois valeurs de polarisation stables au moins attribuées à la caractéristique d'hystérésis torsadée. On l'obtient en plaçant un matériau ferro-électrique, qui enregistre des tensions multi-niveaux résultant de cette caractéristique d'hystérésis multiplex sous forme d'informations, entre des matériaux d'électrode. Ce dispositif comprend également un condensateur diélectique (12) connecté en série au condensateur (11), et un élément de conversion tension-courant (16) qui lit les informations multi-niveaux enregistrées dans ce condensateur (11).
PCT/JP1995/000533 1994-03-29 1995-03-23 Dispositif a memoire ferro-electrique WO1995026570A1 (fr)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP6/58397 1994-03-29
JP6058397A JPH1140759A (ja) 1994-03-29 1994-03-29 強誘電体メモリ装置
JP6/222896 1994-09-19
JP6222896A JPH1139860A (ja) 1994-09-19 1994-09-19 強誘電体メモリ装置

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Cited By (10)

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EP0982779A2 (fr) * 1998-08-28 2000-03-01 Semiconductor Technology Academic Research Center Structure de mémoire dans une mémoire ferro-électrique non-volatile et procédé de lecture
US6327172B1 (en) 1999-05-19 2001-12-04 Semiconductor Technology Academic Research Center Ferroelectric non-volatile memory device
EP1265254A2 (fr) * 2001-06-06 2002-12-11 Matsushita Electric Industrial Co., Ltd. Dispositif à semi-conducteurs
WO2003001599A1 (fr) * 2001-06-22 2003-01-03 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur et son procede de commande
JP2007208280A (ja) * 2007-03-19 2007-08-16 Toshiba Corp 半導体記憶装置
CN100345075C (zh) * 2001-12-20 2007-10-24 松下电器产业株式会社 电位发生电路、电位发生装置和用它的半导体装置和其驱动方法
US7465980B2 (en) 2004-09-10 2008-12-16 Fujitsu Limited Ferroelectric memory, multivalent data recording method and multivalent data reading method
WO2009107489A1 (fr) * 2008-02-29 2009-09-03 ソニー株式会社 Élément à capacité variable, procédé d'ajustement d'élément à capacité variable, dispositif à capacité variable et appareil électronique
WO2011156525A2 (fr) * 2010-06-09 2011-12-15 Radiant Technologies, Inc. Mémoires ferroélectriques basées sur des réseaux de bits de mémoire autonomes
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JPH04171978A (ja) * 1990-11-06 1992-06-19 Olympus Optical Co Ltd メモリ素子
JPH04314361A (ja) * 1991-04-12 1992-11-05 Olympus Optical Co Ltd メモリ装置
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EP0982779A2 (fr) * 1998-08-28 2000-03-01 Semiconductor Technology Academic Research Center Structure de mémoire dans une mémoire ferro-électrique non-volatile et procédé de lecture
EP0982779A3 (fr) * 1998-08-28 2000-05-17 Semiconductor Technology Academic Research Center Structure de mémoire dans une mémoire ferro-électrique non-volatile et procédé de lecture
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US6847071B2 (en) 2001-06-06 2005-01-25 Matsushita Electric Industrial Co., Ltd. Semiconductor device
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WO2003001599A1 (fr) * 2001-06-22 2003-01-03 Matsushita Electric Industrial Co., Ltd. Dispositif semi-conducteur et son procede de commande
CN100345075C (zh) * 2001-12-20 2007-10-24 松下电器产业株式会社 电位发生电路、电位发生装置和用它的半导体装置和其驱动方法
US7465980B2 (en) 2004-09-10 2008-12-16 Fujitsu Limited Ferroelectric memory, multivalent data recording method and multivalent data reading method
JP2007208280A (ja) * 2007-03-19 2007-08-16 Toshiba Corp 半導体記憶装置
WO2009107489A1 (fr) * 2008-02-29 2009-09-03 ソニー株式会社 Élément à capacité variable, procédé d'ajustement d'élément à capacité variable, dispositif à capacité variable et appareil électronique
JP2009212168A (ja) * 2008-02-29 2009-09-17 Sony Corp 可変容量素子、可変容量素子の調整方法、可変容量デバイス、及び電子機器
WO2011156525A2 (fr) * 2010-06-09 2011-12-15 Radiant Technologies, Inc. Mémoires ferroélectriques basées sur des réseaux de bits de mémoire autonomes
WO2011156525A3 (fr) * 2010-06-09 2012-04-12 Radiant Technologies, Inc. Mémoires ferroélectriques basées sur des réseaux de bits de mémoire autonomes
US8310856B2 (en) 2010-06-09 2012-11-13 Radiant Technology Ferroelectric memories based on arrays of autonomous memory bits
US10510862B2 (en) 2018-03-23 2019-12-17 Toshiba Memory Corporation Semiconductor memory device
US11380773B2 (en) 2018-03-23 2022-07-05 Kioxia Corporation Ferroelectric memory device

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