Classifications

• • C—CHEMISTRY; METALLURGY
  • C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
  • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
  • C23C28/00—Coating for obtaining at least two superposed coatings either by methods not provided for in a single one of groups C23C2/00 - C23C26/00 or by combinations of methods provided for in subclasses C23C and C25C or C25D
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/02—Details
  • H01L31/0224—Electrodes
  • H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
  • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
• • H—ELECTRICITY
  • H01—ELECTRIC ELEMENTS
  • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
  • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
  • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
  • Y02E10/00—Energy generation through renewable energy sources
  • Y02E10/50—Photovoltaic [PV] energy
  • Y02E10/547—Monocrystalline silicon PV cells
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
  • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
  • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

• This invention pertains to the manufacture of photovoltaic cells and more particularly to an improved low-cost method of fabricating poly- crystalline silicon solar cells wherein the damaged surface layer generated during hydrogen passivation is used as a plating mask for the final plating steps.
• a common method of fabricating silicon solar cells has included the steps of forming a PN junction by diffusing a suitable dopant into the front side of a silicon wafer or ribbon, etching a grid effectrode pattern in a protective dielectric masking layer formed on that front surface, depositing a nickel plating on all silicon exposed by the etching, overplating the nickel with copper and tin, removing the remainder of the dielectric masking layer from the front surface, and providing an anti-reflection coating on the newly exposed portions of the front surface.
• a process which, in a preferred embodiment as applied to the manufacture of silicon solar cells involves, inter alia, the following steps: (1) forming a thin grid electrode pattern of nickel (or similar material) on the front surface of a shallow-junction silicon rib ⁇ bon, (2) hydrogen passivating the junction side of the cell, (3) sintering the nickel to form in part a nickel silicide, (4) plating additional metal(s) onto the metal-covered portions of the cell, and (5) anti- reflection coating the exposed surface of the silicon. Thereafter, the silicon may be further processed, e.g. to prepare it for connection to electrical circuits.
• the heating of the sample during passivation supplies energy for the nickel sintering step.
• any plating mask initially used to define the front surface electrode grid pattern can be removed after an initial layer of metal has been plated onto the substrate. Passivation may now be accomplished upon an exposed base silicon layer, the passivation not only improving the electrical perfor ⁇ mance of the cell but also, in altering the surface layer, serving as a secondary plating mask for sub ⁇ sequent immersion plating steps.
• passi ⁇ vation of the exposed silicon base may be accomplished prior to the application of base metals without the requirement of an additional masking step prior to immersion plating metallization. Further, applicant has also found that passivation can occur through thin layers of metals such as nickel. Thus, the silicon and nickel silicide under the initial thin nickel plating of a front electrode may be passivated.
• the preferred embo ⁇ diment of the invention relates to the production of solar cells from EFG grown P-type silicon ribbon.
• a partially finished cell 1 has a substrate 2, preferably formed from a P-type conductivity silicon ribbon, one side (hereafter the "front side") of which has been provided with a rela ⁇ tively shallow junction 4 (i.e., a junction of between about 3,000 and about 7,000 Angstrom units deep), an N-type conductivity region 6, and a mask 8.
• Mask 8 is of a material (e.g., a dielectric) to which metals, such as nickel, will only poorly adhere, and is con ⁇ figured to expose portions of the front surface of substrate 2 in a pattern of a multi-fingered grid electrode (e.g., an electrode having the form illustrated in U.S. Patent 3,686,036).
• the other side (hereafter the "rear side") of the substrate is pre ⁇ ferably provided with a layer 10 of .aluminum alloyed to the substrate and a P + region 12.
• the P + region 12 preferably has a depth of from about 1 to about 5 microns.
• Partially finished cell 1 may be fabricated by any of a number of means well known in the art.
• junction 4 and region 6 may be formed in a P-type silicon substrate 2 by the diffusion of phosphorus, and mask 8 may be formed on the front sur ⁇ face thereof by photolithography or printing.
• Layer 10 and P + region 12 may be formed by coating the rear side of the substrate with a layer of an aluminum past comprising aluminum powder in a volatile organic vehicle, such as terpineol, that can be removed by evaporation, and then heating the substrate to remove any volatile or pyrolyzable organic components of the paste and to alloy the aluminum to the substrate and form the P + region.
• a volatile organic vehicle such as terpineol
• other forms of substrate, junction, and rear electrode, and other methods of fabrication may equally well be employed to provide partially finished cell 1.
• both sides of the substrate are first plated with nickel, an adhesive deposition of nickel forming a nickel layer 14 on the back side of the piece over the entire area of aluminum layer 10, while the adhesive deposi ⁇ tion of nickel on the front side forms a layer 16 directly on the surface of substrate 2 only on those areas exposed through mask 8.
• Plating of the nickel layers 14 and 16 may be done in various ways. Preferably it is accomplished in accordance with a known electroless or immersion plating process, e.g., an immersion plating process like or similar to the one described in U.S. Patent No. 4,321,283 of Kirit Patel, et al.
• electroless plating designates plating from a bath that contains a reducing agent without the use of an externally applied electric field
• immersion plating means a pro ⁇ cess wherein an object is plated with a metal without the use of an externally applied electric field by immersing it in a plating bath that does not contain a reducing agent, and the plating involves a dis ⁇ placement reaction.
• the cleaned silicon substrate surface is pre-activated with a suitable agent.
• a suitable agent e.g. platinum chloride, stannous chloride-palladium chlroide, or other well known activators may be used, as described, for instance, in U.S. Patent No. 3,489,603.
• both sides of the silicon ribbon are coated with a layer of nickel, preferably by immersion plating the ribbon in an aqueous bath as described in said U.S. Patent No. 4321283, or an aqueous bath of nickel sulfa ate and ammonium fluoride at a pH of about 2.9 and at approximately room temperature for a period of about 2 to 6 minutes.
• mask 8 is stripped from substrate ⁇ 2. Depending on the nature of the mask, this may be accomplished in any of a number of well-known ways, as, for instance, by the use of a buffered etch. As a result of the mask removal, the front surface of substrate 2 is exposed through a grid pattern formed of nickel layer 16. Next, the cell is hydrogen passivated. A preferred method is to expose the front surface of substrate 2 (and nickel layer 16) to the hydrogen ion beam of a Kaufman-type (broad beam) ion source situated about 15 cm from the substrate.
• a Kaufman-type (broad beam) ion source situated about 15 cm from the substrate.
• This ion source is preferably operated at a pressure of between about 20 and 50 millitorr (of hydrogen) , with a hydro ⁇ gen flow rate on the order of about 25 to 40 s.c.c. per minute, with a potential of about 1700 volts d.c. between source and substrate, and with a beam current of between about 1 and 3 milliam ⁇ ere/cm.2 at the substrate.
• An exposure time of between about 1 and about 4 minutes has been found adequate both to minimize the minority carrier recombination losses typically experienced with EFG-type silicon cells (providing a passivation zone some 20 to 80 microns deep, or about 100 times as deep as junction 4) while simultaneously providing an altered surface layer 18 approximately 200 Angstrom units deep on the exposed portions of substrate 2. It has also been found that using a mechanical shutter to pulse the ion beam on and off with about a 50% duty cycle results in a minimal temperature rise of the substrate during passivation.
• altered surface layer 18 is not known. 'However, it is believed to be a damaged zone wherein the crystal structure has been somewhat disrupted, the silicon in part forming SiH or SiH2 with hydrogen from the ion beam, yet wherein the material is possibly amorphous. A small amount of carbon or one or more hydrocarbons within the vacuum system may be necessary for the formation of the desired altered surface layer.
• the Kaufman ion source used was equipped with a graphite mounting stage about 5 inches (c. 13 cm) in diameter on which the substrates, typically 2 by 4 inches (5 by 10 cm) on a side, were centrally located.
• the substrate is heated in an inert or a nitrogen atmosphere to a temperature and for a time sufficient to sinter the nickel layers and cause the nickel layer 16 on the front side of the substrate to react with the adjacent silicon to form a nickel sili ⁇ cide ohmic contact.
• the substrate is preferably heated to a temperature of about 300'Q for between about 15 and about 40 minutes. This pro ⁇ vides a nickel silicide layer 20 with a depth of about 300 Angstrom units at the interface between nickel layer 16 and substrate 2.
• the nickel layer 14 on the rear side forms an alloy with aluminum layer 10.
• the temperature of this sintering step should not greatly exceed 300'C, as higher temperatures lead to excessive penetration of nickel layer 16 into the silicon.
• This heat treatment if carried out in forming gas (95% nitrogen and 5% hydrogen) also appears to drive off hydrogen loosely bound to nickel layer 16, thereby enhancing subsequent plating adherence.
• the nickel of layers 14 and 16 is subjected to etching with hot dilute nitric acid, followed by ultrasonic cleaning, to remove excess nickel from both sides of the substrate.
• the nickel etch not only removes excess nickel but also removes some of the nickel - aluminum alloy formed on the rear side of the substrate during the sintering step.
• layer 14 is characte ized by an nickel - aluminum alloy layer overlying aluminum electrode layer 10 while layer 16 is stripped to expose nickel silicide layer 20 corresponding to the preselected electrode grid pattern.
• nickel silicide layer 20 and the nickel - aluminum alloy layer 14 are respectively further metallized with one or more layers 22 and 24 to provide suitable contacts.
• altered surface layer 18 of substrate 2 acts as a plating mask to prevent metal fcom adhering to the surface of the substrate between the pattern of the already attached nickel silicide layer 20.
• this additional metallization involves application of a second layer of nickel to layers 14 and 20.
• the additional nickel layers are applied by immersion plating in the manner described above in connection with formation of nickel layers 14 and 16, since with immersion plating nickel will plate onto the layers 14 and 16 but not onto the altered surface 18.
• one or more layers of copper are applied (by immersion plating and/or electroplating, by techniques well known in the art) to the exposed nickel on bot sides of the substrate so as to bond to the nickel layers and thereby protect them against oxidation and to insure a high conductivity.
• No masking of the altered layer 18 is required for the copper plating since the copper will not adhe.re to the altered layer.
• the device may be subjected to other treatments for known purposes, e.g., layers of tin and solder may be applied successively over the previously applied metal layers.
• antirreflection coating 26 is applied to the front surface of the cell. This latter step may be accomplished by any of a number of known methods, such as by chemical vapor deposition or of, for instance, Ti ⁇ 2- Alternatively, anti- reflection coating 26 may be formed by the plasma deposition of silicon nitride.
• the preferred method of prac ⁇ ticing the present invention comprises performing the individual steps set forth hereinabove in the pre ⁇ ferred mode described in detail for each step and in the sequence set forth.
• the preferred method of the present invention comprises performing the individual preferred steps detailed supra, these steps being performed in the sequence just indicated.
• the process described above has a number of other advantages. Firstly, in utilizing the substrate's altered surface layer generated during hydrogen passivation as a mask for subsequent plating by an immersion plating method, e.g., nickel plating as above-described, the method permits passivation of an exposed substrate prior to such later metallization. This allows passivation of a clean substrate (rather than passivation " through a plating mask layer), avoids "soft" or shorted cells (resulting from base metal igration during passivation) , and economizes the steps between passivation and subsequent metallization by immersion plating, as no further masking step is required.
• an immersion plating method e.g., nickel plating as above-described
• the hydrogen passi- vated area also serves as a mask to reject deposition of copper by immersion plating or electroplating. Additionally, by passivating through a thin layer of front electrode material, the substrate beneath the front electrodes may be passivated as well, provided the initial nickel layer is no more than about 750 Angstrom units thick. It will be appreciated also that the process of the present invention incorporates the passivation at a stage of cell fabrication where subsequent treatment of the cell will not adversely affect the effects of passivation.
• the nickel sintering step is performed following passivation, it might also be performed just prior to passivation.
• short ion beam exposures with or without thermal control of the substrate by an appropriate heat sink may be de ⁇ ireable to insure against migration of the nickel silicide to the junction.
• Such control also produces ⁇ 2Si, rather than the other suicides (NiSi or NiSi2) , thereby incorporating less silicon per molecule of the sili- cide and insuring against complete penetration of the N + region by the silicide.
• a baking step following passivation may be required to drive the losely bound hydrogen out of the nickel prior to further processing.
• heating of the cell during passivation can be used to perform at least part of the nickel sintering step.
• the method of the present invention makes use of the altere.d layer formed by hydrogen passivation to mask subsequent immersion nickel plating except on earlier plated nic .el
• the method may be used with other metals than nickel.
• the initial layer of the front surface electrodes on a shallow junction silicon device may be deposited by plating, in. various ways known to persons skilled in the art, any of a number of low reactivity materials capable of forming (preferably at a low temperature) an ohmic contact and serving as a barrier to the diffusion of copper or any other base metal deposited at a later stage.
• Suitable metals for use with copper include palladium, platinum, cobalt, and rhodium, as well as nickel. While all of these materials form suicides, a silicide layer is not essential. It is important, however, that the initial metal layer adhere properly, serve as an ohmic contact, and act as a barrier to the migration of any metal deposited later, as well as not significantly migrating to the junction itself.
• the process provided by this invention is not limited to the production of solar cells from EFG substrates.
• cast polycrystal line substrates, epitaxial silicon on metallurgical grade silicon or fine grade polysilicon layers formed by chemical or physical vapor deposition can be used to form relatively high efficiency solar cells according to the present invention.
• the process is applicable to single crystal silicon. Then, too, the process may be practiced with N-type as well as P-type material.

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• 1984
  • 1984-12-14 AU AU38886/85A patent/AU574761B2/en not_active Ceased
  • 1984-12-14 EP EP19850900535 patent/EP0167589A4/en not_active Withdrawn
  • 1984-12-14 DE DE19843490612 patent/DE3490612T1/de not_active Withdrawn
  • 1984-12-14 GB GB08515901A patent/GB2162996B/en not_active Expired
  • 1984-12-14 NL NL8420338A patent/NL8420338A/nl unknown
  • 1984-12-14 JP JP85500715A patent/JPS61500756A/ja active Pending
  • 1984-12-14 WO PCT/US1984/002065 patent/WO1985002939A1/en not_active Application Discontinuation
• 1985
  • 1985-08-16 SE SE8503833A patent/SE456624B/sv not_active IP Right Cessation
  • 1985-12-14 CH CH3598/85A patent/CH669476A5/de not_active IP Right Cessation

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