US9589609B2 - Bit-line voltage boosting methods for static RAM and semiconductor device including static RAM - Google Patents

Bit-line voltage boosting methods for static RAM and semiconductor device including static RAM Download PDF

Info

Publication number
US9589609B2
US9589609B2 US14/839,357 US201514839357A US9589609B2 US 9589609 B2 US9589609 B2 US 9589609B2 US 201514839357 A US201514839357 A US 201514839357A US 9589609 B2 US9589609 B2 US 9589609B2
Authority
US
United States
Prior art keywords
potential
bit line
pairs
write driver
column switch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US14/839,357
Other languages
English (en)
Other versions
US20160093370A1 (en
Inventor
Wenhao Wu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Socionext Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Socionext Inc filed Critical Socionext Inc
Assigned to SOCIONEXT INC. reassignment SOCIONEXT INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WU, WENHAO
Publication of US20160093370A1 publication Critical patent/US20160093370A1/en
Application granted granted Critical
Publication of US9589609B2 publication Critical patent/US9589609B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits

Definitions

  • the present invention relates to a static RAM (SRAM: Static Random Access Memory) and a semiconductor device including a static RAM.
  • SRAM Static Random Access Memory
  • a write driver is generally formed by an inverter connected between a high potential power source line and a reference potential power source line.
  • the reference potential power source line of the inverter forming the write driver is set as an independent low-side drive line, the low-side drive line is temporarily set to a negative potential at the time of the write operation, and in other cases, the low-side drive line is set to the same potential as that of the reference potential power source line.
  • a capacitive element and a boost control transistor are provided.
  • One terminal of the capacitive element is connected to the low-side drive line.
  • a boost signal is applied to the other terminal of the capacitive element.
  • the boost control transistor is connected between the low-side drive line and the reference potential power source line.
  • the boost signal is applied to a gate of the boost control transistor. Normally, the boost signal is at the high level and the boost control transistor turns on, the potential of the low-side drive line becomes a potential VSS of the reference potential power source line, and the capacitive element is charged to the potential difference between the potential of the boost signal and the VSS.
  • the boost control transistor turns off and the potential of the low-side drive line changes to a negative potential by the charges charged in the capacitive element.
  • the low-side drive line is connected to a bit line, which is driven to the low side, of a plurality of bit line pairs (column) via a transistor, etc., forming an inverter of the write driver, and the bit line which is driven to the low side is driven to a negative potential.
  • the potential difference caused by the boosting differs depending on the variations in the operation voltage, the process conditions, etc.
  • the low-side drive line changes to a large negative potential.
  • the potential of the bit line of the selected bit line pair, which is driven to the low side also changes to a large negative potential, there occurs a case where a voltage applied to a transistor of the non-selected column switch exceeds a threshold voltage of the transistor and the non-selected column switch turns on, and therefore, there has been a problem that data is written erroneously to the non-selected memory cell.
  • Patent Document 1 discloses a clamp circuit that clamps the potential of the low-side drive line.
  • Patent Document 2 discloses a configuration for controlling a potential difference that is boosted by using a variable capacitor as a capacitive element.
  • Patent Document 1 Japanese Laid Open Patent Document No. 2009-151847
  • Patent Document 2 Japanese Laid Open Patent Document No. 2010-257554
  • a static RAM includes: a plurality of word lines; a plurality of bit line pairs; a plurality of memory cells provided at intersections of the plurality of bit line pairs and the plurality of word lines; a write driver connected between a high potential power source line, whose potential is higher than a reference potential, and a drive line; a column switch having transistor pairs which connect one of the plurality of bit line pairs, which is selected, to the write driver; and a boost circuit which boosts the drive line of the write driver to a negative potential, which is a potential lower than the reference potential, at a time of writing of the memory cell, wherein a well of the transistor pairs of the column switch is connected to the drive line.
  • FIG. 1 is a diagram illustrating a configuration of the portions of a memory array, column switches, and a write driver of an SRAM;
  • FIG. 2 is a time chart illustrating the write operation of the SRAM in FIG. 1 ;
  • FIG. 3 is a diagram illustrating the general configuration of the SRAM of the embodiment
  • FIG. 4 is a diagram illustrating a configuration of the portions of a memory array, column switches, and a write driver of an SRAM of an embodiment
  • FIG. 5 is a time chart illustrating the write operation of the SRAM of the embodiment.
  • FIG. 1 is a diagram illustrating a configuration of the portions of a memory array, column switches, and a write driver of an SRAM.
  • a 2 ⁇ 2 memory array is illustrated as an example, but in fact, a large number of memory cells are arranged.
  • the SRAM has two word lines WL 0 and WL 1 , two bit line pairs, i.e., a pair of bit lines BL 0 and BLX 0 and a pair of bit lines BL 1 and BLX 1 , and four memory cells Cell 1 to Cell 4 arranged in correspondence to the intersections of the two word lines and the two bit line pairs.
  • the memory cell has two inverters whose inputs and outputs are connected alternately and two transfer transistors that connect the connection nodes of the inverters to the bit line pairs.
  • the write driver has a first inverter INV that drives one of the bit line pair, i.e., BL 0 , and one of the other bit line pair, i.e., BL 1 , and a second inverter INVX that drives the other of the bit line pair, i.e., BLX 0 , and the other of the other bit line pair, i.e., BLX 1 .
  • the first and second inverters are connected between a high potential power source line VDD and a drive power source line NVS.
  • the potential of the high potential power source line VDD is represented by VDD
  • the potential of the reference potential power source line VSS to be described later, is represented by VSS
  • the potential of the drive power source line NVS is represented by NVS.
  • the PNMOS transistor when a write enable signal WE is at the low (L) level, the PNMOS transistor turns on and turns write signal lines WD and WDX to the high (H) level.
  • the write enable signal WE is at the H level
  • one of the transistors of the first and second inverters turns on and the other turns off.
  • the WIN is at the L level
  • the PMOS transistor turns on and the NMOS transistor turns off
  • the first inverter the PMOS transistor turns off and the NMOS transistor turns on. Due to this, the WDX turns to the H level (VDD) and the WD turns to the L level (NVS).
  • the PMOS transistor turns off and the NMOS transistor turns on
  • the WDX turns to the L level (NVS) and the WD turns to the H level (VDD).
  • bit line pair i.e., BL 0
  • bit line pair i.e., BL 1
  • the other of the bit line pair i.e., BLX 0
  • the other of the other bit line pair i.e., BLX 1
  • column switches t 3 and t 4 respectively.
  • a column selection signal COL 0 is applied
  • a column selection signal COL 1 is applied to the gates of the column switches t 2 and t 4 .
  • the configuration of the SRAM is widely known, and therefore, explanation is omitted.
  • a capacitive element CAP one terminal of which is connected to the NVS, and to the other terminal of which, a boost signal BST is applied, and an NMOS transistor (boost control transistor) t 0 that is connected between the NVS and VSS, and to the gate of which, the boost signal BST is applied are provided.
  • the boost signal BST is at the high level, the t 0 turns on, the potential of the NVS and that of the VSS become the same, and the capacitive element CAP is changed to the potential difference between the boost signal BST and VSS.
  • the boost signal changes to the low level (e.g., VSS)
  • the t 0 turns off and by the voltage charged across the capacitive element CAP
  • the potential of the NVS changes to a negative potential.
  • the NVS is connected to one of the WD and WDX, and one of the WD and WDX is connected to one of the bit line pair, respectively, which is selected, via the selected column switches. Due to this, one bit line of the selected bit line pair, which is driven to the low side, changes to a negative potential, and the negative potential is applied to the memory cell via the transfer gate of the selected memory cell and it is made possible to perform writing stably.
  • FIG. 2 is a time chart illustrating the write operation of the SRAM in FIG. 1 .
  • the WIN changes to L
  • the COL 0 and WL 0 change to H
  • the BL 0 changes to L.
  • the BST changes from H to L
  • the boost functions and the BL 0 changes to a negative potential.
  • the BLX 0 maintains H.
  • a node C 1 of the Cell 1 changes to L in accordance with the change of the BL 0 and further changes to a negative potential.
  • Another node CX 1 of the Cell 1 changes to H in accordance with the change of BLX 0 . Due to this, L is written to the Cell 1 .
  • a transfer gate t 5 of the Cell 3 turns off because the WL 1 is at L and the column switches t 2 and t 4 are off because the COL 1 is at L.
  • FIG. 2 illustrates a case in which although a node C 2 is at the H level and CX 2 is at the L level in the Cell 2 , the C 2 changes to the L and the CX 2 changes to H.
  • the low-side drive line is boosted to a negative potential in order to secure the stability at the time of writing.
  • data may be erroneously written since an over-boost occurs depending on the manufacturing variations and a transistor of the non-selected column switch turns on.
  • a semiconductor device in the present embodiment is an integrated circuit including an SRAM and a processing circuit carrying out predetermined processes based on the data stored in the SRAM.
  • FIG. 3 is a diagram illustrating the general configuration of the SRAM of the embodiment.
  • the SRAM has a memory array 11 , a portion 12 including a write driver, a sense amplifier, and a column switch, an input/output unit 13 , a decoder 14 , and a timing and pre-decoder unit (timing & pre-decoder) 15 .
  • the memory array 11 includes a plurality of word lines, a plurality of bit line pairs, and a plurality of memory cells arranged in correspondence to the intersections of the plurality of word lines and the plurality of bit line pairs.
  • the input/output unit ( 10 ) 13 receives write data from the outside and generates the WIN, and generates read data from an output of the sense amplifier and outputs the read data to the outside.
  • the decoder 14 decodes a pre-coded address signal and generates a word line selection signal WL, decodes a pre-coded address signal and generates a column selection signal, and further, generates the write enable signal WE, the boost signal BST, etc.
  • the timing and pre-decoder unit 15 performs total timing control and at the same times, pre-decodes an address signal.
  • the general configuration of the SRAM in FIG. 3 is widely known, and therefore, explanation is omitted.
  • FIG. 4 is a diagram illustrating a configuration of the portions of a memory array, column switches, and a write driver of an SRAM of the embodiment.
  • a 2 ⁇ 2 memory array is illustrated as an example, as in FIG. 1 , but in fact, a number of memory cells are arranged.
  • the SRAM of the embodiment has a configuration similar to that of the SRAM in FIG. 1 . However, it is different that VSS is applied to a well on which the column switch t 1 -t 4 in a same way as other NMOS transistors in FIG. 1 but a boosted voltage NVS is applied thereto in the embodiment. Due to this, NMOS transistors forming the column switches t 1 -t 4 are formed on an independent well (or independent wells) which is separated from those on which other NMOS transistors (for example, NMOS transistors forming word line drivers) are formed. NVS is applied to the well on which the NMOS transistors forming the column switches t 1 -t 4 are formed, and VSS is applied to wells on which other NMOS transistors are formed.
  • the transistors of the column switch are formed on an independent well which is separated from wells on which other transistors are formed.
  • VSS is applied to the well on which other transistors are formed, but the boosted voltage NVS is applied to the well on which the transistors of the column switch are formed. Because of this, when VDD is 1.2V, the reverse bias of the transistors of the non-selected column switch become deeper, the threshold voltage of the transistors changes from 300 mV to 450 mV which is larger than an absolute value of NVS ( ⁇ 400 mV). Accordingly, it is possible to prevent an erroneous write to the non-selected cells.
  • FIG. 5 is a time chart illustrating the write operation of the SRAM of the embodiment.
  • the waveforms of WE, BST, BL 0 , C 1 and CX 1 are same as those of FIG. 2 , and the explanations regarding the write operation to Cell 1 is omitted.
  • VSS the L level
  • the transistor t 2 of the column switch maintains the off state since NVS is applied to the well of the t 2 of the column switch and the reverse bias is deep. Accordingly, BL 1 and BLX 1 of the bit line pair are maintained at states in correspondence to data stored in Cell 2 . and the relationship of the nodes C 2 and CX 2 of Cell 2 does not change.
  • the SRAM of the embodiment can prevent an erroneous write to cells of the non-selected columns by a simple configuration that a well of transistors of the column switch is separated and the boosted voltage NVS is applied to the well.
  • a row decoder and a column decoder are arranged at horizontal sides of a memory cell array of a rectangular shape including a plurality of word lines, a plurality of bit line pairs and a plurality of memory cells.
  • a read circuit and a write circuit are arranged at vertical sides of the memory cell array.
  • the plurality of column switches are arranged in a rectangular area adjoining to the memory cell array. Accordingly, it is desired that the well(s) of transistors of the plurality of column switches are separated from wells of other transistors and connected to the drive power source line NVS of the first inverter INV and the second inverted INVX.
  • the well of the column switch pairs (t 1 and t 3 ; t 2 and t 4 ) in correspondence to the bit line pairs may be respectively separated, and the boosted voltage NVS is applied to each of the wells only when the corresponding bit line pair is selected, namely, the corresponding column switch pair turns on. In other state in which the corresponding bit line pair is not selected, VSS is applied to the corresponding well. Due to this, it is possible to turn on the selected column switch more correctly.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
US14/839,357 2014-09-25 2015-08-28 Bit-line voltage boosting methods for static RAM and semiconductor device including static RAM Active US9589609B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2014-195612 2014-09-25
JP2014195612A JP6451177B2 (ja) 2014-09-25 2014-09-25 スタティックｒａｍおよびスタティックｒａｍを搭載する半導体装置

Publications (2)

Publication Number Publication Date
US20160093370A1 US20160093370A1 (en) 2016-03-31
US9589609B2 true US9589609B2 (en) 2017-03-07

Family

ID=55585179

Family Applications (1)

Application Number Title Priority Date Filing Date
US14/839,357 Active US9589609B2 (en) 2014-09-25 2015-08-28 Bit-line voltage boosting methods for static RAM and semiconductor device including static RAM

Country Status (2)

Country Link
US (1) US9589609B2 (ja)
JP (1) JP6451177B2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199092B2 (en) * 2016-06-21 2019-02-05 Arm Limited Boost circuit for memory

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11317083A (ja) 1998-05-01 1999-11-16 Nec Corp 半導体記憶回路とその制御方法
US6055655A (en) * 1996-05-30 2000-04-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and method of testing the same
JP2004303340A (ja) 2003-03-31 2004-10-28 Renesas Technology Corp 半導体記憶装置
US20060262635A1 (en) 2005-05-20 2006-11-23 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
US20090161449A1 (en) 2007-12-19 2009-06-25 Yoshinobu Yamagami Semiconductor storage device
JP2010257554A (ja) 2009-04-28 2010-11-11 Panasonic Corp 半導体記憶装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57154696A (en) * 1981-03-20 1982-09-24 Hitachi Ltd Semiconductor integrated circuit device
JP2000195276A (ja) * 1998-12-25 2000-07-14 Mitsubishi Electric Corp 半導体記憶装置
US7379354B2 (en) * 2006-05-16 2008-05-27 Texas Instruments Incorporated Methods and apparatus to provide voltage control for SRAM write assist circuits
US8964490B2 (en) * 2013-02-07 2015-02-24 Apple Inc. Write driver circuit with low voltage bootstrapping for write assist
JP2016012383A (ja) * 2014-06-27 2016-01-21 株式会社ソシオネクスト スタティックｒａｍ

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6055655A (en) * 1996-05-30 2000-04-25 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device and method of testing the same
JPH11317083A (ja) 1998-05-01 1999-11-16 Nec Corp 半導体記憶回路とその制御方法
JP2004303340A (ja) 2003-03-31 2004-10-28 Renesas Technology Corp 半導体記憶装置
US20040252548A1 (en) 2003-03-31 2004-12-16 Yasumasa Tsukamoto Semiconductor memory device
US20060262635A1 (en) 2005-05-20 2006-11-23 Matsushita Electric Industrial Co., Ltd. Semiconductor memory device
JP2006323950A (ja) 2005-05-20 2006-11-30 Matsushita Electric Ind Co Ltd 半導体記憶装置
US20090161449A1 (en) 2007-12-19 2009-06-25 Yoshinobu Yamagami Semiconductor storage device
JP2009151847A (ja) 2007-12-19 2009-07-09 Panasonic Corp 半導体記憶装置
JP2010257554A (ja) 2009-04-28 2010-11-11 Panasonic Corp 半導体記憶装置
US20110032779A1 (en) 2009-04-28 2011-02-10 Panasonic Corporation Semiconductor memory device

Also Published As

Publication number Publication date
JP2016066397A (ja) 2016-04-28
JP6451177B2 (ja) 2019-01-16
US20160093370A1 (en) 2016-03-31

Similar Documents

Publication Publication Date Title
US8503221B1 (en) SRAM cell with common bit line and source line standby voltage
JP6308831B2 (ja) 半導体記憶装置
US7447058B2 (en) Write margin of SRAM cells improved by controlling power supply voltages to the inverters via corresponding bit lines
TWI490867B (zh) 具容忍變異字元線驅動抑制機制之隨機存取記憶體
US9424912B2 (en) Static ram
US7965569B2 (en) Semiconductor storage device
US20170365308A1 (en) Memory device including memory cell for generating reference voltage
US10236055B1 (en) Memory element write-assist circuitry with dummy bit lines
JP2009070480A (ja) 半導体記憶装置
US8400848B2 (en) Bit line negative potential circuit and semiconductor storage device
US7319607B2 (en) Ferroelectric memory
JPH10112185A (ja) 半導体記憶装置のビット線プリチャージ回路
US8830784B2 (en) Negative word line driver for semiconductor memories
CN101430924B (zh) 半导体存储装置
US9715923B2 (en) Semiconductor memory device and method for driving the same
US8743628B2 (en) Line driver circuits, methods, and apparatuses
US8218372B2 (en) Semiconductor storage device
US9589609B2 (en) Bit-line voltage boosting methods for static RAM and semiconductor device including static RAM
JP4336212B2 (ja) 半導体記憶装置
JP6540006B2 (ja) ビット線プリチャージ回路、スタティックｒａｍ、電子デバイスおよびスタティックｒａｍのビット線プリチャージ方法
US20080037337A1 (en) Semiconductor memory
US20100097836A1 (en) Memory Bitcell and Method of Using the Same
US7110279B2 (en) Memory
CN109427394B (zh) 数据线控制电路及相关的数据线控制方法
US7142465B2 (en) Semiconductor memory

Legal Events

Date Code Title Description
AS Assignment

Owner name: SOCIONEXT INC., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:WU, WENHAO;REEL/FRAME:036456/0109

Effective date: 20150821

STCF Information on status: patent grant

Free format text: PATENTED CASE

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 4TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1551); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 4