JPS57154696A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS57154696A
JPS57154696A JP56039426A JP3942681A JPS57154696A JP S57154696 A JPS57154696 A JP S57154696A JP 56039426 A JP56039426 A JP 56039426A JP 3942681 A JP3942681 A JP 3942681A JP S57154696 A JPS57154696 A JP S57154696A
Authority
JP
Japan
Prior art keywords
circuit
constituted
channel
misfets
well area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP56039426A
Other languages
Japanese (ja)
Other versions
JPH0230117B2 (en
Inventor
Kenzo Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP56039426A priority Critical patent/JPS57154696A/en
Publication of JPS57154696A publication Critical patent/JPS57154696A/en
Publication of JPH0230117B2 publication Critical patent/JPH0230117B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE:To elevate a degree of integration, by selectively applying the supply voltage in accordance with the operation mode, to a memory matrix part of an RAM, a bit line selecting circuit separated from a well area of a word line selecting circuit, and a well area of other logical circuit. CONSTITUTION:A circuit 1 is constituted of an FF circuit consisting of p-channel MISFETs Q1, Q2 and n-channel MISFETs Q3, Q4, and n-channel transmission gate MISFETs Q5, Q6. A work line selecting circuit constituted of an inverting circuit consisting of a memory cell, a p-channel MISFET Q7, and an n-channel MISFET Q8, and a Y-address decoding circuit YD, a bit line selecting circuit constituted of MISFETs Q9, Q10 of a circuit 2, inverting circuits Q11, Q12 and an X-address decoding circuit XD, an input/output circuit I/O, and a P type well area for forming an n-channel MISFET in a logical circuit LGC are separated from each other and are constituted. To the well area of the circuit 2 side, negative supply voltage -VDD is supplied selectively in accordance with the operation mode.
JP56039426A 1981-03-20 1981-03-20 Semiconductor integrated circuit device Granted JPS57154696A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56039426A JPS57154696A (en) 1981-03-20 1981-03-20 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56039426A JPS57154696A (en) 1981-03-20 1981-03-20 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS57154696A true JPS57154696A (en) 1982-09-24
JPH0230117B2 JPH0230117B2 (en) 1990-07-04

Family

ID=12552659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56039426A Granted JPS57154696A (en) 1981-03-20 1981-03-20 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57154696A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59231917A (en) * 1983-06-15 1984-12-26 Hitachi Ltd Semiconductor device
JPH04372789A (en) * 1991-06-21 1992-12-25 Sanyo Electric Co Ltd Semiconductor memory
JP2016066397A (en) * 2014-09-25 2016-04-28 株式会社ソシオネクスト Static ram and semiconductor device on which static ram is mounted

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59231917A (en) * 1983-06-15 1984-12-26 Hitachi Ltd Semiconductor device
JPH04372789A (en) * 1991-06-21 1992-12-25 Sanyo Electric Co Ltd Semiconductor memory
JP2016066397A (en) * 2014-09-25 2016-04-28 株式会社ソシオネクスト Static ram and semiconductor device on which static ram is mounted

Also Published As

Publication number Publication date
JPH0230117B2 (en) 1990-07-04

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