US8723051B2 - Wiring substrate and method for manufacturing wiring substrate - Google Patents

Wiring substrate and method for manufacturing wiring substrate Download PDF

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Publication number
US8723051B2
US8723051B2 US13/479,833 US201213479833A US8723051B2 US 8723051 B2 US8723051 B2 US 8723051B2 US 201213479833 A US201213479833 A US 201213479833A US 8723051 B2 US8723051 B2 US 8723051B2
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layer
wiring
substrate body
insulating
trench
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US20120307470A1 (en
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Rie Arai
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Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
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Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD. reassignment SHINKO ELECTRIC INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ARAI, RIE
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00—Constructional details common to different types of electric apparatus
    • H05K7/02—Arrangements of circuit components or wiring on supporting structure
    • H05K7/06—Arrangements of circuit components or wiring on supporting structure on insulating boards, e.g. wiring harnesses
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
    • H05K3/4605—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated made from inorganic insulating material
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09563—Metal filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base

Definitions

  • the present invention generally relates to a wiring substrate and a method for manufacturing a wiring substrate.
  • a wiring substrate including plural wiring layers and plural insulating layers alternately layered on a substrate body formed of an inorganic material such as silicon, glass, or ceramic.
  • the wiring substrate also includes adjacent wiring layers that have the insulating layers interposed therebetween and are connected by a via hole penetrating through the insulating layers.
  • FIG. 1 is a cross-sectional view of a wiring substrate 100 of a related art example.
  • the wiring substrate 100 includes a substrate body 110 having a first surface on which a GND (ground) plane layer 130 is formed.
  • the wiring substrate 100 also includes a first insulating layer 160 covering the GND plane layer 130 .
  • the substrate body 110 has a second surface on which a power plane layer 140 is formed.
  • the wiring substrate 100 also includes a second insulating layer 170 covering the power plane layer 140 .
  • a penetration wiring 150 which penetrates through the substrate body 110 , electrically connects between a wiring layer (not illustrated) formed on the first surface of the substrate body 110 and a wiring layer (not illustrated) formed on the second surface of the substrate body 110 .
  • the substrate body 110 may be covered with an insulating film.
  • the GND plane layer 130 and the power plane layer 140 are formed relatively thick because the GND plane layer 130 and the power plane layer 140 are formed for stabilizing the ground or the electric potential of the power supply.
  • a layer including the term “plane layer” is a layer that is flatly formed almost entirely on a predetermined surface.
  • the ground plane layer 130 is formed almost entirely on the first surface of the substrate body 110 except at the vicinity of an end surface of the penetration wiring 150 .
  • the power plane layer 140 is formed almost entirely on the second surface of the substrate body 110 except at the vicinity of an end surface of the penetration wiring 150 .
  • a photosensitive polyimide type resin may be used to form the first and the second insulating layers 160 , 170 .
  • Wiring layers (not illustrated) are formed on the first and the second insulating layers 160 , 170 , respectively.
  • the wiring layers (not illustrated) formed on the first and the second insulating layers 160 , 170 can be electrically connected to the penetration wiring 150 .
  • a photosensitive polyimide type resin may be applied to the GND plane layer 130 and the power plane layer 140 , and then cured.
  • the GND plane layer 130 and the power plane layer 140 are formed thicker than the wiring layers (not illustrated) formed on the first and the second insulating layers 160 and 170 .
  • the first and the second insulating layers 160 , 170 (which are formed on the GND plane layer 130 and the power plane layer 140 ) tend to have a concavo-convex surface rather than a flat surface.
  • a wiring substrate including a substrate body formed of an inorganic material and including a first surface and a second surface, a first trench formed in a first surface side of the substrate body, a second trench formed in a second surface side of the substrate body, a penetration hole penetrating through the substrate body, a first plane layer filling the first trench, a second plane layer filling the second trench, and a penetration wiring filling the penetration hole, wherein the first plane layer is a reference potential layer, wherein the second plane layer is a power supply layer.
  • FIG. 1 is a cross-sectional view illustrating a wiring substrate according to a related art example
  • FIG. 2 is a cross-sectional view of a wiring substrate according to an embodiment of the present invention.
  • FIG. 3 is a plan view illustrating a positional relationship between a trench and a penetration hole according to an embodiment of the present invention.
  • FIGS. 4 to 12 are schematic diagrams illustrating processes of a method for manufacturing a wiring substrate according to an embodiment of the present invention.
  • FIG. 2 is a cross-sectional view illustrating the wiring substrate 10 according to an embodiment of the present invention.
  • the wiring substrate 10 includes a substrate body 11 , an insulating film 12 , a GND plane layer 13 , a power plane layer 14 , a penetration wiring 15 , a first insulating layer 16 , a first wiring layer 17 , a second insulating layer 18 , a second wiring layer 19 , a third insulating layer 20 , a fourth insulating layer 21 , a third wiring layer 22 , a fifth insulating layer 23 , a fourth wiring layer 24 , a sixth insulating layer 25 .
  • the substrate body 11 is a part of the wiring substrate 10 serving as a base substrate on which a layer(s) such as the GND plane layer 13 is formed. Trenches 11 x , fly and a penetration hole 11 z are formed in the substrate body 11 .
  • the substrate body 11 can be formed having a thickness of, for example, approximately 200 ⁇ m to 400 ⁇ m.
  • an inorganic material such as silicon, glass, or ceramic may be used as the material of the substrate body 11 .
  • the wiring substrate 10 may be manufactured into a semiconductor package by mounting a semiconductor chip X on the wiring substrate 10 .
  • the material of the substrate body 11 is preferably silicon or a borosilicate glass having a thermal expansion coefficient similar to silicon because the semiconductor chip X, often includes a silicon substrate.
  • the borosilicate glass is a glass mainly including boric acid (B 2 O 3 ) or silicic acid (SiO 2 ) and has a thermal expansion coefficient of approximately 3 ppm/° C.
  • the material of the substrate body 11 is preferably silicon.
  • the thermal expansion coefficient of the substrate body 11 is matched with the thermal expansion coefficient of the semiconductor chip X for reducing thermal stress generated at a bonding part between the substrate body 11 and the semiconductor chip X in view of operating under a high temperature atmosphere or a low temperature atmosphere.
  • the substrate body 11 is formed of silicon.
  • the trench 11 x is open on the side of a first surface 11 a (first surface side) of the substrate body 11 .
  • the trench 11 x can be formed in a region excluding the penetration hole 11 z and a part surrounding the penetration hole 11 z from a plan view.
  • the trench 11 x may be in communication with a portion of the penetration hole 11 z .
  • the trench 11 x corresponds to a portion of the substrate body 11 at which the GND plane layer 13 is formed.
  • the plan view shape of the trench 11 x may be, for example, a rectangle or a circle.
  • the depth of the trench 11 x may be, for example, approximately 20 ⁇ m to 50 ⁇ m.
  • the trench 11 y is open on the side of a second surface 11 b (second surface side) of the substrate body 11 .
  • the trench 11 y can be formed in a region excluding the penetration hole 11 z and a surrounding of the penetration hole 11 z .
  • the trench 11 y may be in communication with a portion of the penetration hole 11 z .
  • the trench 11 y corresponds to a portion of the substrate body 11 at which the power plane layer 14 is formed.
  • the plan view shape of the trench 11 y may be, for example, a rectangle or a circle.
  • the depth of the trench 11 y may be, for example, approximately 20 ⁇ m to 50 ⁇ m.
  • the trench 11 x and the trench 11 y may be formed in areas superposing each other from a plane view. It is to be noted that neither the trench 11 x nor the trench 11 y is in communication with a penetration hole 11 z shared by the trench 11 x and the trench 11 y.
  • the trenches 11 x , 11 y may be formed in regions excluding the penetration hole 11 z and a part surrounding the penetration hole 11 z but are to be formed at least below an area on which the semiconductor chip X is mounted.
  • the penetration hole 11 z is a hole penetrating through the substrate body 11 from the first surface side of the substrate body 11 to the second surface side of the substrate body 11 .
  • the penetration hole 11 z has a substantially circular shape from a plan view.
  • the diameter of the penetration hole 11 z may be, for example, approximately 40 ⁇ m to 60 ⁇ m.
  • the depth of the penetration hole 11 z (thickness of the substrate body 11 ) may be, for example, approximately 200 ⁇ m to 400 ⁇ m.
  • the insulating film 12 is formed on the first and the second surfaces 11 a , 11 b of the substrate body 11 , the inner bottom surfaces of the trenches 11 x , fly, and the inner side surfaces of the trenches 11 x , 11 y .
  • the insulating film 12 is for insulating the substrate body 11 from the GND plane layer 13 , the power plane layer 14 , and the penetration wiring 15 .
  • silicon dioxide (SiO 2 ), silicon nitride (SiN), or polyimide (PI) may be used as the material of the insulating film 12 .
  • the thickness of the insulating film 12 may be, for example, approximately 1 ⁇ m to 2 ⁇ m.
  • the insulating film 12 is provided because the substrate body 11 is formed of silicon (semiconductor material).
  • the wiring substrate 10 may be formed without the insulating film 12 .
  • the GND plane layer 13 is for stabilizing the potential of the ground (GND).
  • the GND plane layer 13 fills the trench 11 x having its inner side surface and inner bottom surface covered by the insulating film 12 .
  • the GND plane layer 13 is formed almost entirely on the first surface 11 a of the substrate body 11 except at a part surrounding a first end surface of the penetration wiring 15 from a plan view.
  • the GND plane layer 13 may be conducted with respect to a portion of the penetration wiring having the same potential as the GND plane layer 13 .
  • the ground plane layer 13 is to be formed at least below an area on which the semiconductor chip X is mounted.
  • a top surface of the GND plane layer 13 (surface exposed at the first surface side of the substrate body 11 ) is substantially flush with a top surface of the insulating film 12 covering the first surface 11 a of the substrate body 11 .
  • the thickness of the GND plane layer 13 is substantially greater than or equal to the thickness of, for example, the wiring pattern of the first wiring layer 17 .
  • the thickness of the GND plane layer 13 may be, for example, approximately 20 ⁇ m to 50 ⁇ m.
  • the “plane layer” is a layer that is flatly formed almost entirely on a predetermined surface.
  • the GND plane layer 13 includes a first layer 13 a and a second layer 13 b .
  • the first layer 13 a covers the insulating film 12 covering the inner side surface and the inner bottom surface of the trench 11 x .
  • the first layer 13 a may be, for example, a conductive layer formed by layering a titanium (Ti) film and a copper (Cu) film on the insulating film 12 in this order.
  • the thickness of the first layer 13 a may be, for example, approximately 1 ⁇ m.
  • the second layer 13 b covers the first layer 13 a and fills the trench 11 x .
  • copper (Cu) may be used as the material of the second layer 13 b.
  • the GND plane layer 13 is a representative example of a reference potential layer according to an embodiment of the present invention.
  • the power plane layer 14 is for stabilizing the potential of the power supply.
  • the power plane layer 14 fills the trench 11 y having its inner side surface and inner bottom surface covered by the insulating film 12 .
  • the power plane layer 14 is formed almost entirely on the second surface 11 b of the substrate body 11 except at a part surrounding a second end surface of the penetration wiring 15 from a plan view.
  • the power plane layer 14 may be conducted with respect to a portion of the penetration wiring having the same potential as the power plane layer 14 .
  • the power plane layer 14 is to be formed at least below an area on which the semiconductor chip X is mounted.
  • a top surface of the power plane layer 14 (surface exposed at the second surface side of the substrate body 11 ) is substantially flush with a top surface of the insulating film 12 covering the second surface 11 b of the substrate body 11 .
  • the thickness of the power plane layer 14 it is preferable for the thickness of the power plane layer 14 to be substantially greater than or equal to the thickness of, for example, the wiring pattern of the first wiring layer 17 .
  • the thickness of the power plane layer 14 may be, for example, approximately 20 ⁇ m to 50 ⁇ m.
  • the power plane layer 14 includes a first layer 14 a and a second layer 14 b .
  • the first layer 14 a covers the insulating film 12 covering the inner side surface and the inner bottom surface of the trench 11 y .
  • the first layer 14 a may be, for example, a conductive layer formed by layering a titanium (Ti) film and a copper (Cu) film on the insulating film 12 in this order.
  • the thickness of the first layer 14 a may be, for example, approximately 1 ⁇ m.
  • the second layer 14 b covers the first layer 14 a and fills the trench 11 y .
  • copper (Cu) may be used as the material of the second layer 14 b.
  • the power plane layer 14 can attain a satisfactory adhesiveness between the first layer 14 a and the insulating layer 12 in a case where the material of the insulating film 12 is silicon dioxide (SiO 2 ) or silicon nitride (SiN). Accordingly, unlike a case where the second layer 14 b directly contacts the insulating film 12 , a space(s) between the power plane layer 14 and the insulating film 12 can be prevented from being formed as a result of poor adhesiveness. Thus, the second layer 14 b is adhered to the insulating film 12 interposed by the first layer 14 a .
  • the power plane layer 14 is a representative example of a power layer (power supply layer) according to an embodiment of the present invention.
  • the GND plane layer 13 and the power plane layer 14 do not need to be formed symmetrical to each other.
  • the penetration wiring 15 fills the penetration hole 11 z having its inner side surface covered by the insulating film 12 .
  • the penetration wiring 15 includes a first layer 15 a , a second layer 15 b , and a third layer 15 c .
  • the first layer 15 a fills a portion of the penetration hole 11 z .
  • the first layer 15 a fills the penetration hole 11 z except for an upper portion (toward the first surface 11 a of the substrate body 11 ) of the penetration hole 11 z having its inner side surface covered by the insulating film 12 .
  • a top surface of the first layer 15 a is in a position in which the first surface 11 a is recessed toward the second surface 11 b of the substrate body 11 .
  • the top surface of the first layer 15 a and a portion of the insulating film 12 covering the inner side surface of the penetration hole 11 z constitute a recess part 15 x .
  • the depth of the recess part 15 x may be, for example, approximately 50 ⁇ m.
  • copper (Cu) may be used as the material of the first layer 15 a .
  • a surface of the first layer 15 a exposed toward the second surface side of the substrate body 11 is substantially flush with a surface of the insulating film 12 covering the second surface 11 b of the substrate body 11 .
  • the second layer 15 b is formed inside the recess part 15 x . More specifically, in this embodiment, the second layer 15 b covers the top surface of the first layer 15 a and a portion of the insulating film 12 covering the inner side surface of the penetration hole 11 z .
  • the second layer 15 b may be, for example, a conductive layer formed by layering a titanium (Ti) film and a copper (Cu) film on the insulating film 12 and the first layer 15 a in this order.
  • the thickness of the second layer 15 b may be, for example, approximately 1 ⁇ m.
  • the third layer 15 c covers the second layer 15 b and fills the recess part 15 x .
  • the top surface of the third layer 15 c i.e.
  • the surface of the penetration wiring 15 exposed on the first surface side of the substrate body 11 is substantially flush with the surface of the insulating film 12 covering the first surface 11 a of the substrate body 11 .
  • copper (Cu) may be used as the material of the third layer 15 c.
  • the penetration wiring 15 can attain a satisfactory adhesiveness with respect to the insulating layer 12 in a case where the material of the insulating film 12 is silicon dioxide (SiO 2 ) or silicon nitride (SiN). Accordingly, unlike a case where the third layer 15 c directly contacts the insulating film 12 , a space(s) between the third layer 15 c and the insulating film 12 can be prevented from being formed as a result of poor adhesiveness. Thus, the third layer 15 c is adhered to the insulating film 12 interposed by the second layer 15 b.
  • the first layer 15 a may fill up the entire penetration hole 11 z (including the upper portion of the penetration hole 11 z toward the trench 11 x ) having its inner surface covered by the insulating film 12 .
  • the top surface of the first layer 15 a i.e. surface toward the trench 11 x
  • the penetration wiring 15 may be formed without a recess part 15 x.
  • the first layer 15 a is preferred not to project from the top surface of the insulating film 12 covering the first surface 11 a of the substrate body 11 .
  • the projection would prevent the second layer 15 b from satisfactorily covering the first layer 15 a and the insulating film 12 . This may lead to problems such as peeling or disconnection of the second layer 15 b .
  • the first layer 15 a fills the penetration hole 11 z to a degree that the top surface of the first layer 13 a (i.e. surface toward the trench 11 x ) is in a position in which the first surface 11 a is recessed toward the second surface 11 b of the substrate body 11 . That is, in this embodiment, the recess part 15 x is formed.
  • the second layer 15 b is interposed between the first and the third layers 15 a , 15 c .
  • This owes to the processes of the following method for manufacturing the wiring substrate 10 according to an embodiment of the present invention.
  • the first and the third layers 15 a , 15 c can prevent the generation of defects such as seams and voids.
  • the first insulating layer 16 is formed on the first surface 11 a of the substrate body 11 .
  • the first insulating layer 16 covers the GND plane layer 13 and a first end surface of the penetration wiring 15 .
  • an insulating resin such as a photosensitive polyimide type resin may be used as the material of the first insulating layer 16 .
  • the thickness of the first insulating layer 16 may be, for example, approximately 15 ⁇ m to 25 ⁇ m.
  • the first wiring layer 17 is formed on the first insulating layer 16 .
  • the first wiring layer 17 includes a via wiring that fills a first via hole 16 x and a wiring pattern that is formed on the first insulating layer 16 .
  • the first via hole 16 x penetrates through the first insulating layer 16 and exposes the first end surface of the penetration wiring 15 .
  • the wiring pattern of the first wiring layer 17 is patterned into a predetermined flat shape.
  • the first via hole 16 x has an opening part toward the second insulating layer 18 and a bottom surface part formed by the first end surface of the penetration wiring 15 . Accordingly, in this embodiment, the first via hole 16 x is a recess part having a circular conical shape in which the area of the opening part is larger than the area of the bottom surface part. Further, the via wiring is formed inside the recess part.
  • the first wiring layer 17 is electrically connected to the penetration wiring 15 exposed at the first via hole 16 x .
  • copper (Cu) may be used as the material of the first wiring layer 17 .
  • the thickness of the wiring pattern constituting the first wiring layer 17 may be, for example, approximately 10 ⁇ m to 20 ⁇ m.
  • the second insulating layer 18 is formed on the first insulating layer 16 and covers the first wiring layer 17 .
  • the material of the second insulating layer 18 may be the same as that of the first insulating layer 16 .
  • the thickness of the second insulating layer 18 may be, for example, approximately 15 ⁇ m to 25 ⁇ m.
  • the second wiring layer 19 is formed on the second insulating layer 18 .
  • the second wiring layer 19 includes a via wiring that fills a second via hole 18 x and a wiring pattern that is formed on the second insulating layer 18 .
  • the second via hole 18 x penetrates through the second insulating layer 18 and exposes the top surface of the first wiring layer 17 .
  • the wiring pattern of the second wiring layer 19 is patterned into a predetermined flat shape.
  • the second via hole 18 x has an opening part toward the third insulating layer 20 and a bottom surface part formed by the top surface of the first wiring layer 17 . Accordingly, in this embodiment, the second via hole 18 x is a recess part having a circular conical shape in which the area of the opening part is larger than the area of the bottom surface part. Further, the via wiring is formed inside the recess part.
  • the second wiring layer 19 is electrically connected to the exposed first wiring layer 17 in the second via hole 18 x .
  • copper Cu
  • the thickness of the wiring pattern constituting the second wiring layer 19 may be, for example, approximately 10 ⁇ m to 20 ⁇ m.
  • the third insulating layer 20 is formed on the second insulating layer 18 and covers the second wiring layer 19 .
  • the third insulating layer 20 includes an opening part 20 x . At least a portion of the second wiring layer 19 is exposed at the opening part 20 x .
  • the material of the third insulating layer 20 may be the same as that of the first insulating layer 16 .
  • the thickness of the third insulating layer 20 may be, for example, approximately 15 ⁇ m to 25 ⁇ m.
  • the second wiring layer 19 exposed at the opening part 20 x functions as an electrode pad that is electrically connected to the semiconductor chip X.
  • the second wiring layer 19 exposed at the opening part 20 x is also hereinafter referred to as “first electrode pad 19 ”.
  • a metal layer may be formed on the first electrode pad 19 .
  • the metal layer may be a gold (Au) layer, a nickel/gold (Ni/Au) layer (i.e. a metal layer including a Ni layer and a Au layer layered in this order), or a nickel/palladium/gold (Ni/Pd/Au) layer (i.e. a metal layer including a Ni layer, a Pd layer, and a Au layer layered in this order).
  • Au gold
  • Ni/Au nickel/gold
  • Ni/Pd/Au nickel/palladium/gold
  • an external connection terminal (e.g., solder ball, lead pin) may be formed on the first electrode pad 19 or a metal layer in a case where the metal layer is formed on the first electrode pad 19 .
  • the external connection terminal is for electrically connecting to the semiconductor chip X. It is, however, to be noted that the first electrode pad 19 itself may be used as the external connection terminal. In a case where a metal layer is formed on the first electrode pad 19 , the metal layer itself may be used as the external connection terminal.
  • the first electrode pad 19 is flat and has a shape of, for example, a circle.
  • the diameter of the circle is, for example, approximately 100 ⁇ m to 200 ⁇ m.
  • the fourth insulating layer 21 , the third wiring layer 22 , the fifth insulating layer 23 , the fourth wiring layer 24 , and the sixth insulating layer 25 are sequentially layered on the second surface 11 b of the substrate body 11 .
  • the third wiring layer 22 is electrically connected to the penetration wiring 15 by way of a third via hole 21 x .
  • the fourth wiring layer 24 is electrically connected to the third wiring layer 22 by way of a fourth via hole 23 x .
  • a detailed description of the fourth insulating layer 21 , the third wiring layer 22 , the fifth insulating layer 23 , and the fourth wiring layer 24 is omitted because the fourth insulating layer 21 , the third wiring layer 22 , the fifth insulating layer 23 , and the fourth wiring layer 24 have substantially the same configuration as that of the above-described first insulating layer 16 , the first wiring layer 17 , the second insulating layer 18 , and the second wiring layer 19 , respectively.
  • the sixth insulating layer 25 is formed on the fifth insulating layer 23 and covers the fourth wiring layer 24 .
  • the sixth insulating layer 25 includes an opening part 25 x . At least a portion of the fourth wiring layer 24 is exposed at the opening part 25 x .
  • the material of the sixth insulating layer 25 may be the same as that of the first insulating layer 16 .
  • the thickness of the sixth insulating layer 25 may be, for example, approximately 15 ⁇ m to 25 ⁇ m.
  • the fourth wiring layer 24 exposed at the opening part 25 x functions as an electrode pad that is electrically connected to a mount board such as a motherboard (not illustrated).
  • the fourth wiring layer 24 exposed at the opening part 25 x is also hereinafter referred to as “second electrode pad 24 ”.
  • a metal layer may be formed on the second electrode pad 24 .
  • the metal layer may be a gold (Au) layer, a nickel/gold (Ni/Au) layer (i.e. a metal layer including a Ni layer and a Au layer layered in this order), or a nickel/palladium/gold (Ni/Pd/Au) layer (i.e. a metal layer including a Ni layer, a Pd layer, and a Au layer layered in this order).
  • an external connection terminal (e.g., solder ball, lead pin) may be formed on the second electrode pad 24 or a metal layer in a case where the metal layer is formed on the second electrode pad 24 .
  • the external connection terminal is for electrically connecting to a mount board such as a motherboard (not illustrated). It is, however, to be noted that the second electrode pad 24 itself may be used as the external connection terminal. In a case where a metal layer is formed on the second electrode pad 24 , the metal layer itself may be used as the external connection terminal.
  • the second electrode pad 24 is flat and has a shape of, for example, a circle.
  • the diameter of the circle is, for example, approximately 200 ⁇ m to 1000 ⁇ m.
  • the diameter of the second electrode pad 24 (which is to be electrically connected to a mount board such as a motherboard (not illustrated)) is greater than the diameter of the first electrode pad 19 (which is to be electrically connected to the semiconductor chip X.
  • the pitch between the second electrode pads 24 may be, for example, approximately 500 ⁇ m to 1200 ⁇ m. In other words, the pitch between the second electrode pads 24 (which are to be electrically connected to a mount board such as a motherboard (not illustrated)) is greater than the pitch between the first electrode pads 19 (which are to be electrically connected to the semiconductor chip X.
  • the side of the wiring substrate 10 on which the GND plane layer 13 is formed is the side on which the semiconductor chip X is to be mounted.
  • the GND plane layer 13 can be easily connected to the GND of a semiconductor chip X.
  • the GND plane layer 13 can be used as a ground layer of a microstrip line that contributes to the reduction of signal transmission loss of a signal layer including the first and the second wiring layers 17 , 19 . Assuming that the GND plane layer 13 is formed on the side of the wiring substrate 10 on which a mount board such as a motherboard (not illustrated) is to be mounted (i.e.
  • the GND plane layer 13 and a signal layer including the first and the second wiring layers 17 , 19 would be far from each other. As a result, it would be difficult for the GND plane layer 13 to function as the ground of a microstrip line, and signal transmission loss is increased.
  • FIGS. 4 to 12 illustrate the steps of the method for manufacturing a wiring substrate according to an embodiment of the present invention.
  • the substrate body 11 is prepared. Then, the trench 11 x and the penetration hole 11 z are formed on the first surface side of the substrate body 11 .
  • the penetration hole 11 z penetrates through the substrate body 11 from the first surface 11 a to the second surface 11 b .
  • the trench 11 x is an area at which the GND plane layer 13 is to be formed.
  • the substrate body 11 may be a silicon wafer having a length of 6 inches (approximately 150 mm), 8 inches (approximately 200 mm), or 12 inches (approximately 300 mm).
  • the thickness of the silicon wafer may be, for example, 0.625 mm (in a case of a 6 inch wafer), 0.725 mm (in a case of an 8 inch wafer), or 0.775 mm (in a case of a 12 inch wafer). It is, however, to be noted that, the thickness of the silicon wafer may be reduced by using, for example, a back-side grinder.
  • a resist layer is formed on the first surface 11 a of the substrate body 11 .
  • the resist layer has openings corresponding to areas at which the trench 11 x and the penetration hole 11 z are to be formed.
  • the substrate body 11 is etched by using the resist layer as a mask. Thereby, the trench 11 x and the penetration hole 11 z are formed.
  • the etching it is preferable for the etching to be anisotropic etching such as deep reactive ion etching (DRIE) using sulfur hexafluoride (SF 6 ).
  • the trench 11 x is formed by etching the substrate body 11 to a predetermined depth.
  • the penetration hole liz is formed by etching the substrate body 11 until the substrate body 11 is penetrated.
  • the depth of the trench 11 x may be, for example, approximately 40 ⁇ m to 60 ⁇ m.
  • the depth of the penetration hole 11 z (thickness of the substrate body 11 ) may be, for example, approximately 200 ⁇ m to 400 ⁇
  • the insulating film 12 is formed on the first and second surfaces 11 a , 11 b of the substrate body 11 , the inner bottom surface and the inner side surface of the trench 11 x , and the inner side surface of the penetration hole 11 z .
  • the insulating film 12 may be, for example, a silicon oxide (SiO 2 ) film.
  • the insulating film 12 may be formed by performing thermal oxidation using a wet thermal oxidation method on the substrate body 11 in which the vicinity of the surface of the substrate body 11 is heated to a temperature of, for example, 1000° C., or more.
  • the thickness of the insulating film 12 may be, for example, approximately 1 ⁇ m to 2 ⁇ m.
  • the insulating film 12 may be a silicon dioxide (SiO 2 ) film, a silicon nitride (SiN) film, or a polyimide film formed by using, for example, a chemical vapor deposition (CVD) method.
  • SiO 2 silicon dioxide
  • SiN silicon nitride
  • CVD chemical vapor deposition
  • a metal layer 32 is formed on the insulating film covering the second surface 11 b interposed by an adhesive layer 31 .
  • an opening part 31 x is formed by removing (e.g., ashing) a portion of the adhesive layer 31 corresponding to the penetration hole 11 z having its inner side surface covered by the insulating film 12 .
  • a top surface of the metal layer 32 is exposed at the penetration hole 11 z having its inner side surface covered by the insulating film 12 .
  • the metal layer 32 is a member to be used as a feeding layer when forming, for example, the penetration wiring by using an electroplating method.
  • a copper (Cu) plate or a copper (Cu) foil may be used as the material of the metal layer 32 .
  • a copper (Cu) plate is used as the metal layer 32 .
  • a plating film is deposited (grown) inside the penetration hole 11 z from the side of the metal layer 32 by performing an electroplating method using the metal layer 32 as a power feed layer (power supply layer).
  • a conductive layer 41 filling at least a portion of the penetration hole 11 z is formed.
  • the conductive layer 41 eventually becomes the first layer 15 a of the penetration wiring 15 .
  • copper (Cu) may be used as the material of the conductive layer 41 .
  • the conductive layer 41 fills the penetration hole 11 z except for a top part of the penetration hole 11 z .
  • the conductive layer 41 fills the penetration hole 11 z except for a top part of the penetration hole 11 z that corresponds to the depth of the trench 11 x .
  • the recess part 15 x is formed by the top surface of the conductive layer 41 (i.e. surface of the conductive layer 41 toward the trench 11 x ) and the insulating film 12 covering the inner side surface of the penetration hole 11 z.
  • the conductive layer 41 may be formed filling the entire penetration hole liz (including the top part of the penetration hole liz (toward the trench 11 x )) having its inner side surface covered by the insulating film 12 . That is, the conductive layer 41 may be formed, so that the top surface of the conductive layer 41 (i.e. surface of the conductive layer 41 toward the trench 11 x ) is substantially flush with the top surface of the insulating film 12 covering the first surface lie of the substrate body 11 . Nevertheless, it is not preferable to form the conductive layer 41 projecting from the top surface of the insulating film 12 covering the first surface 11 a of the substrate body 11 .
  • the depth of the recess part 15 x may be, for example, approximately 0 ⁇ m to 10 ⁇ m.
  • the conductive layer 41 can be formed by growing a plating film only from one side (in this embodiment, from the side of metal layer 32 ). Accordingly, unlike the wiring substrate 100 of the related art example, the generation of, for example, seams or voids due to growing plating films from two directions can be prevented. As a result, the first layer 15 a of the penetration wiring 15 (i.e. final product of the conductive layer 41 ) can be prevented from being disconnected by thermal pressure due to the generation of, for example, seams or voids. Further, the first layer 15 a of the penetration wiring 15 can prevent reduction of connection reliability with respect to the first wiring layer 17 or the third wiring layer 22 .
  • a conductive layer 42 is formed.
  • the conductive layer 42 covers the insulating film 12 covering the first surface 11 a of the substrate body 11 , the inner bottom surface of the trench 11 x , and the inner side surface of the trench 11 x along with a surface of the recess part 15 x .
  • the adhesive layer 31 and the metal layer 32 illustrated in FIG. 7 are removed. Further, a portion of the conductive layer 41 which projects from the second surface side of the substrate body 11 is polished (see, for example, FIG. 7 ). Thereby, the first layer 15 a of the penetration wiring 15 is formed.
  • the conductive layer 42 may be formed by, for example, a sputtering method. By removing an unnecessary portion of, for example, the conductive layer 42 , the conductive layer 42 eventually becomes the first layer 13 a of the GND plane layer 13 and the second layer 15 b of the penetration wiring 15 .
  • the conductive layer 42 may be formed by layering a titanium (Ti) film and a copper (Cu) film on the insulating layer 12 or the conductive layer 41 (see, for example, FIG. 7 ) in this order.
  • the conductive layer 42 may have a thickness of, for example, approximately 1 ⁇ m. It is to be noted that the conductive layer 42 is a representative example of a second feed layer according to an embodiment of the present invention.
  • the metal layer (in this embodiment, a copper (Cu) plate) 32 can be removed by, for example, a wet-etching method using a solution such as a ferric chloride solution, a cupric chloride solution, or an ammonium persulfate solution.
  • the adhesive layer 31 can be removed by, for example, an ashing method.
  • the conductive layer 41 may be polished by, for example, a chemical mechanical polishing (CMP) method.
  • CMP chemical mechanical polishing
  • the trench 11 y is formed on the second surface side of the substrate body 11 .
  • the insulating film 12 is formed on the inner bottom surface of the trench 11 y and the inner side surface of the trench 11 y .
  • the trench 11 y is an area at which the power plane layer 14 is to be formed.
  • the trench 11 y may be formed by using the same method for forming the trench 11 x .
  • the material of the insulating film 12 , the thickness of the insulating film 12 , and method for forming the insulating film 12 are the same as those illustrated, in for example, FIG. 5
  • a conductive layer 43 is formed.
  • the conductive layer 43 covers the insulating film 12 covering the second surface 11 b of the substrate body 11 , the inner bottom surface of the trench 11 y , and the inner side surface of the trench 11 y along with an end surface of the first layer 15 a on the second surface side of the substrate body 11 .
  • the conductive layer 43 may be formed by, for example, a sputtering method. By removing an unnecessary portion of, for example, the conductive layer 43 , the conductive layer 43 eventually becomes the first layer 14 a of the power plane layer 14 .
  • the conductive layer 43 may be formed by layering a titanium (Ti) film and a copper (Cu) film on the insulating layer 12 and on the end surface of the first layer 15 a on the second surface side of the substrate body 11 in this order.
  • the conductive layer 43 may have a thickness of, for example, approximately 1 ⁇ m. It is to be noted that the conductive layer 43 is a representative example of a third feed layer according to an embodiment of the present invention.
  • a plating film is deposited (grown) inside the trench 11 x and the recess part 15 x from the side of the conductive layer 42 and another plating film is deposited (grown) inside the recess part 11 y from the side of the conductive layer 43 by performing an electroplating method using the first layer 15 a , the conductive layer 42 , and the conductive layer 43 as a power feed layer (power supply layer).
  • a conductive layer 44 and a conductive layer 45 are formed.
  • the conductive layer 44 and the conductive layer 45 may be formed simultaneously.
  • the conductive layer 44 By removing an unnecessary portion of, for example, the conductive layer 44 , the conductive layer 44 eventually becomes the second layer 13 b of the GND plane layer 13 and the third layer 15 c of the penetration wiring 15 . Further, by removing an unnecessary portion of, for example, the conductive layer 45 , the conductive layer 45 eventually becomes the second layer 14 b of the power plane layer 14 .
  • copper may be used as the material of the conductive layers 44 , 45 .
  • the conductive layer 44 is formed projecting from the top surface of the insulating film 12 covering the first surface 11 a of the substrate body 11 .
  • the conductive layer 45 is formed projecting from the top surface of the insulating film 12 covering the second surface 11 b of the substrate body 11 .
  • the degree in which the conductive layers 44 , 45 project from the top surface of the corresponding insulating films 12 is, for example, approximately 30 ⁇ m to 40 ⁇ m, respectively.
  • the conductive layer 44 projecting from the first surface side of the substrate body 11 is polished by, for example, a chemical mechanical polishing (CMP) method.
  • CMP chemical mechanical polishing
  • the second layer 13 b of the GND plane layer 13 and the third layer 15 c of the penetration wiring 15 are formed.
  • the top surface of the second layer 13 b of the GND plane layer 13 and the top surface of the third layer 15 c of the penetration wiring 15 are substantially flush with the top surface of the insulating film 12 covering the first surface 11 a of the substrate body 11 .
  • the second layer 14 b of the power plane layer 14 is formed by polishing the conductive layer 45 projecting from the second surface side of the substrate body 11 (see, for example, FIG. 11 ).
  • the top surface of the second layer 14 b of the power plane layer 14 is substantially flush with the top surface of the insulating film 12 covering the second surface 11 b of the substrate body 11 .
  • the first insulating film 16 , the first wiring layer 17 , the second insulating layer 18 , the second wiring layer 19 , and the third insulating layer 20 are sequentially layered on the first surface 11 a of the substrate body 11 .
  • the fourth insulating layer 21 , the third wiring layer 22 , the fifth insulating layer 23 , the fourth wiring layer 24 , and the sixth insulating layer 25 are sequentially layered on the second surface 11 b of the substrate body 11 .
  • a photosensitive polyimide type resin liquid is applied to the first surface 11 a of the substrate body 11 by using a spin-coating method. Then, the first insulating layer 16 is formed by curing the photosensitive polyimide type resin liquid. Then, the first via hole 16 x penetrating the first insulating layer 16 and exposing the first end surface of the penetration wiring 15 is formed by using, for example, a photolithography method.
  • the first via hole 16 x can be formed in the first insulating layer 16 with a photolithography method. Accordingly, the first via holes 16 x can be formed with a narrow pitch.
  • the material of the first insulating layer 16 may be, for example, a non-photosensitive epoxy resin.
  • the first via hole 16 x is formed by using, for example, a laser process method.
  • the first wiring layer 17 is formed on the first insulating layer 16 .
  • the first wiring layer 17 includes a via wiring that fills the first via hole 16 x and a wiring pattern that is formed on the first insulating layer 16 .
  • the first wiring layer 17 is electrically connected to the penetration wiring 15 exposed in the first via hole 16 x .
  • copper (Cu) may be used as the material of the first wiring layer 17 .
  • the first wiring layer 17 may be formed by various wiring forming methods such as a semi-additive method or a subtractive method.
  • the second insulating layer 18 , the second wiring layer 19 , and the third insulating layer 20 are sequentially layered on the first surface 11 a of the substrate body 11 .
  • the fourth insulating layer 21 , the third wiring layer 22 , the fifth insulating layer 23 , the fourth wiring layer 24 , and the sixth insulating layer 25 are sequentially layered on the second surface 11 b of the substrate body 11 .
  • the manufacturing of the wiring substrate 10 is completed by forming the opening part 20 x in the third insulating layer 20 and the opening part 25 x in the sixth insulating layer 25 .
  • the flatness of the first insulating layer 16 and the fourth insulating layer 21 can be improved (compared to, for example, the related art example) regardless of the thickness of the GND plane layer 13 or the power plane layer 14 . Accordingly, other wiring layers and insulating layers can be easily layered on the first insulating layer 16 or the fourth insulating layer 21 . Further, because the GND plane layer 13 and the power plane layer 14 can be formed (flatly formed) having a sufficient thickness and size (area), the GND and the potential of the power supply can be more stable compared to, for example, the related art example.
  • the difference of the thermal expansion between the conductive layers (e.g., copper) constituting the GND plane layer 130 and the power plane layer 140 may cause peeling of film or generation of cracks (for example, cracks are more likely to be generated the larger the contact area between the GND plane layer 130 and the substrate body 110 or the contact area between the power plane layer 140 and the substrate body 110 ).
  • thermal expansion of the GND plane layer 13 and the power plane layer 14 can be controlled at the sidewalls of the trenches 11 x , 11 y by providing the GND plane layer 13 and the power plane layer 14 inside the substrate body 11 (i.e. inside the trenches 11 x , 11 y ).
  • peeling of film or generation of cracks can be prevented.
  • the GND plane layer 130 and the power plane layer 140 are to be formed avoiding areas of the substrate body 110 or the first insulating layer 160 on which other wiring patterns are to be formed.
  • the arrangement of the wiring patterns is limited.
  • the other wiring patterns can be freely arranged because the GND plane layer 13 and the power plane layer 14 are formed inside the substrate body 11 (i.e. inside the trenches 11 x , 11 y ).
  • each wiring layer by, for example, electroplating with copper
  • the plating thicknesses of the wiring layers becomes more inconsistent the greater the occupancy of copper in the wiring layers.
  • the copper occupancy in each wiring layer of the wiring substrate 10 can be reduced by providing the GND plane layer 13 and the power plane layer 14 that have high copper occupancy. Thereby, inconsistent plating thickness of each of the wiring layers can be prevented.
  • the thickness of the wiring substrate 10 can be reduced.

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  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Structure Of Printed Boards (AREA)
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US20160079149A1 (en) * 2013-05-31 2016-03-17 Toppan Printing Co., Ltd. Wiring board provided with through electrode, method for manufacturing same and semiconductor device

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JP6600573B2 (ja) * 2015-03-31 2019-10-30 新光電気工業株式会社 配線基板及び半導体パッケージ
CN109661125B (zh) * 2017-10-12 2021-11-16 宏启胜精密电子(秦皇岛)有限公司 电路板及其制作方法
KR102442256B1 (ko) * 2020-11-05 2022-09-08 성균관대학교산학협력단 보이드가 없는 실리콘 관통전극의 제조방법

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