US8547368B2 - Display driving circuit having a memory circuit, display device, and display driving method - Google Patents

Display driving circuit having a memory circuit, display device, and display driving method Download PDF

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US8547368B2
US8547368B2 US12/734,363 US73436308A US8547368B2 US 8547368 B2 US8547368 B2 US 8547368B2 US 73436308 A US73436308 A US 73436308A US 8547368 B2 US8547368 B2 US 8547368B2
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signal
transistor
electrode
potential level
driving circuit
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US20100245305A1 (en
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Makoto Yokoyama
Yasushi Sasaki
Yuhichiroh Murakami
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3674—Details of drivers for scan electrodes
    • G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3655—Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/18—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages
    • G11C19/182—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes
    • G11C19/184—Digital stores in which the information is moved stepwise, e.g. shift registers using capacitors as main elements of the stages in combination with semiconductor elements, e.g. bipolar transistors, diodes with field-effect transistors, e.g. MOS-FET
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/08—Details of timing specific for flat panels, other than clock recovery
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0219—Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling

Definitions

  • the present invention relates to a display driving circuit and a display driving method for driving a display panel, such as an active matrix liquid crystal display panel, which includes scan signal lines, data signal lines, pixel electrodes, switching elements, and capacity coupling lines, wherein the scan signal lines turn on and off the switching elements corresponding thereto, and each of the switching elements has (i) one terminal connected with one of the respective pixel electrodes and (ii) another terminal connected with one of the respective data signal lines, and the capacity coupling lines are capacity-coupled with corresponding ones of the pixel electrodes, wherein each of the scan signal lines forms a row together with switching elements connected thereto, pixel electrodes respectively connected to these switching elements, and one of the capacity coupling lines capacity-coupled with these pixel electrodes.
  • a display driving circuit for driving a display panel, such as an active matrix liquid crystal display panel, which includes scan signal lines, data signal lines, pixel electrodes, switching elements, and capacity coupling lines, wherein the scan signal lines turn on and off the switching elements corresponding thereto, and
  • CC Charge Coupling driving
  • FIG. 24 is an equivalent circuit diagram illustrating a structure of a device for carrying out the CC driving.
  • FIG. 25 is a timing chart illustrating operating waveforms of various signals in the CC driving.
  • a liquid crystal display device which carries out the CC driving includes an image display section 110 which includes: a plurality of source lines (signal lines) 101 ; a plurality of gate lines (scan lines) 102 which intersect with the plurality of source lines 101 at right angles; switching elements 103 respectively provided near to each of the intersections; pixel electrodes 104 respectively connected to the switching elements 103 ; a plurality of CS (Capacity Storage) bus lines (common electrode lines) 105 which are respectively paired with the plurality of gate lines 102 , and are aligned in parallel with each of the plurality of gate lines 102 ; storage capacitors 106 provided between the pixel electrodes 104 and the plurality of CS bus lines 105 ; a counter electrode 109 ; and a liquid crystal 107 provided between the pixel electrode 104 and the common electrode 109 .
  • CS Capacity Storage
  • Each switching element 103 is formed from amorphous silicon (a-Si), polycrystalline polysilicon (p-Si), monocrystalline silicon (c-Si), or the like. Further, the switching element 103 has a structure in which a capacitor 108 is formed between a gate and a drain. Due to the capacitor 108 , a phenomenon is occurred in which an electric potential of the pixel electrode 104 is shifted to a negative side by a gate pulse supplied via the gate line 102 .
  • the liquid crystal display device includes, outside of the image display section 110 : a source line driving circuit 111 (source driver) which drives the source lines 101 ; a gate line driving circuit 112 (gate driver) which drives the gate lines 102 ; and a CS driving circuit 113 (CS driving circuit) which drives the CS bus line 105 .
  • source driver source driver
  • gate driver gate driver
  • CS driving circuit 113 CS driving circuit
  • FIG. 25 shows operating waveforms of various signals in the liquid crystal display device.
  • a waveform Wg of a gate line 102 is at a voltage Von only during an H-period (horizontal scan period) during which the gate line 102 is being selected. During the other periods, the waveform Wg maintains at a voltage Voff.
  • a waveform Ws of a source line 101 is inverted in polarity in every H-period and, on an identical gate line 102 , polarities are alternated in every H-period (line inversion driving). Note that, the polarities are inverted with amplitude which differs in accordance with a signal of video to be displayed.
  • amplitude of the waveform Ws is constant based on the assumption that a uniform video signal is supplied.
  • the switching element 103 In the period during which the waveform Wg is being at the voltage Von, the switching element 103 is being conductive, whereby a waveform Wd of the pixel electrode 104 has a same electric potential as that of the waveform Ws of the source line 101 during the period. Whereas, when the waveform Wg is turned to be at the voltage Voff, a voltage of the waveform Wd is slightly shifted to the negative side due to the capacitor 108 between the gate and the drain.
  • a waveform We of the CS bus line 105 is at a voltage Ve+ during (i) an H-period during which a corresponding gate line 102 is being selected and (ii) the next H-period.
  • the voltage Ve+ is switched to Ve ⁇ , and then the voltage Ve ⁇ is maintained until a next field.
  • the switch of the voltage shifts a voltage of the waveform Wd of the pixel electrode 104 to the negative side due to the storage capacitor 106 .
  • the waveform Wd of the pixel electrode 104 obtains large amplitude than that of the waveform Ws of the source line 101 . This allows the waveform Ws of the source line 101 to have smaller amplitude.
  • the configuration gives the source line driving circuit 111 a simplified circuit structure and reduced power consumption.
  • FIG. 26 is a block diagram illustrating a schematic structure of a liquid crystal display device which includes a general gate/CS driving circuit.
  • FIG. 27 is a timing chart illustrating waveforms of various signals which are inputted to or outputted from the gate/CS driving circuit.
  • the gate/CS driving circuit includes a gate line driving circuit and a CS driving circuit which are integrated together.
  • a left block of the diagram functions as the gate line driving circuit 112
  • a right block of the diagram functions as the CS driving circuit 113 .
  • the gate line driving circuit 112 and the CS driving circuit 113 are provided so as to deal with each of the rows.
  • a gate line driving circuit 112 at an n-th row and a CS driving circuit 113 at the n-th row are indicated by Gn and CSn, respectively.
  • a row (line) next to the n-th row in a scanning direction (a downward direction in FIG. 26 )
  • a row previous to the n-th row that is, a row opposite the (n+1)th row is referred to as an (n ⁇ 1)th row.
  • the gate line driving circuit 112 includes inside a shift register (not illustrated).
  • a signal supplied from a shift register on the n-th row is indicated by SROn
  • a signal (gate signal) supplied to a gate line on the n-th row is indicated by GLn.
  • the signal GLn is a signal which is produced from the signal SROn which has passed through a buffer, whereby the signal GLn has a same waveform as that of the signal SROn.
  • Gate clocks GCK 1 and GCL 2 are supplied from a control circuit (not illustrated) and define operation timing of shift registers.
  • Clocks CK and CKB are signals which correspond to the gate clocks GCK 1 and GCL 2 , respectively, and are supplied to a gate line driving circuit 112 on each of the rows.
  • a single horizontal scan period (1H) is defined by (i) a period from a rising edge of the clock CK to a rising edge of the clock CKB, or (ii) a period from the rising edge of the clock CKB to a rising edge of the clock CK.
  • the CS driving circuit 113 includes inside a selection switch (UDSW) 113 a and a memory circuit (not illustrated).
  • the selection switch 113 a selects whether a gate signal which serves as a timing signal in generating a CS signal on the n-th row is fetched from a gate line driving circuit Gn ⁇ 1 on the previous row ((n ⁇ 1)th row) or from a gate line driving circuit Gn+1 on the next row (the (n+1)th row).
  • the selection switch 113 a carries out the selection in accordance with switching signals supplied from the control circuit (not illustrated).
  • the switching signals are indicated by UD and UDB and have respective waveforms whose polarities are opposite to each other.
  • the memory circuit In accordance with a gate signal selected by the selection switch 113 a and polarity signals CMI and CMIB, the memory circuit outputs a signal LAOn (see FIG. 27 ) from which a CS signal is produced.
  • the polarity signals CMI and CMIB (i) are supplied from the control circuit to the CS driving circuit 113 and (ii) have respective waveforms whose polarities are opposite to each other.
  • a signal CSOUTn indicates a signal (CS signal) whose electric potential level (level L or level H) is determined based on the signal LAOn.
  • the signal CSOUTn is supplied to a CS bus line on the n-th row.
  • the following describes operation in outputting a CS signal from the CS driving circuit CSn on the n-th row, with reference to the timing chart in FIG. 27 .
  • the following describes a case where (i) the selection switch 113 a selects a gate signal GLn+1 of the gate line driving circuit Gn+1 on the (n+1)th row in accordance with a switching signal supplied from the control circuit, and then (ii) the signal GLn+1 is supplied to the CS driving circuit CSn.
  • the gate signal GLn is supplied from the gate line driving circuit (Gn) on the n-th row to a gate line on the n-th row. Then, after a lapse of a period 1H, that is, at timing of the rising edge of the clock CKB, the gate signal GLn+1 is supplied from the gate line driving circuit (Gn+1) on the (n+1)th row. At the same time, the gate signal GLn+1 is supplied to the memory circuit of the CS driving circuit CSn.
  • the memory circuit 113 is made up of, for example, a D-latch circuit.
  • a gate signal on the (n+1)th row or the (n ⁇ 1)th row is used for generating a CS signal which is to be supplied from a CS driving circuit on the n-th row.
  • a selection switch (UDSW) is required for selecting a row (the (n+1)th row or the (n ⁇ 1)th row) adjacent to the row (the n-th row) on which the CS signal is generated.
  • wires are required for transmitting (i) a signal for controlling the selection switch and (ii) a gate signal from the adjacent row (the (n+1)th row or the (n ⁇ 1)th row) to the row (n-th row).
  • Such a configuration causes a structure of the CS driving circuit to be complicated, (ii) influences a size of the whole liquid crystal display device, and (iii) prevents space-saving of a region other than a display panel. As a result, a cost of the liquid crystal display device would be increased.
  • the present invention is accomplished in view of the problems, and its object is to provide a display driving circuit and a display driving method for carrying out a CC driving with a simple structure.
  • the display driving circuit of the present invention drives a display panel which includes scan signal lines, data signal lines, pixel electrodes, switching elements, and capacity coupling lines, wherein the scan signal lines turn on and off the switching elements corresponding thereto, and each of the switching elements has (i) one terminal connected with one of the respective pixel electrodes and (ii) another terminal connected with one of the respective data signal lines, and the capacity coupling lines are capacity-coupled with corresponding ones of the pixel electrodes, wherein each of the scan signal lines forms a row together with switching elements connected thereto, pixel electrodes respectively connected to these switching elements, and one of the capacity coupling lines capacity-coupled with these pixel electrodes, the display driving circuit driving the display panel to carry out a gradation display in accordance with electric potentials of the pixel electrodes, the display driving circuit comprising: a scan signal line driving circuit for driving the scan signal lines; a data signal line driving circuit for outputting a data signal which is based on a video signal; and a capacity coupling
  • the display panel driven by the display driving circuit has the above described configuration; According to a typical arrangement, for example, a plurality of pixel electrodes are arranged in a matrix manner in which (i) scan signal lines, switching elements, and capacity coupling lines are arranged along a row direction, and (ii) data signal lines are arranged along a column direction.
  • the terms “row” and “column”, or the terms “horizontal” and “vertical” often indicate a lateral direction and a longitudinal direction, respectively, in the display panel.
  • the directions are not necessarily interpreted as described above, but the lateral-longitudinal relation can be interpreted reversely. Therefore, the terms “row”, “column”, “horizontal”, and “vertical” in the present invention do not limit the directions in particular.
  • the display driving circuit for driving the display panel can have a configuration in which, for example, a horizontal scan period is assigned to each row or a plurality of rows in turn, a switching element provided on any one of the rows is turned on in accordance with a scan signal during the horizontal scan period, and then an electric potential in accordance with a data signal is supplied to a pixel electrode connected to the switching element thus turned on.
  • the display driving circuit shifts, with use of a potential shift signal, electrical potential of a pixel electrode which is capacity-coupled with a capacity coupling line.
  • the potential shift signal has an electric potential which switches, for example, after a horizontal scan period of each of the rows. Directions of the switching (a low level to a high level, or the high level to the low level) are determined in accordance with a polarity of a data signal in a horizontal scan period of each of the rows. With the configuration, so-called CC driving can be realized.
  • CS signal a potential shift signal
  • a scan signal a gate signal
  • a potential shift signal is outputted to a row by the capacity coupling line driving circuit in accordance with an output signal outputted to the row from the scan signal line driving circuit. That is, for example, a potential shift signal (a CS signal) supplied to a capacity coupling line (a CS bus line) on an n-th row is generated in accordance with a scan signal (a gate signal) outputted to a scan signal line (a gate line) on the n-th row. Accordingly, a scan signal line to which a scan signal is supplied is not necessary to be selected, whereby a selection switch, which is conventionally required, is not required. This allows a structure of the capacity coupling line driving circuit to be simplified. Therefore, according to the display driving circuit, CC driving can be carried out with a simple structure.
  • the capacity coupling line driving circuit of the present invention has a configuration in which a potential shift signal is outputted to a row in accordance with an output signal outputted to the row from the scan signal line driving circuit.
  • the output signal is not limited to a scan signal but can be, for example, a setting signal outputted to another stage (e.g., a next stage) from a shift register of the scan signal line driving circuit.
  • the display driving circuit can be a circuit made up of, for example, a single channel transistor, whereby a structure of the circuit can be further simplified. Therefore, in a case where the display driving circuit is made up of the single channel transistor, it is possible to bring about an especially advantageous effect.
  • the capacity coupling line driving circuit outputs the potential shift signal after at least a single horizontal scan period has passed from when the output signal is outputted from the scan signal line driving circuit.
  • the potential shift signal is outputted after at least a single horizontal scan period has passed from when the output signal is outputted from the scan signal line driving circuit. This makes it possible to certainly carry out CC driving.
  • the capacity coupling line driving circuit includes a transfer circuit for securing at least a single horizontal period between when the output signal is outputted from the scan signal line driving circuit and when the potential shift signal is outputted.
  • a potential shift signal can be outputted after at least a single horizontal scan period has passed.
  • the capacity coupling line driving circuit includes: a memory circuit which (i) stores a first signal corresponding to change of a potential level of the output signal outputted from the scan signal line driving circuit and (ii) outputs the first signal to the transfer circuit, the transfer circuit which outputs a second signal which is derived from the first signal with at least a single horizontal scan period, the first signal being outputted from the memory circuit, and a switch circuit which generates the potential shift signal based on a potential level of the second signal outputted from the transfer circuit.
  • a potential shift signal in accordance with an output signal outputted to a row from the scan signal line driving circuit, can be outputted to the row after at least a single horizontal scan period has passed from when the output signal is outputted.
  • the memory circuit includes a first transistor having (i) a first electrode which receives a first input signal and (ii) a control electrode which receives the output signal outputted from the scan signal line driving circuit, a first capacitor element provided between a second electrode of the first transistor and a reference power supply line through which a reference voltage is supplied, a second transistor having (i) a first electrode which receives a second input signal and (ii) a control electrode connected to the control electrode of the first transistor, and a second capacitor element provided between a second electrode of the second transistor and the reference power supply line through which the reference voltage is supplied;
  • the transfer circuit includes a third transistor having (i) a first electrode connected to the second electrode of the first transistor and (ii) a control electrode which receives a clock signal, and a fourth transistor having (i) a first electrode connected to the second electrode of the second transistor and (ii) a control electrode which receives the clock signal; and the switch circuit includes a fifth transistor having (i) a first electrode which receives a first
  • the capacity coupling line driving circuit can be made up of a single channel circuit (N-channel or P-channel). This makes it possible to simplify the structure of the circuit, as compared to, for example, a circuit made up of a CMOS.
  • the capacity coupling line driving circuit causes a potential level of the first signal to be changed from a first potential level to a second potential level when a potential level of the output signal outputted from the scan signal line driving circuit is changed from the first potential level to the second potential level, the second potential level being a potential level at which a transistor is turned on, the capacity coupling line driving circuit outputs the second signal derived from the first signal, after the third transistor is turned on in response to a change in a potential level of the clock signal, and the capacity coupling line driving circuit outputs, as the potential shift signal, a signal at a potential level of the first power supply voltage, at a time when the potential level of the second signal is changed from the first potential level to the second potential level.
  • the first potential level is a potential level at which a transistor is turned off.
  • the second potential level is a potential level at which a transistor is turned on. More specifically, in a case of an N-channel type MOS transistor, the first potential level represents a low (L) level (VSS) and the second potential level represents a high (H) level (VDD). Note that, in a case of a P-channel type MOS transistor, the first potential level represents the high (H) level (VDD) and the second potential level represents the low (L) level (VSS).
  • the capacity coupling line driving circuit causes a potential level of the first signal to be changed from a second potential level to a first potential level when a potential level of the output signal outputted from the scan signal line driving circuit is changed from the first potential level to the second potential level, the second potential level being a potential level at which a transistor is turned on, the capacity coupling line driving circuit outputs the second signal derived from the first signal, after the fourth transistor is turned on in response to a change in a potential level of the clock signal, and the capacity coupling line driving circuit outputs, as the potential shift signal, a signal at a potential level of the second power supply voltage, at a time when the potential level of the second signal is changed from the first potential level to the second potential level.
  • the capacity coupling line driving circuit further includes a booster circuit which (i) increases a potential level of the first signal outputted from the memory circuit and (ii) supplies, to the transfer circuit, the first signal whose potential level is thus increased.
  • a potential level of a signal supplied to the transfer circuit can be increased. This makes it possible to restrain threshold decrease caused due to a writing characteristic of a transistor, whereby a stable electric potential can be supplied to the switch circuit. Accordingly, a stable potential shift signal can be outputted.
  • the memory circuit includes a first transistor having (i) a first electrode which receives a first input signal and (ii) a control electrode which receives the output signal outputted from the scan signal line driving circuit, a first capacitor element provided between a second electrode of the first transistor and a reference power supply line through which a reference voltage is supplied, a second transistor having (i) a first electrode which receives a second input signal and (ii) a control electrode connected to the control electrode of the first transistor, and a second capacitor element provided between a second electrode of the second transistor and the reference power supply line through which the reference voltage is supplied;
  • the booster circuit includes a seventh transistor having (i) a first electrode which receives a predetermined voltage at a second potential level at which a transistor is turned on and (ii) a control electrode connected to the second electrode of the first transistor, a third capacitor element provided between the control electrode of the seventh transistor and a clock signal line through which a clock signal is supplied, an eighth transistor having (i) a first electrode which receives a first
  • a stable potential shift signal can be outputted with a simple structure.
  • the capacity coupling line driving circuit further includes a refresh circuit which causes (i) a potential level of the first signal outputted from the memory circuit to be increased every single horizontal scan period or less frequently than every single horizontal scan period, and (ii) the potential level of the first signal to be maintained during a period in which the potential level is not increased.
  • the potential level of the first signal is increased every single horizontal scan period or less frequently than every single horizontal scan period, whereby an effect of decreasing a voltage due to a leakage current can be reduced. Moreover, during the period in which the potential level is not increased, the potential level of the first signal is maintained. Accordingly, the potential level of the first signal can be stabilized, whereby a stable potential shift signal can be outputted.
  • the memory circuit includes a first transistor having (i) a first electrode which receives a first input signal and (ii) a control electrode which receives the output signal outputted from the scan signal line driving circuit, a first capacitor element provided between a second electrode of the first transistor and a reference power supply line through which a reference voltage is supplied, a second transistor having (i) a first electrode which receives a second input signal and (ii) a control electrode connected to the control electrode of the first transistor, and a second capacitor element provided between a second electrode of the second transistor and the reference power supply line through which the reference voltage is supplied;
  • the refresh circuit includes a ninth transistor having (i) a first electrode which receives a predetermined voltage at a second potential level at which a transistor is turned on and (ii) a control electrode connected to the second electrode of the first transistor, a fifth capacitor element provided between a second electrode of the ninth transistor and a clock signal line through which a clock signal is supplied, a ten
  • a stable potential shift signal can be outputted with a simple structure.
  • the capacity coupling line driving circuit further includes a capacity reduction switch circuit which reduces capacity load on the refresh circuit.
  • the refresh circuit has capacity load. Accordingly, in a case where the refresh circuit is provided on each of the rows, the clock signal is subjected to great load.
  • the capacity reduction switch circuit is provided for reducing the capacity load in the refresh circuit. This makes it possible to reduce clock load.
  • the memory circuit includes the first transistor having (i) the first electrode which receives the first input signal and (ii) the control electrode which receives the output signal outputted from the scan signal line driving circuit, the first capacitor element provided between the second electrode of the first transistor and the reference power supply line through which the reference voltage is supplied, the second transistor having (i) the first electrode which receives the second input signal and (ii) the control electrode connected to the control electrode of the first transistor, and the second capacitor element provided between the second electrode of the second transistor and the reference power supply line through which the reference voltage is supplied;
  • the capacity reduction switch circuit includes a sixteenth transistor having (i) a first electrode which receives a clock signal and (ii) a control electrode connected to the second electrode of the first transistor, and a seventeenth transistor having (i) a first electrode which receives the clock signal and (ii) a control electrode connected to the second electrode of the second transistor,
  • the refresh circuit includes the ninth transistor having (i) the first electrode which receives the predetermined voltage
  • a transistor is provided as a capacity reduction switch circuit between the clock signal line and the refresh circuit. This prevents the clock signal line and a capacitor element of the refresh circuit from being directly connected with each other. Accordingly, for example, in a case where an input signal at the level L is supplied to the transistor of the capacity reduction switch circuit, the transistor is turned off, whereby the clock signal line can be separated off from the capacitor element. This makes it possible to reduce clock load.
  • the capacity coupling line driving circuit further includes a potential stabilizing circuit which fixes the first potential level of at least one of the first signal and the second signal.
  • a potential level (level H or level L) is preferable to be stabilized for outputting a stable potential shift signal.
  • the first signal and the second signal are floated for a certain period during which the first and second signals are easily affected by noise. Accordingly, it would be possible that the potential level is varied.
  • a first potential level of at least one of the first signal and the second signal is fixed.
  • the level L of the first signal and the second signal can be fixed. Accordingly, the potential level of at least one of the first signal and the second signal is fixed, whereby a stable potential shift signal can be outputted.
  • the potential stabilizing circuit includes a thirteenth transistor having (i) a first electrode which receives a reference voltage for the first potential level, (ii) a control electrode connected to the second electrode of the second transistor, and (iii) a second electrode connected to the second electrode of the first transistor, and a fourteenth transistor being arranged in parallel with the first transistor and having (i) a first electrode which receives the reference voltage, (ii) a control electrode connected to the second electrode of the first transistor, and (iii) a second electrode connected to the second electrode of the second transistor.
  • a first potential level of at least one of the first signal and the second signal can be stabilized with a simple structure.
  • the potential stabilizing circuit stabilizes, at the reference voltage, a potential level of a signal outputted from the second transistor; and when a signal outputted from the second transistor is changed from the first potential level to the second potential level, the potential stabilizing circuit stabilizes, at the reference voltage, a potential level of a signal outputted from the first transistor.
  • one of the potential levels (in this case, the first potential level) of the first signal can be stabilized.
  • the capacity coupling line driving circuit further includes a clock booster circuit which (i) increases a potential level of the first signal outputted from the memory circuit and then (ii) supplies the second signal to the switch circuit, the second signal being derived from the first signal whose potential level is thus increased.
  • a potential level of a signal to be supplied to the switch circuit can be increased. This makes it possible to restrain threshold decrease caused due to a writing characteristic of a transistor, whereby a stable electric potential can be supplied to the switch circuit. Accordingly, a stable potential shift signal can be outputted.
  • the clock booster circuit includes a fifteenth transistor having (i) a first electrode which receives a reference voltage, (ii) a control electrode which receives an inversion clock signal, and (iii) a second electrode connected to the control electrodes of the third and fourth transistors, and a seventh capacitor element which has (i) one end connected to a clock signal line through which the clock signal is supplied and (ii) the other end connected to the second electrode of the fifteenth transistor.
  • a potential level of a signal to be supplied to the switch circuit can be increased with a simple structure.
  • the clock booster circuit can be used as a circuit for increasing a potential level of an output signal supplied from the scan signal line driving circuit to the memory circuit (the details are described later).
  • the first electrode of the second transistor and the control electrode of the fifth transistor are connected to each other; and the second signal is supplied, as the second input signal, to the first electrode of the second transistor.
  • the second signal is supplied as the second input signal to the first electrode of the second transistor. This allows the levels H and L to be inputted alternately in each frame. Further, a signal line for the second input signal from the control circuit can be omitted, whereby a circuit structure can be simplified.
  • a display device of the present invention includes any one of the display driving circuits and the display panel.
  • a display driving method of the present invention is a method for driving a display panel which includes scan signal lines, data signal lines, pixel electrodes, switching elements, and capacity coupling lines, wherein the scan signal lines turn on and off the switching elements corresponding thereto, and each of the switching elements has (i) one terminal connected with one of the pixel electrodes and (ii) another terminal connected with one of the data signal lines, and the capacity coupling lines are capacity-coupled with corresponding ones of the pixel electrodes, wherein each of the scan signal lines forms a row together with switching element connected thereto, pixel electrodes respectively connected to these switching elements, and one of the capacity coupling lines capacity-coupled with these pixel electrodes, the display panel being driven to carry out a gradation display in accordance with electric potentials of the pixel electrodes, the display driving method comprising the steps of: (a) driving the scan signal line; (b) outputting a data signal which is based on a video signal; and (c) outputting a potential shift signal
  • the method can bring about an effect of carrying out CC driving with a simple structure, as with the effect described for the display driving circuit.
  • the display device of the present invention is preferable to be a liquid crystal display device.
  • FIG. 1 is a block diagram illustrating a structure of a liquid crystal display device according to an embodiment of the present invention.
  • FIG. 2 is an equivalent circuit diagram illustrating an electrical structure of each pixel of the liquid crystal display device shown in FIG. 1 .
  • FIG. 3 is a block diagram illustrating a schematic structure of a CS driver according to Example 1.
  • FIG. 4 is a circuit diagram illustrating a structure of the CS driver shown in FIG. 3 .
  • FIG. 5 is a timing chart illustrating waveforms of various signals in the CS driver according to Example 1.
  • FIG. 6 is a circuit diagram illustrating a structure of a conventional CS driver made up of a CMOS.
  • FIG. 7 is a circuit diagram illustrating a structure of a CS driver which is obtained by making the CS driver shown in FIG. 4 into a P-channel type.
  • FIG. 8 is a timing chart illustrating waveforms of various signals in the CS driver shown in FIG. 7 .
  • FIG. 9 is a block diagram illustrating a structure of a liquid crystal display device in which the gate driver and the CS driver in the liquid crystal display device shown in FIG. 1 are provided separately.
  • FIG. 10 is a block diagram illustrating a structure of a liquid crystal display device in which a buffer is provided between the gate driver and the CS driver in the liquid crystal display device shown in FIG. 9 .
  • FIG. 11 is a circuit diagram illustrating a structure of a CS driver according to Example 2.
  • FIG. 12 is a circuit diagram illustrating a structure of a CS driver according to Example 3.
  • FIG. 13 is a timing chart illustrating waveforms of various signals in the CS driver according to Example 3.
  • FIG. 14 is a timing chart illustrating waveforms of various signals for explaining a principle of the CS driver according to Example 3.
  • FIG. 15 is a circuit diagram schematically illustrating a relation between a booster circuit and a transfer switch circuit of the CS driver according to Example 3.
  • FIG. 16 is a circuit diagram illustrating a structure of a CS driver according to Example 4.
  • FIG. 17 is a timing chart illustrating waveforms of various signals in the CS driver according to Example 4.
  • FIG. 18 is a circuit diagram illustrating a structure in a case where a transistor is provided between a clock CKB line and a refresh circuit of the CS driver according to Example 4.
  • FIG. 19 is a circuit diagram illustrating a structure of a CS driver according to Example 5.
  • FIG. 20 is a timing chart illustrating waveforms of various signals in the CS driver according to Example 5.
  • FIG. 21 is a circuit diagram illustrating a structure of another CS driver according to Example 5.
  • FIG. 22 is a timing chart illustrating waveforms of various signals in the CS driver shown in FIG. 21 .
  • FIG. 23 is a circuit diagram illustrating a case where a signal LAOn is taken in as a polarity signal CMIB in the CS driver according to the embodiment.
  • FIG. 24 is a block diagram illustrating a structure of a conventional liquid crystal display device which carries out CC driving.
  • FIG. 25 is a timing chart illustrating waveforms of various signals in conventional CC driving.
  • FIG. 26 is a block diagram illustrating a schematic structure of a liquid crystal display device which includes a general gate/CS driving circuit.
  • FIG. 27 is a timing chart illustrating waveforms of various signals in the gate/CS driving circuit shown in FIG. 26 .
  • FIG. 1 is a block diagram illustrating a whole structure of the liquid crystal display device 1
  • FIG. 2 is an equivalent circuit diagram illustrating an electrical configuration of a pixel of the liquid crystal display device 1 .
  • the liquid crystal display device 1 includes: an active matrix liquid crystal display panel 10 (a display panel); a source driver 20 (a data signal line driving circuit); and a gate/CS driver 50 which includes a gate driver 30 (a scan signal line driving circuit) and a CS driver 40 (a capacity coupling line driving circuit). Further, the liquid crystal display device 1 includes a control circuit (not illustrated) which controls the gate driver 30 and the CS driver 40 .
  • the liquid crystal display panel 10 (i) is made up of an active matrix substrate and a counter substrate between which liquid crystal is provided (not illustrated) and (ii) has a plurality of pixels P (see FIG. 2 ) which are arranged in a matrix manner.
  • the liquid crystal display panel 10 includes, on the active matrix substrate: a source bus line 11 (a data signal line); a gate line 12 (a scan signal line); a thin film transistor (hereinafter, referred to as “TFT”) 13 (a switching element); a pixel electrode 14 (a pixel electrode); and a CS bus line 15 (a capacity coupling line). Further, the liquid crystal display panel 10 includes a counter electrode 18 on the counter substrate.
  • a source bus line 11 a data signal line
  • a gate line 12 a scan signal line
  • TFT thin film transistor
  • pixel electrode 14 a pixel electrode
  • CS bus line 15 a capacity coupling line
  • the source bus lines 11 are provided in respective columns so as to be in parallel with each other in a column direction (longitudinal direction).
  • the gate lines 12 are provided in respective rows so as to be in parallel with each other in a row direction (transverse direction).
  • Each of the TFT 13 and the pixel electrode 14 is provided so as to correspond to each intersection of the source bus lines 11 and the gate lines 12 .
  • the TFT 13 includes a source electrode s, a gate electrode g, and a drain electrode d which are connected to the source bus line 11 , the gate line 12 , and the pixel electrode 14 , respectively.
  • a liquid crystal capacitor 17 is defined by the pixel electrode 14 , the common electrode 18 , and the liquid crystal provided between the pixel electrode 14 and the common electrode 18 .
  • a gate signal (scan signal) supplied to the gate line 12 turns on the gate of the TFT 13 , and then a source signal (data signal) supplied from the source bus line 11 is written into the pixel electrode 14 so that the pixel electrode 14 has a electric potential corresponding to the source signal. Further, a voltage corresponding to the source signal is applied to the liquid crystal provided between the pixel electrode 14 and the common electrode 18 , whereby a gradation display can be carried out in accordance with the source signal.
  • the CS bus lines 15 are provided in respective rows so as to be in parallel with each other in a row direction (transverse direction).
  • the CS bus lines 15 are capacity-coupled with the pixel electrodes 14 , respectively, which are provided on the respective rows, whereby a storage capacitor (also called as “auxiliary capacitor”) 16 is formed between each pair of the CS bus line 15 and the pixel electrode 14 .
  • the liquid crystal display panel 10 having the above described configuration is driven by the source driver 20 , the gate driver 30 , CS driver 40 , and the control circuit which controls these components.
  • the rows are scanned in turn by assigning a horizontal scan period to each of the rows in turn so that the horizontal scan period meets an active period (effective scan period) of a vertical scan period which is periodically repeated.
  • the gate driver 30 sequentially supplies gate signals to gate lines 12 for turning on TFTs 13 provided on the gate lines 12 on the rows.
  • the source driver 20 supplies a source signal to each of the source bus lines 11 .
  • the source signal is produced from a video signal which has been (i) supplied to the source driver 20 from outside the liquid crystal display device 1 via the control circuit, (ii) assigned to each of the columns by the source driver 20 , and (iii) boosted, and the like.
  • source signals outputted from the source driver 20 are made to have (i) polarities each of which is inverted in sync with a horizontal scan period of each of the rows and (ii) polarities alternated in adjacent horizontal scan periods on an identical row.
  • polarities of a source signal are inverted between a horizontal scan period on a first row and a horizontal scan period on a second row. Further, polarities of source signals are alternated in every horizontal scan period of a first frame and a second frame on the first row.
  • a line inversion driving method is described as an example just for convenience of explanations. The present invention is not limited to the method but can be applied to, for example, various driving methods such as a frame inversion driving method or a 2H inversion driving method.
  • the CS driver 40 supplies a CS signal (i.e., potential shift signals of the present invention) to each of the CS bus lines 15 .
  • the CS signal has electric polarity which is switched between two values (the electric polarity rises or falls).
  • electric potentials of a CS bus line 15 on each of the rows is switched from one value to the other value.
  • CS signal electric potentials of the potential shift signal
  • the present invention is not limited to this but can be applied to, for example, a configuration in which electric potentials are switched either among three values or within infinitesimal amplitude. Moreover, timing of the switching does not need to be the same as timing of the end of the horizontal scan period on each of the rows, as long as the timing of the switching is after the horizontal scan period.
  • the CS driver 40 shifts an electric potential of a pixel electrode 14 at a time after a horizontal scan period. Note that, in FIG. 1 , a CS driver provided on each of the rows is indicated by a reference numeral “ 40 ′”, and it is assumed that the CS driver 40 includes the CS driver 40 ′ on each of the rows.
  • the control circuit controls the gate driver 30 , the source driver 20 , and the CS driver 40 , so that these circuits output a gate signal, a source signal, and a CS signal, respectively.
  • the CS driver 40 is particularly distinctive among the components included in the liquid crystal display device 1 of the present invention.
  • the CS driver 40 of the present invention generates a CS signal and supplies it to a row in accordance with a gate signal (an output signal from a scan signal line driving circuit) of the row. That is, a CS driver provided on an n-th row (i) takes in a gate signal supplied to a gate line on the n-th row, and then supplies a CS signal to a CS bus line 15 on the n-th row.
  • a CS driver provided on an n-th row i
  • takes in a gate signal supplied to a gate line on the n-th row and then supplies a CS signal to a CS bus line 15 on the n-th row.
  • the following describes details of the CS driver 40 Note that, Example 1 below includes only the above described features. Each of the further Examples 2 through 5 includes other features in addition to the features of Example 1.
  • FIG. 3 is a block diagram illustrating a schematic structure of a CS driver 40 ′ according to Example 1.
  • FIG. 4 is a circuit diagram illustrating a detail of the structure.
  • FIG. 5 is a timing chart illustrating waveforms of various signals in the CS driver 40 ′.
  • a CS driver 40 ′ on an n-th row As an example, as with FIG. 26 , a gate driver 30 and a CS driver 40 ′ on the n-th row are indicated by Gn and CSn, respectively.
  • a row (line) next to the n-th row in a scanning direction (a downward direction in FIG. 1 ) is referred to as an (n+1)th row, and a row previous to the n-th row, that is, a row opposite the (n+1)th row is referred to as an (n ⁇ 1)th row.
  • the gate driver Gn on the n-th row includes inside a shift register (not illustrated).
  • a signal supplied from the shift register is indicated by SROn
  • a signal (gate signal) supplied to a gate line on the n-th row is indicated by GLn.
  • the signal GLn is a signal produced from the signal SROn which has passed through a buffer and has a waveform whose pattern accords with changes in potential levels of the signal SROn.
  • Gate clocks GCK 1 and GCL 2 are supplied from a control circuit and define operation timing of shift registers.
  • Clocks CK and CKB are signals which indicate the gate clocks GCK 1 and GCL 2 , respectively, and are supplied to a gate driver 30 on each of the rows.
  • a single horizontal scan period (1H) is defined by (i) a period from a rising edge of the clock CK to a rising edge of the clock CKB, or (ii) a period from the rising edge of the clock CKB to a rising edge of the clock CK.
  • the CS driver 40 ′ receives the gate signal GLn supplied from the gate driver Gn on the n-th row, the gate clock CKB supplied from the control circuit, and polarity signals CMI (a first input signal), and CMIB (a second input signal).
  • a potential level (level L or level H) of a CS signal CSOUTn is determined, and then the CS signal CSOUTn is supplied to a CS bus line on the n-th row.
  • the CS driver 40 ′ includes a memory circuit 41 , a transfer switch circuit 42 (transfer circuit), and an analogue switch circuit 43 (switch circuit).
  • the memory circuit 41 includes transistors 41 a and 41 b (a first transistor and a second transistor) as switching elements, and capacitors 41 c and 41 d (a first capacitor element and a second capacitor element).
  • the transfer switch circuit 42 includes transistors 42 a and 42 b (a third transistor and a fourth transistor) as transfer switches.
  • the analogue switch circuit 43 includes transistors 43 a and 43 b (a fifth transistor and a sixth transistor).
  • each of the transistors is made up of an N-channel MOS transistor and the CS driver 40 ′ serves as a single channel (N-channel) driving circuit.
  • each of the transistors can be made up of a P-channel MOS transistor and the CS driver 40 ′ can serve as a P-channel driving circuit.
  • the memory circuit 41 includes the capacitors 41 c and 41 d .
  • the capacitors 41 c and 41 d can be omitted.
  • the capacitors 41 c and 41 d can be omitted in the further Examples.
  • the CS driver 40 ′ receives the gate signal GLn on the n-th row, the polarity signals CMI and CMIB, and the clock CKB. Then, the CS driver 40 ′ outputs the CS signal CSOUTn via the memory circuit 41 , the transfer switch circuit 42 , and the analogue switch circuit 43 .
  • the gate driver Gn on the n-th row receives a signal SROn ⁇ 1 supplied from a shift register of a gate driver Gn ⁇ 1 on the (n ⁇ 1)th row, and then (ii) supplies a gate signal GLn to the gate line 12 so as to turn on a TFT on the n-th row.
  • the gate signal GLn is supplied to the CS driver CSn on the n-th row.
  • a signal SROn is supplied from a shift register of the gate driver Gn to a gate driver Gn+1 on a next row (the (n+1)th row).
  • the memory circuit 41 of the CS driver CSn which has received the gate signal GLn from the gate driver Gn takes in a polarity signal CMI in accordance with the gate signal GLn. More specifically, when a potential level of the gate signal GLn is changed from a low level (level L: first potential level) to a high level (level H: second potential level), that is, when the transistor 41 a is turned on, the polarity signal CMI is transferred to the memory circuit 41 , and then the polarity signal CMI is outputted as a signal LAn (a first signal) from the memory circuit 41 . At the time, electric charge is accumulated (stored) in the capacitor 41 c . That is, as shown in FIG.
  • the polarity signal CMI is outputted, and accordingly the signal LAn has a level H.
  • the transistor 41 a is shut off, whereby the polarity signal CMI stops being outputted.
  • the capacitor 41 c in which electric charge is stored allows the signal LAn to maintain a potential level (in this case, the level H) at the time when the transistor 41 a is turned off.
  • the signal LAn maintains the state (the level H) until the potential level of the gate signal GLn is changed from the level H to the level L next time, that is, during a single vertical scan period (1V).
  • the polarity signal CMI is transferred and then outputted, whereby the signal LAn is switched from the level H to the level L. Then, the signal LAn maintains the state (the low level) during another single vertical scan period (1V). Thereafter, the above described process is repeated.
  • the signal LAn outputted from the memory circuit 41 via the process is supplied to the transistor 42 a of the transfer switch circuit 42 , and then outputted as a signal LAOn (a second signal) after a lapse of a single horizontal scan period (1H). More specifically, the transistor 42 a receives a clock CKB by which the transistor 42 a is turned on and off. At timing of a rising edge of the clock CKB, the transistor 42 a is turned on, and then the signal LAn is outputted as the signal LAOn. As described above, the signal LAn outputted from the memory circuit 41 is generated in accordance with the gate signal GLn. Accordingly, the signal LAn is outputted in sync with timing of a clock CK.
  • a period from a rising edge of the clock CK to a rising edge of the clock CKB is defined as 1H. Accordingly, the signal LAn which has been outputted at timing of the rising edge of the clock CK is to be outputted as the signal LAOn at timing of the rising edge of the clock CKB, that is, after a lapse of 1H.
  • the signal LAOn which has been outputted from the transfer switch circuit 42 via the process is supplied to the transistor 43 a of the analogue switch circuit 43 .
  • the analogue switch circuit 43 receives a positive polarity common voltage VCSH and a negative polarity common voltage VCSL.
  • the transistor 43 a is turned on and off in accordance with the signal LAOn. Accordingly, the transistor 43 a (i) is turned on at timing of a rising edge (a level H) of the signal LAOn, and (ii) outputs, while being at the level H, the common voltage VCSH as a CS signal CSOUTn.
  • the polarity signals CMI and CMIB have polarities opposite to each other. Accordingly, the signals LAn and LABn supplied from the memory circuit 41 have respective different potential levels (levels H and L). Similarly, the signals LAOn and the LABOn supplied from the transfer switch circuit 42 have respective different potential levels (levels H and L). Therefore, as shown in FIG. 5 , when one of the signals is at the level H, the other signal is at the level L. This makes it possible to output a CS signal whose electric potential is inverted in each frame.
  • the CS driver 40 of the present invention carries out CC driving by outputting the CS signal CSOUTn in accordance with the gate signal GLn on the row (the n-th row).
  • a switch UDSW in FIG. 26
  • a wire for the switch are not required. This makes it possible to simplify a circuit structure of the CS driver 40 .
  • the CS driver 40 of the present invention can be applied to a circuit structure of a CMOS.
  • the circuit structure of a CMOS also does not require the conventional switch UDSW, whereby a similar effect can be achieved.
  • a single channel circuit structure is preferable. According to the single channel circuit structure, as compared to the circuit structure of a CMOS, manufacturing steps such as a masking step can be omitted, whereby production efficiency can be improved. Accordingly, advantageous effects such as reduction of manufacturing cost can be obtained.
  • the CS driver 40 ′ can be a P-channel driving circuit.
  • FIG. 7 illustrates an example in which the CS driver 40 ′ shown in FIG. 4 is has a configuration of a P-channel type.
  • FIG. 8 is a timing chart illustrating waveforms of various signals in the CS driver.
  • a generally known technique can be used for substituting an N-channel type with a P-channel type. Accordingly, an explanation of a specific method for the substitution is omitted.
  • the CS driver 40 receives a signal as the gate signal GLn supplied from the gate driver 30 .
  • the present invention is not limited to this.
  • a signal supplied to the CS driver 40 can be a signal inside the gate driver 30 , more specifically, the signal can be the signal SROn supplied from the shift register.
  • the configuration can also obtain an effect similar to that obtained in the case where a gate signal is supplied.
  • the gate driver 30 and the CS driver 40 are integrated so as to constitute the gate/CS driver 50 .
  • the present invention is not limited to this.
  • the gate driver 30 and the CS driver 40 can be provided separately.
  • An overall size of the liquid crystal display device 1 can be reduced by providing the gate driver 30 and the CS driver 40 on respective sides of the display panel 10 (see FIG. 9 ).
  • gate clocks GCK 1 and GCK 2 need to be supplied to each of the drivers 30 and 40 from the control circuit. This causes wiring to be complicated. Accordingly, waveform distortion occurs due to wiring load, and the waveform distortion adversely affects operation timing of the drivers 30 and 40 .
  • it is preferable to provide a buffer between the drivers 30 and 40 see FIG. 10 ). This makes it possible to compensate differences in process speed and transfer speed between the drivers 30 and 40 , whereby the waveform distortion can be reduced.
  • the following describes a configuration in which operation of the CS driver 40 is further stabilized, whereby CC driving in the liquid crystal display device 1 is stabilized.
  • FIG. 11 is a circuit diagram illustrating a structure of a CS driver 40 ′ in Example 2.
  • the CS driver 40 ′ in Example includes potential stabilizing circuits 44 and 45 in addition to the components of the CS driver 40 ′ in Example 1.
  • signals LAn and LABn have respective different potential levels (levels H and L).
  • signals LAOn and LABOn have respective different potential levels (levels H and L) (see FIG. 5 ).
  • the signals LAn and LAOn are at the level H
  • the signals LABn and LABOn are at the level L.
  • the potential stabilizing circuits 44 and 45 are provided for stabilizing the potential levels.
  • the potential stabilizing circuit 44 includes transistors 44 a and 44 b (thirteenth and fourteenth transistors).
  • the transistor 44 a is arranged so that a control electrode and a second electrode thereof are connected to a second electrode of the transistor 41 b and a second electrode of the transistor 41 a , respectively.
  • the transistor 44 b is arranged so that a control electrode and a second electrode thereof are connected to the second electrode of the transistor 41 a and the second electrode of the transistor 41 b , respectively.
  • the potential stabilizing circuit 45 includes transistors 45 a and 45 b which are connected to second electrodes of the transistors 42 a and 42 b in a similar way to the transistors 44 a and 44 b (see FIG. 11 ).
  • the transistor 44 b is turned on, whereby a potential level of the signal LABn becomes a reference voltage (VSS) and is fixed at the level L (the first potential level).
  • the transistor 45 b is turned on, whereby a potential level of the signal LAOBn becomes a reference voltage (VSS) and is fixed at the level L.
  • FIG. 12 is a circuit diagram illustrating a structure of a CS driver 40 ′ in Example 3.
  • FIG. 13 is a timing chart illustrating waveforms of various signals in the CS driver 40 ′.
  • the CS driver 40 ′ in Example 3 includes booster circuits 46 ( 46 a and 46 b ) in addition to the components of the CS driver 40 ′ in Example 2.
  • the CS drivers 40 ′ in Examples 1 and 2 indicate in detail, when the transistor 41 a is turned on and the polarity signal CMI at the level H is taken in, the electric potential of the signals LAn is decreased by a threshold amount of voltage (Vth) (hereinafter, this phenomenon is referred to as “threshold decrease”) due to a writing characteristic of the transistor. Then, a voltage of the decreased beyond threshold signal LAn is further decreased due to distribution property of electric charge between capacitance of the capacitor 41 c (see FIG. 4 ) and load capacitance of the transistor 43 a in the analogue switch circuit 43 (see FIG.
  • the signal LAOn in FIG. 14 illustrates a state where the voltage-decreased signal LAn is transferred after a lapse of 1H, and then the signal LAOn is affected by the voltage decrease of the signal LAn.
  • the CS driver 40 ′ in Example 3 includes the booster circuits 46 ( 46 a and 46 b ).
  • the booster circuit 46 a includes: a capacitor 461 a (a third capacitor element) which increases an electric potential of the signal LAn outputted from the memory circuit 41 ; and a transistor 462 a (a seventh transistor) which (i) is turned on and off in accordance with the signal LAn whose potential level has been increased and (ii) receives a predetermined voltage (VDD) as input data.
  • the booster circuit 46 b includes a capacitor 461 b (a fourth capacitor element) and a transistor 462 b (an eighth transistor).
  • each of the booster circuits 46 is provided in a previous stage with respect to the transfer switch circuit 42 , so that a data line (an output line of the memory circuit 41 ) and an output line of the transfer switch circuit 42 are not directly connected with each other but are connected via a gate.
  • FIG. 15 is a circuit diagram schematically illustrating a relation between the booster circuit 46 and the transfer switch circuit 42 .
  • memory data which is based on the signal LAn outputted from the memory circuit 41 , is inputted as a signal only for turning on and off the transistor 462 a but the memory data is not outputted as transfer data. This makes it possible to prevent the voltage decrease caused due to the distribution property of electric charge.
  • Example 3 operation of the CS driver 40 ′ in Example 3 with reference to FIG. 12 and a timing chart shown in FIG. 13 . Note that, regarding components which operate in the same way as those in Examples 1 and 2, explanations thereof are omitted.
  • the electric potential of the signal LAn which is outputted when the transistor 41 a is turned on is decreased by a threshold amount of voltage (Vth).
  • Vth threshold amount of voltage
  • This decrease in the electric potential of the signal LAn is caused due to a writing characteristic of the transistor 41 a .
  • the signal LAn is supplied to the booster circuit 46 a , and then potential level of the signal LAn is increased at timing of the rising edge of the clock CKB (in the present embodiment, the third potential level is lager than the second potential level because the transistor is made up of an N-channel MOS transistor).
  • the potential level of the signal LAn is increased in every 1H in sync with a cycle of the clock CKB.
  • the potential level of signal LAn is increased from the second potential level to the third potential level.
  • the signal LAn is supplied, as a gate signal, to the transistor 462 a so that the transistor 462 a is turned on and off.
  • a signal Xn is an output signal outputted from the booster circuit 46 a .
  • the signal Xn whose electric potential is further decreased beyond threshold from the predetermined voltage (VDD; the second potential level) is outputted.
  • VDD the predetermined voltage
  • the signal Xn is supplied to the transfer switch circuit 42 . Further, after a lapse of 1H, the signal Xn is supplied to the analogue switch circuit 43 from the transfer switch circuit 42 , as a signal LAOn whose electric potential has been decreased beyond threshold from the voltage VDD in every 1H.
  • a voltage of the signal LAOn in Example 3 is not so much decreased from the voltage VDD as that of the signal LAOn (see FIG. 14 ) in Examples 1 and 2 is. This makes it possible to output a stable CS signal.
  • FIG. 16 is a circuit diagram illustrating a structure of a CS driver 40 ′ in Example 4.
  • FIG. 17 is a timing chart illustrating waveforms of various signals in the CS driver 40 ′.
  • the CS driver 40 ′ in Example 4 includes refresh circuits 47 ( 47 a and 47 b ) in addition to the components of the CS driver 40 ′ in Example 3.
  • a potential level of the signal LAn in the memory circuit 41 is maintained during the period 1V.
  • a leakage current is inevitably occurred, whereby the potential level is decreased as time passes.
  • the potential level of the signal LAn is gradually decreased due to an effect of the leakage current.
  • a potential level at the beginning of the period 1V differs at the end of the period 1V. This prevents stable voltage supply, and as a result, the CS signal cannot be outputted stably.
  • This phenomenon can be occurred in any of Examples 1 through 3.
  • the voltage decrease of the signal LAn caused due to the leakage current is illustrated in FIG. 13 (indicated by dotted circles on the signal LAn in FIG. 13 ). As indicated by the signal LAn, it is seen that the potential level is decreased as time passes.
  • the CS driver 40 ′ in Example 4 includes refresh circuits 47 ( 47 a and 47 b ) for restraining the voltage decrease caused due to the leakage current.
  • the refresh circuit 47 a is turned on and off by the signal LAn outputted from the memory circuit 41 .
  • the refresh circuit 47 a includes: a transistor 471 a (a ninth transistor) which receives a predetermined voltage (VDD) as input data; a capacitor 472 a (a fifth capacitor element) which increases a potential level of a signal outputted from the transistor 471 a ; and a transistor 473 a (a tenth transistor) which (i) is turned on and off by the signal whose potential level has been increased and (ii) receives the predetermined voltage (VDD) as input data.
  • the refresh circuit 47 b includes: a transistor 471 b (an eleventh transistor); a capacitor 472 b (a sixth capacitor element); and a transistor 473 b (a twelfth transistor).
  • each of the refresh circuits 47 is provided in a previous stage with respect to the transfer switch circuit 42 .
  • Example 4 operation of the CS driver 40 ′ in Example 4 with reference to FIG. 16 and a timing chart shown in FIG. 17 . Note that, regarding components which operate in the same way as those in Examples 1 through 3, explanations thereof are omitted.
  • an electric potential of the signal LAn which is outputted when the transistor 41 a is turned on is decreased by a threshold amount of voltage (Vth) due to a writing characteristic of the transistor 41 a (see a waveform (i) of the signal LAn in FIG. 17 ).
  • the signal thus decreased beyond threshold is supplied to the refresh circuit 47 a , and then the potential level of the signal is decreased beyond threshold again due to the transistor 471 a (see a waveform (ii) of the signal LA′n in FIG. 17 ).
  • the potential level of the signal thus decreased beyond threshold again is increased at timing of the rising edge of the clock CKB (see a waveform (iii) of the signal LA′n in FIG.
  • the signal whose potential level has been increased is outputted from the refresh circuit 47 a as a signal LA′n.
  • the signal whose potential level has been increased turns on the transistor 473 a , and accordingly, the capacitor 41 c is charged with the predetermined voltage (VDD) (see a waveform (iv) of the signal LAn in FIG. 17 ).
  • the clock CKB has a potential level (the third potential level) which is larger than a potential level (the second potential level) of the voltage VDD.
  • the operation of charging the capacitor 41 c is synchronized with operation timing of the clock CKB. Accordingly, the charging operation is carried out (i) in every 1H and (ii) during the clock CKB is being at the level H. As a result, the potential level of the signal LAn is increased to the voltage VDD in every 1H.
  • the signal LAn which has been outputted at the potential level of the voltage VDD maintains the potential level during a period between a falling edge and a next rising edge of the clock CKB (see a waveform (v) of the signal LAn in FIG. 17 ).
  • the potential level of the signal LA′n which is outputted in the period is decreased beyond threshold due to the transistor 471 a (see a waveform (vi) of the signal LA′n in FIG. 17 ).
  • the potential level of the signal LA′n is increased again, whereby the capacitor 41 c is charged with the predetermined voltage (VDD). Thereafter, the process is repeated.
  • the signal LA′n is supplied for turning on and off the transistor 462 a in the booster circuit 46 a of Example 3 (see FIG. 12 ).
  • the capacitor 41 c is charged with electric charge in every 1H so that the potential level of the signal LAn is increased to a potential level larger than that of the voltage VDD. Accordingly, a period during which the potential level is maintained can be reduced from the period 1V. This makes it possible to restrain voltage decrease caused due to a leakage current. Therefore, a stable potential level can be maintained during the period 1V (one frame), whereby a CS signal can be outputted more stably.
  • the clock signal is supplied as a two-phase signal, whereby the refresh circuit 47 a increases the potential level in every 1H.
  • the clock signal is inputted with, for example, three-phase, four-phase, or further, the potential level is increased less frequently than every 1H.
  • Each of the refresh circuits 47 of the Example 4 is subjected to load capacitance (e.g., 200 fF). Therefore, in a case where the refresh circuits 47 are provided on each of the rows, a clock CKB receives large load.
  • load capacitance e.g. 200 fF
  • transistors 474 a and 474 b as a capacity reduction switch circuit 474 are provided between the clock CKB line and each of the refresh circuits 47 . This prevents the clock CKB line and each of the capacitors 472 b from being directly connected with each other.
  • FIG. 19 is a circuit diagram illustrating a structure of a CS driver 40 ′ in Example 5.
  • FIG. 20 is a timing chart illustrating waveforms of various signals in the CS driver 40 ′.
  • the CS driver 40 ′ in Example 5 includes a transfer clock booster circuit 48 (clock booster circuit) in addition to the components of the CS driver 40 ′ in Example 4.
  • threshold decrease is occurred due to a writing characteristic of the transistor 42 a in the transfer switch circuit 42 . More specifically, for example, as indicated by the waveform of the signal LAOn in FIG. 17 , when the transistor 42 a (see FIG. 16 ) is turned on and the voltage VDD of the signal Xn is taken in, an electric potential of the signal LAOn is decreased by a threshold amount of voltage (Vth) due to a writing characteristic of the transistor. This prevents a stable electric potential from being supplied to the analogue switch circuit 43 , whereby stabilization in outputting a CS signal cannot be achieved.
  • the CS driver 40 ′ of Example 5 includes a transfer clock booster circuit 48 for preventing the threshold decrease in the transfer switch circuit 42 .
  • the transfer clock booster circuit 48 is turned on and off by a clock CK.
  • the transfer clock booster circuit 48 includes: a transistor 48 a fifteenth transistor) which receives a reference voltage (VSS) as input data; and a capacitor 48 b (a seventh capacitor element) which increases, by a clock CKB, a potential level of a signal outputted from the transistor 48 a.
  • the transfer clock booster circuit 48 is provided in a previous stage with respect to the transfer switch circuit 42 , so that the transistor 42 a in the transfer switch circuit 42 is turned on and off by a signal outputted from the transfer clock booster circuit 48 .
  • Example 5 it is assumed that the clocks CK and CKB have amplitude of 15 V ( ⁇ 5 V through +10 V), the reference voltage (VSS) is 0 V, and the predetermined voltage (VDD) is 10 V.
  • the reference voltage (VSS) is written in the capacitor 48 b , whereby a voltage of the capacitor 48 b becomes 0 V.
  • the amplitude 15 V of the clock CKB (a signal CKB′) is outputted at timing of a rising edge of the clock CKB.
  • the signal CKB′ at 15 V is supplied to the transistor 42 a .
  • This allows the transistor 42 a to be turned on with a voltage (CKB′: 15 V) which is larger than that of the signal Xn (Xn in FIG. 17 : VDD (10 V)) serving as the input data to the transistor 42 a . Therefore, the voltage VDD (10 V) can be outputted as a signal LAOn from the transfer switch circuit 42 , without being decreased beyond threshold.
  • the signal outputted from the transfer clock booster circuit 48 is indicated as the signal CKB′ in the timing chart shown in FIG. 20 .
  • a potential level of the signal CKB′ is increased to a voltage (15 V: the third potential level) which is larger than the voltage VDD (10 V: the second potential level) at timing of the rising edge of the clock CKB.
  • VDD the voltage of the voltage
  • This operation is carried out in sync with the timing of the clock CKB, whereby the electric potential is increased in every 1H. This makes it possible to stabilize the electric potential of the signal LAOn. Accordingly, a signal with a stable electric potential can be supplied to the analogue switch circuit 43 , whereby the CS signal can be outputted stably.
  • the transfer clock booster circuit 48 can be applied to the transistors 41 a and 41 b of the memory circuit 41 .
  • FIG. 21 is a circuit diagram illustrating a structure of another CS driver 40 ′ in Example 5.
  • FIG. 22 is a timing chart illustrating waveforms of various signals in the CS driver 40 ′.
  • the transfer clock booster circuit 48 in the another CS driver 40 ′ is turned on and off by the clock CK.
  • the transfer clock booster circuit 48 includes: a transistor 48 a which receives a reference voltage (VSS) as input data; and a capacitor 48 b which increases, by a gate signal GLn, a potential level of a signal outputted from the transistor 48 a .
  • the clock CK and the gate signal GLn has amplitude of 15 V ( ⁇ 5 V through +10 V), the reference voltage (VSS) is 0 V, and the electric potential of the polarity signal CMI is 10 V.
  • the signal outputted from the transfer clock booster circuit 48 is indicated as a signal GLOn in the timing chart shown in FIG. 22 .
  • a potential level of the signal GLOn is increased to a voltage (15 V) which is larger than the voltage VDD (10 V) at timing of the rising edge of the clock CK.
  • This allows the transistor 41 a to be turned on by a voltage (GLOn: 15 V) which is larger than that of the signal CMI (10 V) serving as input data to the transistor 41 a .
  • the signal CMI (10 V) is outputted as a signal LAn without being decreased beyond threshold (see a dotted-circled part in FIG. 22 ). This makes it possible to stabilize operation thereafter.
  • the transistors 41 a and 41 b are turned on, the polarity signals CMI and CMIB have polarities opposite to each other. Accordingly, the signals LAOn and LABOn which are outputted from the transfer switch circuit 42 have respective different potential levels (levels H and L). Therefore, when one of the signals is at the level H, the other is outputted at the level L. This allows CS signals to be outputted whose potential levels are inverted in each frame. According to the configuration, for example, when a polarity signal CMI at the level H is supplied to the CS driver 40 ′ for generating a CS signal at the level H, a signal LAOn is supplied at the level L to the transistor 43 a of the analogue switch circuit 43 .
  • a polarity signal (CMIB) at the level L is required for generating a CS signal at the level L.
  • the signal LAOn can be taken in as the polarity signal CMIB. This makes it possible to input signals at the respective levels H and L alternately in each frame. Accordingly, a signal line for the signal CMIB from the control circuit can be omitted, whereby a structure of the circuit can be simplified.
  • switch elements in the CS driver can be made up of D-latch circuits.
  • a signal which is outputted from the gate driver used in the CS driver of the present invention can be the above described gate signal or a setting signal outputted from the shift register of the gate driver to another stage (e.g., a next stage).
  • the capacity coupling line driving circuit outputs a potential shift signal to a row on which the capacity coupling line driving circuit is provided.
  • the potential shift signal is outputted in accordance with an output signal outputted to the row from the scan signal line driving circuit.
  • the present invention can be particularly suitably applied to driving of an active matrix liquid crystal display device.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
US12/734,363 2007-12-28 2008-09-02 Display driving circuit having a memory circuit, display device, and display driving method Expired - Fee Related US8547368B2 (en)

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EP2226788A1 (en) 2010-09-08
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