US7949977B2 - Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium - Google Patents
Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium Download PDFInfo
- Publication number
- US7949977B2 US7949977B2 US11/882,293 US88229307A US7949977B2 US 7949977 B2 US7949977 B2 US 7949977B2 US 88229307 A US88229307 A US 88229307A US 7949977 B2 US7949977 B2 US 7949977B2
- Authority
- US
- United States
- Prior art keywords
- noise
- simultaneous switching
- setting information
- user setting
- pins
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Definitions
- the present invention relates to a technique of estimating a simultaneous switching noise (SSN) (also referred to as simultaneous switching output (SSO) noise) caused by simultaneous switching of signals input into and output from a plurality of pins in a semiconductor device.
- SSN simultaneous switching noise
- SSO simultaneous switching output
- An FPGA Field Programmable Gate Array
- An FPGA is a semiconductor device that allows a user to set any pin arrangement, circuit configuration, and the like.
- ground bouncing occurring between reference levels of a ground pin in a device package and the ground of an internal die in the device has been one of the main causes of erroneous switching in high-speed devices.
- the erroneous switching can be caused by only one signal line; thus, when there is a plurality of lines for signals that switch simultaneously, any noise that they can cause is a serious problem.
- Patent Document 1 discloses a technique of suppressing noise caused in branch power source lines.
- a plurality of logic cells connected to one branch power source line are categorized into one arrangement of a logic cell group, the value of simultaneous switching noise that is expected to be caused by the simultaneous switching of a plurality of logic cell groups is obtained on the basis of a noise value for each arrangement of a logic cell, and the delay time of a plurality of delay adjustment buffers inserted into the logic cell group is adjusted on the basis of the comparison result between the total value of noise limitation value of the plurality of logic cell groups constituting the logic cell group arrangement and the expected simultaneous switching noise value.
- a method of estimating simultaneous switching noise is a method of estimating simultaneous switching noise that is realized by a computer executing a process of estimating simultaneous switching noise caused by the simultaneous switching of signals input into and output from a plurality of pins that can be set by a plurality of sets of user signal setting information in a semiconductor device, comprising: a number of simultaneously switching signals calculation step for each set of user setting information in which the number of simultaneously switching signals is calculated on the basis of the user setting information of pins arranged in an area of the neighborhood of a process-target pin; a difference calculation step in which a difference is calculated between instances of noise respectively corresponding to an initial point and a terminal point in a range of the number of simultaneously switching signals calculated for each set of user setting information on the basis of caused noise information expressing a
- a method of estimating simultaneous switching noise according to a second aspect of the present invention is a simultaneous switching noise estimation method for estimating, by using a computer, simultaneous switching noise that is noise expected to be caused when input/output signals set by user setting information are respectively input into and output from a plurality of pins included in a semiconductor device, said method comprising: a number calculation step of calculating, on the basis of a pin selected from the plurality of pins to be the process-target pin, the number of other pins that are to be used for the estimation of the simultaneous switching noise as the number of simultaneously switching signals; and a noise calculation step of calculating simultaneous switching noise corresponding to the number of simultaneously switching signals calculated in the number calculation step, by referring to caused noise information stored in a storage unit in the computer to express a relationship between the number of simultaneously switching signals and noise expected to be caused.
- a simultaneous switching noise estimation device is a simultaneous switching noise estimation device that executes a process of estimating the simultaneous switching noise caused by the simultaneous switching of signals input into and output from a plurality of pins that can be set by a plurality of sets of user setting information in a semiconductor device, comprising: a number of simultaneously switching signals calculation unit for calculating the number of simultaneously switching signals for each set of user setting information on the basis of the user setting information of pins arranged in an area of the neighborhood of a process-target pin; a storage unit for storing caused noise information expressing a relationship between the number of simultaneously switching signals and the noise caused by the simultaneously switching signals for each set of user setting information; a difference calculation unit for calculating the difference between instances of noise respectively corresponding to an initial point and a terminal point in a range of the number of simultaneously switching signals calculated for each set of user setting information on the basis of the caused noise information stored in the storage unit for each set of user setting information; and a noise sum calculation unit for calculating the simultaneous switching noise in the process-target pin by calculating
- a storage medium is a storage medium that can be accessed by a computer performing a process of estimating simultaneous switching noise caused by the simultaneous switching of input/output signals of a plurality of pins that can be set by a plurality of sets of user setting information in a semiconductor device, said storage medium recording a program for realizing: a number of simultaneously switching signals calculation function by which the number of simultaneously switching signals is calculated for each set of user setting information on the basis of the user setting information of the pins arranged in an area in the neighborhood of a process-target pin; a difference calculation function by which a difference is calculated between instances of noise respectively corresponding to an initial point and a terminal point in a range of the number of simultaneously switching signals calculated for each set of user setting information on the basis of a caused noise information expressing a relationship between the number of simultaneously switching signals and the noise caused by the simultaneously switching signals for each set of user setting information; and a noise sum calculation function by which the simultaneous switching noise in the process-target pin is calculated by calculating the sum of the differences between the instances of
- the number of specified pins are calculated as the number of simultaneously switching signals, caused noise information expressing a relationship between the number of simultaneously switching signals and noise caused by the simultaneously switching signals (noise expected to be caused) is referred to, the difference between the instances of noise corresponding to the numbers of the simultaneously switching signals is calculated, and the difference is integrated, thereby the simultaneous switching noise is calculated.
- other pins are specified and the simultaneous switching noise is estimated on the basis of the specified other pins, and thereby the estimation can be performed in a short time.
- Other pins are categorized into a plurality of groups on the basis of the magnitude of the simultaneous switching noise caused, the degree of influence of the noise, the input/output signals being input and output, and the like. Further, the caused noise information is created for each group. Thereby, the difference (noise) is obtained for each group, the obtained difference is integrated in order to calculate the simultaneous switching noise, and accordingly it is possible to estimate the simultaneous switching noise more accurately.
- the estimation of the simultaneous switching noise can be performed in a short time, and thus it is possible to assist in the quick design/production of semiconductor devices or PCBs that include semiconductor devices.
- the simultaneous switching noise that is actually caused changes in accordance with changes in the design of one of the semiconductor devices and the PCB. Accordingly, when there is a fault in the design of one of the semiconductor devices and the PCB, that fault can be compensated by the design of the one not involving the fault. This compensation can be performed promptly because the estimation of the simultaneous switching noise can be performed in a short time.
- FIG. 1A shows a configuration of a simultaneous switching noise estimation device according to a first embodiment of the present invention
- FIG. 1B is a block diagram showing a configuration of a simultaneous switching noise estimation device according to a second embodiment of the present invention
- FIG. 2 is a graph illustrating a relationship between the number of simultaneous switching signals and the noise that is expected to be caused expressed by caused noise information for each IO user setting information;
- FIG. 3 shows an example of categorization
- FIG. 4 is a graph illustrating a relationship between the number of simultaneously switching signals and the noise expressed by the caused noise information of one of IO user setting information
- FIG. 5 shows a data configuration of the pin information storage unit shown in FIG. 1B ;
- FIG. 6 is a flowchart of the simultaneous switching noise calculation process
- FIG. 7 shows an example of pin arrangement in the neighborhood of the target pin on the FPGA chip
- FIG. 8 is a graph illustrating a method of calculating the simultaneous switching noise on the target pin shown in FIG. 7 ;
- FIG. 9 shows an example of a storage medium.
- FIG. 10A shows an electric current flowing between PCBs and a semiconductor device
- FIG. 10B shows a space in which a magnetic flux is generated by a return current that is caused to flow by the provision of an IO signal to a pin;
- FIG. 11 shows a method of grouping in a fourth embodiment
- FIG. 12 is a flowchart for designing for a case when the design of a semiconductor device and the design of PCBs are related.
- the present invention relates to a technique of simply (promptly) estimating the simultaneous switching noise caused by the simultaneous switching of a plurality of input and output signals of a plurality of pins included in a semiconductor device.
- FIG. 1A shows a configuration of a simultaneous switching noise estimation device according to a first embodiment of the present invention.
- the simultaneous switching noise estimation device includes a pin information storage unit 1 , a number of simultaneously switching signals (the number of pins) calculation unit 2 , a noise difference calculation unit 3 , a number of simultaneously switching signals/noise storage unit 4 , and a noise sum calculation unit 5 .
- the pin information storage unit 1 stores pin arrangement information and information that is set by a user about the input/output (IO) signals of the pins (hereinafter, referred to as “IO user setting information”) of the semiconductor device that is to be analyzed.
- the IO user setting information is information that can be set by a user about the IO signals such as the standard of the IO signals (LVTTL, LVCMOS, HSTL, and the like), the output current value (12 mA, 8 mA, 4 mA, or the like), the through rate (FAST/SLOW), and the like.
- the number of simultaneously switching signals calculation unit 2 calculates the number of simultaneously switching signals for each set of IO user setting information on the basis of the pin arrangement information on an area around a pin that is to be analyzed (process-target pin) and on the basis of the IO user setting information on these pins.
- the number of simultaneously switching signals/noise storage unit 4 stores information expressing the relationship (relation function, hereinafter referred to as “caused noise information”) between the number of simultaneously switching signals and the noise caused by the simultaneously switching signals for each set of IO user setting information.
- the noise difference calculation unit 3 associates, with the range of the number of simultaneously switching signals in the caused noise information, the number of pins (the number of simultaneously switching signals) calculated for the IO user setting information on the basis of the caused noise information stored for each set of IO user setting information stored in the number of simultaneously switching signals/noise storage unit 4 in order to calculate the difference between the instances of noise that respectively correspond to the initial point and the terminal point in the range.
- the noise sum calculation unit 5 calculates the simultaneous switching noise caused in the pin that is to be analyzed by calculating the sum of the differences between the instances of noise calculated for the respective sets of IO user setting information.
- the simultaneous switching noise (amount) that is expected to be caused in the pins as the process targets is obtained by defining the method of extracting other pins that have to be considered for the noise estimation, and the relationship between the number of pins (the number of simultaneously switching signals) and the noise expected to be caused before the obtainment. Thereby, the noise can be estimated quickly.
- FIG. 1B is a block diagram showing a configuration of a simultaneous switching noise estimation device according to a second embodiment of the present invention.
- a simultaneous switching noise estimation device 10 includes a pin information storage unit 11 , the number of simultaneously switching signals (the number of pins) calculation units 121 , 122 , and 123 , initial point position calculation units 131 , 132 , and 133 , the number of simultaneously switching signals/noise storage unit 14 , and a noise calculation unit 15 .
- the pin information storage unit 11 stores pin arrangement information for each pin of a semiconductor device that is to be analyzed and the IO user setting information as pin information.
- the number of simultaneously switching signals calculation unit 12 extracts the pin arrangement information and the IO user setting information of pins arranged in an area for at most eight pins, that are the closest to the target pin (the pins included in this area are referred to as the pins included in a group 1 ) by using the pin information of the target pin, and the number of pins for each set of IO user setting information, i.e., the number of simultaneously switching signals, is calculated on the basis of the extracted information.
- the number of simultaneously switching signals calculation unit 12 2 extracts the pin arrangement information and the IO user setting information of the pins arranged in an area around the above area that includes at most sixteen pins (the pins included in this area are referred to as the pins included in group 2 ) for at most the closest eight pins by using the pin information of the target pin, and the number of pins in group 2 and for each set of IO user setting information is calculated on the basis of the extracted information.
- the number of simultaneously switching signals calculation unit 12 3 extracts the IO user setting information and the pin arrangement information for at most twenty-four pins arranged in an area around above area that includes at most sixteen pins (the pins included in this area are referred to as the pins included in group 3 ) by using the information of the target pin, and the number of pins for each set of IO user setting information in the area including the at most twenty-four pins is calculated on the basis of the extracted information.
- the initial point position calculation units 13 1 , 13 2 , and 13 3 receive at least one set of information that includes the IO user setting information and the number of pins from the number of simultaneously switching signals calculation units 12 1 , 12 2 , and 12 3 respectively, and adds, to the received set of information, the initial point position corresponding to the number of pins, i.e., corresponding to the number of simultaneously switching signals. Then, the initial point position calculation units 13 1 , 13 2 , and 13 3 respectively output, to the noise calculation unit 15 in a later stage, a set of data including the IO user setting information, the number of pins, and the initial point position.
- the initial point position is the range width of the number of simultaneously switching signals calculated for each set of user setting information of input/output signals.
- the initial point position calculation unit 13 calculates the number of pins for each set of IO user setting information in the area including the eight pins that are the closest to the target pin, i.e., calculates the initial point position corresponding to the number of simultaneously switching signals for each set of IO user setting information.
- the initial point position calculation unit 132 calculates the number of pins for each set of IO user setting information in the area including the sixteen pins that are the second closest to the target pin, i.e., calculates the initial point position that is recognized as the number of simultaneously switching signals.
- the initial point position calculation unit 133 calculates the initial point position used for causing the number of pins for each set of IO user setting information in the area including the twenty-four pins that are the third closest to the target pin to correspond to the number of simultaneously switching signals.
- the number of simultaneously switching signals/noise storage unit 14 stores the caused noise information that expresses the relationship between the number of simultaneous switching signals and the noise that is expected to be caused by the simultaneous switching for each set of IO user setting information.
- the noise calculation unit 15 refers to the caused noise information stored in the number of simultaneously switching signals/noise storage unit 14 , assumes the number of pins calculated for each set of IO user setting information (a, b, and c in FIG. 2 ) and the initial point position (zero, a, and a+b in FIG. 2 ) to be the number of simultaneously switching signals, and calculates the difference between the noise corresponding to the “the number of pins+the initial point position” and the noise corresponding to the initial point position.
- the number of simultaneously switching signals/noise storage unit 14 also calculates the simultaneous switching noise of the target pins by calculating the sum of the differences between the instances of noise calculated for the respective sets of IO user setting information.
- FIG. 2 is a graph illustrating a relationship between the number of simultaneous switching signals and the noise expected to be caused expressed by the caused noise information; the caused noise information (graph) for each set of IO user setting information is stored in the number of simultaneous switching signals/noise storage unit shown in FIG. 1B .
- the horizontal axis represents the number of simultaneously switching signals, and the vertical axis represents the noise expected to be caused (specifically, for example, the variation amount of the voltage level, the voltage ratio between the IO signal and the noise expected to be caused, or the like; here, the example of the variation amount [V] of the voltage level is used).
- IO user setting information A is information used for recognizing a combination of the standard of an IO signal, an output current value, and a through rate
- IO user setting information B is information used for recognizing another combination of the standard of an IO signal, an output current value, and a through rate.
- the pins located in the neighborhood of the target pin are categorized into a plurality of groups in accordance with the degrees (coupling coefficient) to which these pins influence the target pin (the distances between these pins and the target pin).
- the caused noise information for each IO user setting information has, as the actually measured data, data for the simultaneous switching noise with respect to the total value of the number of pins included in each group and included in the groups closer to the target pin than the group itself (the number of simultaneously switching signals corresponding to the total value).
- the eight pins shown in area 22 around the target pin shown in area 21 are categorized into the pins included in group 1
- the sixteen pins shown in area 23 in which is the area around the above area including the eight pins are categorized into the pins included in group 2
- the twenty-four pins shown in area 24 which is the area around the above area including sixteen pins are categorized into the pins included in group 3 in FIG. 3 .
- the total value of the number of pins included in group 1 is eight
- the simultaneous switching noise data is acquired.
- the data of the simultaneous switching noise is acquired also when the twenty-four pins consisting of the eight pins in group 1 and the sixteen pins in group 2 have common IO user setting information and the IO signals are switched in accordance with the same setting information.
- the data of the simultaneous switching noise is acquired also when the forty-eight pins consisting of the eight pins in group 1 , the sixteen pins in group 2 , and the twenty-four pins in group 3 have the common IO user setting information and the IO signals are switched in accordance with the same setting information.
- the caused noise information having the contents shown in FIG. 4 is obtained with IO user setting information by interpolating the data acquired as above (the number of simultaneously switching signals and the simultaneous switching noise).
- the respective total numbers of simultaneously switching signals each corresponding to the total value of the number of pins included in each group and included in the groups closer to the target pin than the group itself are represented by G 1 , by G 1 +G 2 , and by G 1 +G 2 +G 3 instead of 8, 8+16, and 8+16+24 because the pins may be categorized for example on the basis of the distances between the pins on a smaller scale.
- FIG. 2 will be explained again.
- the value a on the axis of the number of simultaneous switching signals (the number of SW) “a” represents the number of pins having the IO user setting information A in a group.
- the value b on the axis of the number of simultaneous switching signals (the number of SW) “b” represents the number of pins having the IO user setting information B in that group.
- the value c on the simultaneous switching signals (the number of SW) “c” represents the number of pins having the IO user setting information C in that group.
- the largest noise with respect to the number of simultaneously switching signals is caused with the IO user setting information A; the intermediate amount of noise is caused with the IO user setting information B; and the smallest noise with respect to the number of simultaneously switching signals is caused with the IO user setting information C.
- the noise (Noise_A) corresponding to the number of pins (a) of the IO user setting information A causing the largest noise with respect to the number of simultaneously switching signals is obtained as the noise from the pins of the IO user setting information A.
- the difference (Noise_B) between the noise of the caused noise information of the IO user setting information B corresponding to the number (a+b) obtained by adding the number (b) of pins of the IO user setting information B causing the second largest noise with respect to the number of simultaneously switching signals to the number (a) of the pins of the IO user setting information A and the noise of the caused noise information of the IO user setting information B corresponding to the number (a) is obtained as the contribution from the pins of the IO user setting information B.
- the purpose of using, as the initial point position, the number (a) of pins having the IO user setting information A causing the larger noise with respect to the number of simultaneously switching signals than the IO user setting information B in the above calculation of the contribution from the pins having the IO user setting information B is to reflect the qualitative shapes of the lines of the simultaneously switching signals in the graph in which the lines rise sharply immediately after the origin of the number of simultaneously switching signals, and thereafter the slopes become gradual as the number of simultaneously switching signals increases.
- the caused noise information is created in such a manner that it can support all the groups.
- the calculation of the noise on the basis of the IO setting information as described above is performed for other groups ( FIG. 8 ).
- the origin varies depending on the group, and the number of simultaneously switching signals is G in group 2 , and the number of simultaneous switching signals in group 3 is G 1 +G 2 .
- the caused noise information may be prepared for each group.
- FIG. 5 shows a data configuration of the pin information storage unit shown in FIG. 1B .
- the arrangement of the respective pins are represented by the numbers in the rows and columns, and together with these numbers (arrangement information), the pin information storage unit 11 shown in FIG. 1B stores the column number and the like. Thereby, it is possible to specify the pins included in the respective groups from the row number and the column number of target pins.
- FIG. 6 is a flowchart of the simultaneous switching noise calculation process.
- This calculation process shows the flows of processes performed in the respective portions that constitute the simultaneous switching noise estimation device 10 shown in FIG. 1B , and is realized by a program causing a computer to execute this flow.
- the computer includes the program having the functions of the above respective portions.
- the program is executed for example by specifying the pin information and the caused noise information to be referred to. These pieces of information are stored in a storage device (such as a hard disk device) that a computer can access.
- a storage device such as a hard disk device
- a process-target pin is selected by referring to the pin information, and the pin information storage unit 11 reads the pin information stored in the computer accessible storage device, obtains the IO user setting information about the pins (pins included in group 1 ) arranged in the area 22 closest to the pin for which the process is to be executed, and calculates the number of pins for each set of IO user setting information obtained (the number of simultaneously switching signals calculation unit 121 ).
- step s 12 for example, the IO user setting information is processed in descending order of the noise with respect to the number of simultaneously switching signals, and the initial point is calculated for each piece of IO user setting information by using the number of pins calculated.
- the initial point position calculation unit 13 1 sets to zero the initial point position corresponding to the IO user setting information with which the larger noise is caused with respect to the number of simultaneously switching signals.
- the initial point position calculation unit 13 1 also sets each of the other initial point positions to a value obtained by adding, to the number of pins, the initial point positions in the immediately previous IO user setting information that causes a larger noise with respect to the number of simultaneously switching signals.
- step s 13 it is determined whether or not all the groups in the neighborhood of the target pin are processed.
- group 1 the area including the eight pins
- group 2 the area including the sixteen pins
- group 3 the area including the twenty four pins. Accordingly, at the current timing, the determination result in step 13 is No, and the process returns to step S 11 .
- step s 11 the pin information stored in the pin information storage unit 11 is read, and the IO user setting information of the pins that are is the second closest to the target pin is arranged in the area 23 from the pin information. Then, for each piece of the obtained IO user setting information, the number of pins is calculated (simultaneously switching signals calculation unit 12 2 ).
- step s 12 the IO user setting information is processed in descending order of the noise with respect to the simultaneously switching signals, and the initial point position is calculated for each piece of IO user setting information by using the calculated number of pins.
- the initial point position calculation unit 13 2 sets the initial point position to the largest value of the number of pins that can be arranged in area 22 , which is included in area 23 .
- the initial point position calculation unit 13 1 also sets each of the other initial point positions to a value obtained by adding, to the number of pins, the initial point positions in the immediately previous IO user setting information that causes a larger noise with respect to the number of simultaneously switching signals.
- step s 13 it is determined that all the groups in the neighborhood of the target pin are not processed, and the process returns to step s 11 again.
- step s 11 the pin information stored in the pin information storage unit 11 is read, and the IO user setting information of the pins arranged in the area 24 that are the third closest to the target pin is obtained from the pin information. Then, for each of the obtained pieces of IO user setting information, the number of pins is calculated (simultaneously switching signals calculation unit 12 3 ).
- step s 12 the initial point position calculation unit 133 processes the IO user setting information of the pins in the area including the twenty-four pins that are the third closest to the target pin in, for example, descending order of the level of noise with respect to the number of simultaneously switching signals, and calculates the initial position by using the number of pins calculated for each piece of IO user setting information.
- the initial point position calculation unit 13 3 sets the initial point position to the largest number of pins that can be arranged in areas 22 and 23 , which are within area 24 .
- the initial point position calculation unit 13 1 also sets each other initial point position to a value obtained by adding, to the number of pins, the initial point positions in the immediately previous IO user setting information that causes greater noise with respect to the number of simultaneously switching signals.
- step S 13 the judgment becomes YES because all the groups in the neighborhood of the target pin are processed, and the process proceeds to step s 14 .
- step S 14 the corresponding caused noise information is referred to by data including the IO user setting information, the number of pins, and the initial position (offset value), and the difference between noise of “the number of pins+initial point position” and the initial point position is calculated (noise calculation unit 15 ).
- step s 15 the simultaneous switching noise in the target pin is calculated by calculating the sum of the differences calculated for the respective groups and IO user setting information in step S 14 .
- step s 16 it is determined whether or not the noise calculated in step s 15 is greater than the threshold value that is the toleration limit value. When this is determined to be YES because the calculated noise is greater in step s 16 , a message such as, for example, “Please change pin arrangement” is output in step s 17 .
- step S 16 When this is determined, in contrast, to be NO because the calculated noise is equal to or smaller than the threshold value in step S 16 , the target pin is changed to the next pin in step S 18 , and the process returns to step s 11 .
- the simultaneous switching noise in all the pins included in the semiconductor device can be estimated, and it is confirmed whether or not the noise is within the tolerated range.
- FIG. 7 shows an example of pin arrangement in the neighborhood of the target pin on an FPGA chip.
- FIG. 8 is a graph illustrating a method of calculating the simultaneous switching noise on the target pin shown in FIG. 7 .
- FIG. 7 an example is shown of the status in which area 32 including the eight pins (group 1 ) that are the closest to the area 31 in which the target pin is arranged includes two pins having the IO user setting information A, four pins having the IO user setting information B, and two pins having the IO user setting information C.
- FIG. 7 an example is shown of the status in which area 32 including the sixteen pins (group 2 ) that are the second closest to area 31 in which the process target pin is arranged includes five pins having the IO user setting information A, five pins having the IO user setting information B, five pins having the IO user setting information C, and one pin that is not used.
- FIG. 7 an example is shown of the status in which area 34 including the twenty-four pins (group 3 ) that is the third closest to area 31 in which the process target pin is arranged includes seven pins having the IO user setting information A, seven pins having the IO user setting information B, seven pins having the IO user setting information C, and three pins that are not used.
- the greatest noise with respect to the number of simultaneously switching signals is caused with the IO user setting information A, and the least noise with respect to the number of simultaneously switching signals is caused with the IO user setting information C.
- any of groups 1 through 3 include the pin that has the IO user setting information A that causes the greatest noise for the number of simultaneously switching signals between the three types of IO user setting information (IO user setting information A, IO user setting information B, and IO user setting information C).
- the value of the IO user setting information, the number of pins, the initial point position, and the corresponding noise in group 1 are expressed as below.
- X represents the number of simultaneously switching signals
- F(X) represents the simultaneous switching noise represented by the caused noise information (function) for the IO user setting information A
- G(X) represents the simultaneous switching noise represented by the caused noise information (function) for the IO user setting information B
- H(X) represents the simultaneous switching noise represented by the caused noise information (function) for the IO user setting information C.
- the noise calculation unit 15 calculates the simultaneous switching noise (SSO) by calculating the sum of the instances of noise (differences) calculated for the respective groups and the sets of IO user setting information on the basis of the equation below.
- SSO simultaneous switching noise
- step S 14 Each instance of noise (difference) is calculated in step S 14 , and the calculation of the simultaneous switching noise by using the equation below is performed in step S 15 .
- the above equation is of the simultaneous switching noise calculated under the pin arrangement shown in FIG. 7 .
- the areas in the neighborhood of the target pin (the area in which the pins to be used for the simultaneous switching noise estimation are arranged) are categorized into N number of areas (groups), and each group includes M number of sets of IO user setting information
- the simultaneous switching noise caused in the target pin with the IO user setting information Y included in the group X is represented by Noise_X_Y.
- the simultaneous switching noise SSO that the target pin receives from the area around it is expressed by the equation below.
- SSO Noise — 1 — 1+Noise — 1 — 2+ . . . +Noise — 1 — M +Noise — 2 — 1+ . . . +Noise — N — M
- FIG. 9 shows an example of a storage medium.
- the simultaneous switching noise estimation device can be realized by using a computer (information processing apparatus) 61 .
- the computer 61 has devices such as a CPU, a memory input device, a medium driving device, a network connection device, and the like.
- the program and data having functions of realizing the respective units constituting the simultaneous switching noise estimation device 10 can be executed by being loaded into memory in the computer 61 from a storage device 65 , can be executed by being loaded into the medium driving device from a transportable storage medium 63 , and also can be executed by being received by the network connection device via a network 66 from an external storage device 62 .
- the present invention can be widely applied to semiconductor devices such as an ASIC and the like even though the above embodiment has been explained by using the example of the FPGA.
- FIG. 10A shows an electric current flowing between the PCBs and a semiconductor device.
- FIG. 10B shows a space in which a magnetic flux is generated by a return current that is caused to flow by the provision of an IO signal to a pin.
- a BGA (Ball Grid Array) package 100 that is a semiconductor device is connected between a power source plane 201 and a ground plane 202 of the PCB.
- the power source plane 201 is connected to a power source pattern 131 via a board pattern 211 on the PCB side, a solder ball 111 , and a board pattern (bonding wire) 121 on the package 100 side.
- the ground plane 202 is connected to the ground pattern 132 of the chip 101 via the board pattern 213 , the solder ball 113 , and the board pattern (bonding wire) 123 .
- Symbols S 1 through S 3 in FIGS. 10A and 10B are switches respectively provided on the chip 101 .
- the respective switches S 1 through S 3 respectively control the flows of current between the power source pattern 131 and the ground pattern 132 .
- the terminals used for the control are respectively connected to the solder balls 112 , 114 and 115 via the board pattern 122 , 124 or 125 .
- the respective solder balls 111 through 115 respectively exist for each pin.
- the above coupling degree corresponds to the target pin, and is generally equal to the coupling inductance of the return current path of a pin that causes the noise for the pin (corresponding to a pin included in any of the groups; hereinafter this pin is referred to as “noise causing pin” for simplicity).
- the magnitude depends on the arrangement of the target pin/noise causing pin on the package 100 , the board patterns that are respectively connected to these pins, the positions of the switches respectively connected via the board patterns on the chip 101 , the arrangement of the pins for the power/ground on the package 100 , the board patterns respectively connected to the pins, and positions of the connections between the board patterns on the chip 101 .
- the spaces L 1 through L 3 that constitute the path become magnetic regions in which magnetic fields are generated.
- the coupling inductance of the return current path is in direct proportion to the magnetic flux amount generated in the space L 1 .
- the coupling inductance of the return current path is in direct proportion to the magnetic flux amount generated in the space L 1 +L 2 .
- the number of fluxes in the space L 1 +L 2 is greater than that in the space L 1 ; accordingly, a greater noise is caused when the target pin is connected to the switch S 2 .
- the coupling coefficient (coupling inductance) is in direct proportion to the area size of the space formed by the return current path, and the magnetic flux amount generated is in direct proportion to the area size.
- the return current path is analyzed by the actual measurement or the simulation, and grouping is performed for the pin (noise causing pin) that is the target pin and also is the pin used for the estimation of the simultaneous switching noise.
- This grouping is performed by preparing, for each target pin, differentiation information (for example, arrangement information) used for specifying pins included in the respective groups and by referring to prepared information.
- the caused noise information is used for each group similarly in the first and second embodiments. By performing this grouping, it is possible to accurately estimate the simultaneous switching noise.
- the simultaneous switching noise calculation process performed for estimating the noise is fundamentally the same as that of the second embodiment except that the method for specifying the pins included in the respective groups is different. Therefore, the configuration of the simultaneous switching noise estimation device is also fundamentally the same as that in the second embodiment. Accordingly, the detailed explanation thereof is omitted.
- the package 100 /substrate board pattern is much larger and more dominant than the pattern formed on the chip 101 . Accordingly, the amount of noise caused is mainly determined by the arrangement of the pins on the package 100 . Accordingly, in the first and second embodiment, the grouping is performed on the basis of the arrangement of the pins. Therefore, in FIG. 10B , the dashed slants that represent the area of the spaces L 1 through L 3 are shown only in the ground plane 202 .
- the above first through third embodiments all employ a configuration in which the simultaneous switching noise is estimated on the assumption that the pin to which the IO user setting information is assigned causes the noise.
- the pins that can be neglected are not used for the estimation in order to perform more accurate estimation of the simultaneous switching noise.
- FIG. 11 shows a grouping method according to the fourth embodiment.
- pins are categorized in accordance with the IO user setting information, and also the pins are categorized in accordance with the phases of the IO signals that are input and output on the basis of the IO user setting information.
- the IO signals can be roughly categorized into three types. The first type is signal that change being in phase with the IO signal input into and output from the target pin (effective edges are synchronous). The second type is signal that change not being in phase with the IO signal input into and output from the target pin (the effective edges are not synchronous; here it is called “opposite phase”). The third type is signal that change being asynchronously.
- the signals that change being in phase and the signals that change being asynchronously can be proven to cause noise in the target pin while the signals that change being out of phase cannot be proven to cause noise in the target pin. Accordingly, the pins used for inputting and outputting the IO signals that change being out of phase are not used for the estimation of the simultaneous switching noise in order to avoid the overestimation of the (amount of) noise. Thereby, it is possible to estimate the noise more accurately.
- the above grouping can be performed by preparing phase information of the IO signals that are input into and output from each pin used for the estimation of the simultaneous switching noise or by preparing the phase information of the IO signals for each pin.
- the simultaneous switching noise calculation process executed for estimating the noise is fundamentally the same as in the second embodiment except for the method of specifying the pins included in the respective groups. Therefore, the configuration of the simultaneous switching noise estimation device is the same as that in the second embodiment. Accordingly, a detailed explanation thereof is omitted.
- specifications of the device (product) constituted by the semiconductor device and the PCB including the semiconductor device are determined (S 101 ).
- a required LSI Large Scale Integration
- mapping is performed to determine whether the identified LSI is to be included in the semiconductor device or the PCB (S 102 ).
- specifications of the interface are determined between the semiconductor device and the PCBs, and between the PCBs and the external devices (S 103 ). Thereafter, the design of the semiconductor device and the PCBs proceed respectively.
- fundamental specifications are determined (S 201 ). Thereafter, the functional design (S 202 ) reflecting the result of S 102 and S 103 is performed. After performing the functional design, the determination of the pin arrangement (S 203 ), the wiring design (S 204 ) based on the determined pin arrangement, and the timing verification (S 205 ) for verifying whether or not the device appropriately operates are performed in this order.
- the LSI (semiconductor device) production phase starts. When a fault or the like is detected in S 204 or S 205 , the previous phase starts again in order to change the design.
- the fundamental design of the PCBs is performed while taking into consideration the results of S 102 and S 103 , and the size, type, and the like of the PCBs are determined (S 301 ). Thereafter, the arrangement of the LSIs (power circuit and connectors to connect the semiconductor device) to be included in the PCBs are determined (S 302 ), and the wire connection based on the determined arrangement is determined (S 303 ).
- the simultaneous switching noise to be estimated may change depending on the pin arrangement, the wiring based on the arrangement, and the arrangement of LSIs on the PCBs. Accordingly, the SSN check is performed on the semiconductor device when the designing of S 203 and S 204 is completed and on the PCBs when the LSI arrangement in S 302 is determined.
- the SSN check is a check of whether or not simultaneous switching noise estimated for each pin is within the tolerated range (S 401 ). If the check result indicates that there is a pin that causes simultaneous switching noise that is out of the tolerated range, the phase before the checking or one of the other phases starts, and a design change, a pin arrangement change, or a wiring change is performed to react to this fault. Also, if the phase in which a fault is detected is in S 302 , it is possible to change the design such as the LSI arrangement.
- timing verification in S 205 and the wire connection between the LSIs in S 303 are performed, a timing verification is performed for verifying whether or not signals can be transmitted and received appropriately via the external interface.
- a fault is not detected in this verification, the production of the semiconductor device in S 206 or the production of the PCB in S 304 starts. After these production steps, the production of a device including the semiconductor device on the PCB is started (S 104 ).
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
Description
(A, 2, 0),a1=F(2+0)(−F(0))
(B, 4, 2),b1=G(4+2)−G(2)
(C, 2, 6),c1=H(2+6)−H(6)
(A, 5, 8),a2=F(5+8)−F(8)
(B, 5, 13),b2=G(5+13)−G(13)
(C, 5, 18),c2=H(5+18)−H(18)
(A, 7, 24),a3=F(7+24)−F(24)
(B, 7, 31),b3=G(7+31)−G(31)
(C, 7, 38),c3=H(7+38)−H(38)
SSO=a1+a2+a3+b1+b2+b3+c1+c2+c3
SSO=
Claims (14)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/882,293 US7949977B2 (en) | 2006-07-31 | 2007-07-31 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium |
US13/064,805 US8214785B2 (en) | 2006-07-31 | 2011-04-18 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium |
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006-209098 | 2006-07-31 | ||
JP2006209098 | 2006-07-31 | ||
US60472906A | 2006-11-28 | 2006-11-28 | |
JP2007-120060 | 2007-04-27 | ||
JP2007120060A JP4940013B2 (en) | 2006-07-31 | 2007-04-27 | Simultaneous operation signal noise estimation method and program for semiconductor device |
US11/882,293 US7949977B2 (en) | 2006-07-31 | 2007-07-31 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US60472906A Continuation-In-Part | 2006-07-31 | 2006-11-28 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/064,805 Division US8214785B2 (en) | 2006-07-31 | 2011-04-18 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium |
Publications (2)
Publication Number | Publication Date |
---|---|
US20080027662A1 US20080027662A1 (en) | 2008-01-31 |
US7949977B2 true US7949977B2 (en) | 2011-05-24 |
Family
ID=38987426
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/882,293 Expired - Fee Related US7949977B2 (en) | 2006-07-31 | 2007-07-31 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium |
US13/064,805 Expired - Fee Related US8214785B2 (en) | 2006-07-31 | 2011-04-18 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US13/064,805 Expired - Fee Related US8214785B2 (en) | 2006-07-31 | 2011-04-18 | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium |
Country Status (2)
Country | Link |
---|---|
US (2) | US7949977B2 (en) |
JP (1) | JP4940013B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8151233B1 (en) * | 2009-04-07 | 2012-04-03 | Altera Corporation | Circuit design with incremental simultaneous switching noise analysis |
US8302058B1 (en) * | 2009-09-11 | 2012-10-30 | Altera Corporation | Reducing simultaneous switching noise in an integrated circuit design during placement |
WO2012170780A2 (en) * | 2011-06-10 | 2012-12-13 | Mayo Foundation For Medical Education And Research | Zero sum signaling in a digital system environment |
US8694946B1 (en) | 2008-02-20 | 2014-04-08 | Altera Corporation | Simultaneous switching noise optimization |
US20150286770A1 (en) * | 2012-03-23 | 2015-10-08 | Nec Corporation | Design rule check system, method, and non-transitory computer readable medium storing presentation program |
Families Citing this family (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7496871B2 (en) | 2003-10-21 | 2009-02-24 | Roberto Suaya | Mutual inductance extraction using dipole approximations |
US8161438B2 (en) * | 2003-10-21 | 2012-04-17 | Mentor Graphics Corporation | Determining mutual inductance between intentional inductors |
US8402402B1 (en) * | 2006-12-11 | 2013-03-19 | Altera Corporation | Method for calculating a mixed I/O standard simultaneous switching noise (SSN) using a non-mixed I/O standard SSN model |
US7788620B1 (en) | 2007-01-22 | 2010-08-31 | Lattice Semiconductor Corporation | Input/output placement systems and methods to reduce simultaneous switching output noise |
JP4888556B2 (en) * | 2007-06-20 | 2012-02-29 | 富士通株式会社 | Inter-unit setting synchronizer |
JP5071081B2 (en) * | 2007-12-06 | 2012-11-14 | 富士通株式会社 | Simultaneous operation signal noise basic characteristic acquisition method and program in simultaneous operation signal noise estimation method for semiconductor device |
JP5228481B2 (en) | 2007-12-28 | 2013-07-03 | 富士通株式会社 | Method for estimating jitter based on simultaneous operation signal noise for semiconductor device, method for calculating correlation between simultaneous operation signal noise amount and jitter amount used for the estimation, program for realizing them, and semiconductor device and the same Printed circuit board design method |
US7983880B1 (en) * | 2008-02-20 | 2011-07-19 | Altera Corporation | Simultaneous switching noise analysis using superposition techniques |
US8214788B2 (en) | 2008-03-08 | 2012-07-03 | Mentor Graphics Corporation | High-frequency VLSI interconnect and intentional inductor impedance extraction in the presence of a multi-layer conductive substrate |
US8234611B2 (en) | 2008-07-02 | 2012-07-31 | International Business Machines Corporation | System and method for modeling I/O simultaneous switching noise |
US20100017158A1 (en) * | 2008-07-21 | 2010-01-21 | International Business Machines Corporation | Generating worst case bit patterns for simultaneous switching noise (ssn) in digital systems |
JP5056650B2 (en) * | 2008-07-28 | 2012-10-24 | 富士通株式会社 | Voltage fluctuation amount estimation method, apparatus, semiconductor device operation verification apparatus, semiconductor device design method, printed board design method, and program |
JP6645114B2 (en) * | 2015-10-16 | 2020-02-12 | 富士通株式会社 | Design support program, information processing apparatus, and design support method |
KR20210095781A (en) | 2020-01-24 | 2021-08-03 | 주식회사 에이프릴바이오 | A multi-specific antibody comprising a fusion construct consisting of a Fab and a bioactive effector moiety |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5477460A (en) * | 1994-12-21 | 1995-12-19 | International Business Machines Corporation | Early high level net based analysis of simultaneous switching |
JP2000285146A (en) | 1999-03-29 | 2000-10-13 | Nec Ic Microcomput Syst Ltd | Circuit design method for semiconductor device and storage medium storing program therefor |
US6564355B1 (en) * | 1999-08-31 | 2003-05-13 | Sun Microsystems, Inc. | System and method for analyzing simultaneous switching noise |
US7139691B1 (en) * | 2003-10-21 | 2006-11-21 | Xilinx, Inc. | Method for calculating weighted average ground bounce noise generated by simultaneous switching outputs in a digital system |
US7412673B1 (en) * | 2006-01-30 | 2008-08-12 | Xilinx, Inc. | Integrated system noise management—bounce voltage |
US7523430B1 (en) * | 2005-09-09 | 2009-04-21 | Altera Corporation | Programmable logic device design tool with simultaneous switching noise awareness |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH077063A (en) * | 1993-06-14 | 1995-01-10 | Fujitsu Ltd | Method for verifying noise |
JPH08278992A (en) * | 1995-04-04 | 1996-10-22 | Hitachi Ltd | Designing method for semiconductor integrated circuit device |
JP3183244B2 (en) * | 1998-03-03 | 2001-07-09 | 日本電気株式会社 | Test method for integrated circuits |
JP2004054522A (en) * | 2002-07-18 | 2004-02-19 | Fujitsu Ltd | Method for evaluating simultaneous switching noise of semiconductor device |
US6807656B1 (en) * | 2003-04-03 | 2004-10-19 | Lsi Logic Corporation | Decoupling capacitance estimation and insertion flow for ASIC designs |
JP4432606B2 (en) * | 2003-06-27 | 2010-03-17 | 富士通株式会社 | Simultaneous switching output noise estimation method and apparatus for semiconductor integrated circuit, and design method and apparatus for semiconductor integrated circuit |
US7454301B1 (en) * | 2006-08-18 | 2008-11-18 | Altera Corporation | Method and apparatus for predicting system noise |
-
2007
- 2007-04-27 JP JP2007120060A patent/JP4940013B2/en not_active Expired - Fee Related
- 2007-07-31 US US11/882,293 patent/US7949977B2/en not_active Expired - Fee Related
-
2011
- 2011-04-18 US US13/064,805 patent/US8214785B2/en not_active Expired - Fee Related
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5477460A (en) * | 1994-12-21 | 1995-12-19 | International Business Machines Corporation | Early high level net based analysis of simultaneous switching |
JP2000285146A (en) | 1999-03-29 | 2000-10-13 | Nec Ic Microcomput Syst Ltd | Circuit design method for semiconductor device and storage medium storing program therefor |
US6564355B1 (en) * | 1999-08-31 | 2003-05-13 | Sun Microsystems, Inc. | System and method for analyzing simultaneous switching noise |
US7139691B1 (en) * | 2003-10-21 | 2006-11-21 | Xilinx, Inc. | Method for calculating weighted average ground bounce noise generated by simultaneous switching outputs in a digital system |
US7523430B1 (en) * | 2005-09-09 | 2009-04-21 | Altera Corporation | Programmable logic device design tool with simultaneous switching noise awareness |
US7412673B1 (en) * | 2006-01-30 | 2008-08-12 | Xilinx, Inc. | Integrated system noise management—bounce voltage |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8694946B1 (en) | 2008-02-20 | 2014-04-08 | Altera Corporation | Simultaneous switching noise optimization |
US8151233B1 (en) * | 2009-04-07 | 2012-04-03 | Altera Corporation | Circuit design with incremental simultaneous switching noise analysis |
US8302058B1 (en) * | 2009-09-11 | 2012-10-30 | Altera Corporation | Reducing simultaneous switching noise in an integrated circuit design during placement |
WO2012170780A2 (en) * | 2011-06-10 | 2012-12-13 | Mayo Foundation For Medical Education And Research | Zero sum signaling in a digital system environment |
WO2012170780A3 (en) * | 2011-06-10 | 2013-04-18 | Mayo Foundation For Medical Education And Research | Zero sum signaling in a digital system environment |
US9300434B2 (en) | 2011-06-10 | 2016-03-29 | Mayo Foundation For Medical Education And Research | Zero sum signaling in a digital system environment |
US20150286770A1 (en) * | 2012-03-23 | 2015-10-08 | Nec Corporation | Design rule check system, method, and non-transitory computer readable medium storing presentation program |
US9342649B2 (en) * | 2012-03-23 | 2016-05-17 | Nec Corporation | Rule check system, method, and non-transitory computer readable medium storing presentation program |
Also Published As
Publication number | Publication date |
---|---|
JP4940013B2 (en) | 2012-05-30 |
US8214785B2 (en) | 2012-07-03 |
US20080027662A1 (en) | 2008-01-31 |
US20110239175A1 (en) | 2011-09-29 |
JP2008059553A (en) | 2008-03-13 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7949977B2 (en) | Method and device for estimating simultaneous switching noise in semiconductor device, and storage medium | |
KR102563308B1 (en) | Deskewing of rising and falling signals | |
US20080034338A1 (en) | Timing analysis method and device | |
JP3887231B2 (en) | Crosstalk analysis method, electronic circuit device design method, design support method, design system, and creation method using the same | |
JP2005004268A (en) | Method for analyzing operation of semiconductor integrated circuit device, analyzing device used for same, and optimized designing method using the same | |
JP2006227762A (en) | Method for designing semiconductor integrated circuit and device for designing semiconductor integrated circuit | |
TWI521220B (en) | Timing analysis method for integrated circuit and computer program product thereof | |
US8250510B2 (en) | Jitter amount estimating method, method for calculating correlation between amount of simultaneously operating signal noise and jitter amount, and recording medium | |
US8079012B2 (en) | Method for acquiring basic characteristic of simultaneous switching noise in method for estimating simultaneous switching noise on semiconductor device | |
US7496872B2 (en) | Library creating device and interconnect capacitance estimation system using the same | |
JP4526596B2 (en) | Signal delay evaluation program, signal delay evaluation method, and signal delay evaluation apparatus | |
US8275596B2 (en) | Method for robust statistical semiconductor device modeling | |
US7216315B2 (en) | Error portion detecting method and layout method for semiconductor integrated circuit | |
US20160283639A1 (en) | Semiconductor Device Design Methods and Conductive Bump Pattern Enhancement Methods | |
US6577150B1 (en) | Testing apparatus and method of measuring operation timing of semiconductor device | |
US20070229110A1 (en) | Power supply method for semiconductor integrated circuit in test and CAD system for semiconductor integrated circuit | |
US8302066B2 (en) | Clock jitter suppression method and computer-readable storage medium | |
US20050055611A1 (en) | Method of testing semiconductor apparatus | |
US5894421A (en) | Method and apparatus for calculating slew rates and signal propagation times for signal waveforms | |
JP2007192635A (en) | System and method for measuring circuit | |
US8813010B2 (en) | Timing analysis program, timing analysis apparatus, and timing analysis method | |
KR100503551B1 (en) | Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor | |
JP2006235889A (en) | Method for analyzing timing | |
CN114722770A (en) | Method and equipment for creating delay model of FPGA circuit and obtaining delay | |
KR20230166767A (en) | Temperature margin setting method for 3d integrated circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: FUJITSU LIMITED, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:KOUZAKI, YASUO;UEKUSA, SHINICHIRO;REEL/FRAME:019921/0135 Effective date: 20070802 |
|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
MAFP | Maintenance fee payment |
Free format text: PAYMENT OF MAINTENANCE FEE, 8TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1552); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Year of fee payment: 8 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20230524 |