CN114722770A

CN114722770A - Method and equipment for creating delay model of FPGA circuit and obtaining delay

Info

Publication number: CN114722770A
Application number: CN202110013940.4A
Authority: CN
Inventors: 钱港; 王似飞; 林智锋; 陈建利; 俞军
Original assignee: Shanghai Fudan Microelectronics Group Co Ltd
Current assignee: Shanghai Fudan Microelectronics Group Co Ltd
Priority date: 2021-01-06
Filing date: 2021-01-06
Publication date: 2022-07-08

Abstract

The embodiment of the invention provides a method and equipment for creating a time delay model of an FPGA circuit and acquiring time delay, wherein the method comprises the following steps: determining a path delay of a path calculated from a path of a first junction box immediately adjacent to and downstream of the output pin to a path of a second junction box immediately adjacent to and upstream of the input pin based on coordinates of any two slices, the output pin of one and the input pin of the other; and storing the coordinates of any two slices, the output pin of one Slice and the input pin and the path delay of the other Slice in a path delay table. The technical scheme of the embodiment of the invention can reduce the storage space required for storing a large number of combination types of long line segments and the corresponding time delay.

Description

Method and equipment for creating delay model of FPGA circuit and obtaining delay

Technical Field

The present invention relates to the Field of integrated circuit technology, and in particular, to a method and apparatus for creating a delay model of a Field-Programmable Gate Array (FPGA) circuit and obtaining a delay.

Background

The design process of the FPGA chip mainly includes stages of logic synthesis, technology mapping, packaging, layout, wiring, bit stream generation, etc., where the layout is a very complex and most critical stage, and the result directly affects circuit performance, area, reliability, power, manufacturing yield, etc.

With the continuous development of the FPGA technology, the time delay caused by the connecting lines in the FPGA chip becomes one of the main factors of the time delay of the whole circuit, but the efficiency and accuracy of evaluating the time delay are low.

Disclosure of Invention

The technical problems solved by the invention include lower efficiency and accuracy of time delay evaluation and the like.

To solve the foregoing technical problem, an embodiment of the present invention provides a method for creating a delay model of an FPGA circuit, where the FPGA circuit includes a plurality of slices, the delay model includes a path delay table, and the method includes: determining a path from a first junction box immediately adjacent and downstream of the output pin to a second junction box immediately adjacent and upstream of the input pin based on the coordinates of any two slices, the output pin of one and the input pin of the other; calculating the path delay of the path by the following formula; and storing the coordinates of any two slices, the output pin of one Slice and the input pin and the path delay of the other Slice in a path delay table.

Path_delay＝Long_delay+Remainder_delay，

Wherein, Path _ delay represents Path delay, Long _ delay represents Long-line section delay generated by a Long-line section, and Remainder _ delay represents residual delay generated by a short-line section after removing the Long-line section, and comprises delay generated by converting at least one Long-line section into a short-line section.

Optionally, the method for creating the delay model of the FPGA circuit includes calculating the long-line-segment delay according to the following formula:

Long_delay＝Nx*Long_delayX+Ny*Long_delayY，

where Nx denotes the number of Long segments in the X direction, Long _ delayX denotes the time delay of a Long segment in the X direction, Ny denotes the number of Long segments in the Y direction, and Long _ delayY denotes the time delay of a Long segment in the Y direction.

Optionally, the method for creating the delay model of the FPGA circuit includes calculating a remaining delay by the following formula:

Remainder_delay＝Remainder_delayX+Remainder_delayY，

the remaining _ delayX represents the remaining delay in the X direction, Mx represents the number of types of short line segments in the X direction, Pi represents the number of types of short line segments in the ith X direction, Base _ delayXi represents the basic delay of the short line segments in the ith X direction, the remaining _ delayY represents the remaining delay in the Y direction, My represents the number of types of short line segments in the Y direction, Qi represents the number of types of short line segments in the ith Y direction, and Base _ delayYi represents the basic delay of the short line segments in the ith Y direction.

Optionally, the short line segment type is determined based on the length and direction of the line segment.

Optionally, if Nx1 is greater than 0, the method for creating the delay model of the FPGA circuit is implemented by the following formula such that the remaining delay in the X direction includes a delay generated by converting an X-direction long line segment into an X-direction short line segment:

Nx2＝Nx1-1，

Remainder_X2＝Remainder_X1+Lx，

where Lx represents the time delay of one long line segment in the X direction, Nx1 represents the original number of long line segments in the X direction, Nx2 represents the new number of long line segments in the X direction after one long line segment is converted into a short line segment in the X direction, Remainder _ X1 represents the original residual time delay in the X direction, and Remainder _ X2 represents the new residual time delay in the X direction after one long line segment is converted into a short line segment in the X direction.

Optionally, the remaining delay in the X direction comprises an extra delay in the X direction.

Optionally, the method for creating the delay model of the FPGA circuit includes, if Ny1 is greater than 0, making the remaining delay in the Y direction include a delay generated by converting a long Y-direction line segment into a short Y-direction line segment by the following formula:

Ny2＝Ny1-1.

Remainder_Y2＝Remainder_Y1+Ly，

where Ly represents the length of one long line segment in the Y direction, Ny1 represents the original number of long line segments in the Y direction, Ny2 represents the new number of long line segments in the Y direction after one long line segment is converted into a short line segment in the Y direction, Remainder _ Y1 represents the original residual delay in the Y direction, and Remainder _ Y2 represents the new residual delay in the Y direction after one long line segment is converted into a short line segment in the Y direction.

Optionally, the remaining delay in the Y direction comprises an extra delay in the Y direction.

Optionally, the delay model includes an internal delay table, and the method for creating the delay model of the FPGA circuit includes: determining a number of paths from an input pin to an output pin inside each Slice of the plurality of slices; respectively calculating internal time delay from the input pin to the output pin based on a plurality of paths; and storing the internal time delay between the input pin and the output pin corresponding to the paths of each Slice and the two pins in an internal time delay table.

Optionally, the delay model includes a pin delay table, and the method for creating the delay model of the FPGA circuit includes: calculating the time delay from the output pin of each Slice in the plurality of slices to the output pin of the first junction box which is adjacent to and located at the downstream of the Slice; calculating an input pin delay of each Slice of the plurality of slices to an input pin of a second junction box immediately adjacent and upstream therefrom; and storing the output pin time delay of each Slice and the output pin time delay corresponding to the output pin time delay as well as the input pin time delay corresponding to the input pin time delay into a pin time delay table.

Optionally, the Slice includes an LUT, an FF, and a MUX, the input pin includes an input of the LUT, and the output pin includes an output of the LUT, an output of the FF, and an output of the MUX.

Optionally, the delay model includes a modified delay table, and the method for creating the delay model of the FPGA circuit includes: determining a path from the output pin to the input pin based on the coordinates of any two slices, the output pin of one and the input pin of the other; determining the type and the number of non-Slice modules passing through a path; obtaining a corrected time delay based on the type and the number of the non-Slice modules; and storing the coordinates of any two slices, the output pin of one Slice, the input pin of the other Slice and the correction time delay of the path in a correction time delay table.

Optionally, the type of non-Slice module includes DSP and RAM.

Optionally, the modified delay table includes a first table and a second table, and the method for creating the delay model of the FPGA circuit includes: recording the corresponding line number of each line segment passing through each non-Slice module in a path in a second table through the related line of the first table; respectively recording resistance values and capacitance values respectively corresponding to connecting lines in the line segments through each line of the second table; calculating the corrected time delay passing through the non-Slice module by the following formula:

τ2＝In²(R1C1+(R1+R2)C2)，

where τ 2 represents the corrected time delay through the non-Slice module, In2 represents the square of the value of the base e logarithm, R1 and C1 represent the resistance value and capacitance value corresponding to the connection line of the non-Slice module to the connection box immediately adjacent thereto and located upstream, respectively, and R2 and C2 represent the resistance value and capacitance value corresponding to the connection line of the non-Slice module to the connection box immediately adjacent thereto and located downstream, respectively.

The embodiment of the invention also provides equipment for creating the time delay model of the FPGA circuit, which comprises a memory and a processor, wherein the memory is stored with computer instructions capable of running on the processor, and the steps of the method for creating the time delay model of the FPGA circuit are executed when the processor runs the computer instructions.

The embodiment of the invention also provides a method for acquiring the time delay of the FPGA circuit according to the time delay model, which comprises the following steps: respectively acquiring the internal time delay of the source Slice and the internal time delay of the terminal Slice from an internal time delay table based on an output pin of the source Slice and an input pin of the terminal Slice; acquiring a path delay from a first connection box which is adjacent to and located at the downstream of the output pin to a second connection box which is adjacent to and located at the upstream of the input pin from a path delay table based on the coordinates and the output pin of the source Slice and the coordinates and the input pin of the terminal Slice; calculating a first total time delay from the source Slice to the terminal Slice by the following formula:

Total_delay1＝Inertal_delay+Path_delay，

where Total _ delay1 denotes the first Total delay, initial _ delay denotes the internal delay, which includes the internal delay of the source Slice and the internal delay of the terminal Slice, and Path _ delay denotes the Path delay.

Optionally, the method for obtaining the time delay of the FPGA circuit includes: respectively acquiring the output pin time delay of the source Slice and the input pin time delay of the terminal Slice from a pin time delay table based on the output pin of the source Slice and the input pin of the terminal Slice; calculating a second total time delay from the source Slice to the terminal Slice by:

Total_delay2＝Inertal_delay+Pin_delay+Path_delay，

where Total _ delay2 represents the second Total delay and Pin _ delay represents the Pin delay, which includes the output Pin delay of the source Slice and the input Pin delay of the terminal Slice.

Optionally, the method for obtaining the time delay of the FPGA circuit includes: acquiring a correction time delay from the output pin to the input pin from a correction time delay table based on the coordinate and the output pin of the source Slice and the coordinate and the input pin of the terminal Slice; calculating a third total time delay from the source Slice to the terminal Slice by the following formula:

Total_delay3＝Inertal_delay+Pin_delay+Path_delay+Modify_delay，

where, Total _ delay3 represents the third Total delay, and modification _ delay represents the correction delay.

The embodiment of the invention also provides equipment for acquiring the time delay of the FPGA circuit, which comprises a memory and a processor, wherein the memory is stored with a computer instruction capable of running on the processor, and the step of the method for acquiring the time delay of the FPGA circuit is executed when the processor runs the computer instruction.

Compared with the prior art, the technical scheme of the embodiment of the invention has beneficial technical effects.

For example, in the embodiments of the present invention, a delay model including a path delay table is created, where the path delay stored in the path delay table includes a long segment delay and a remaining delay, and the remaining delay includes a delay generated by converting at least one long segment into a short segment, which may reduce a storage space required for storing a combination type of a large number of long segments and a delay corresponding to the long segments.

For another example, the delay model of the FPGA circuit created in the embodiment of the present invention includes one or more of a path delay table, an internal delay table, a pin delay table, and a correction delay table, and the total delay calculated based on these delay tables is relatively accurate, so that the FPGA circuit designed or optimized based on the estimation can satisfy timing constraints.

For another example, the delay model of the FPGA circuit created in the embodiment of the present invention includes one or more of a path delay table, an internal delay table, a pin delay table, and a correction delay table, and the total delay is specifically divided into a path delay, an internal delay, a pin delay, and a correction delay, which considers that the internal structure and the resource distribution of the FPGA chip are very symmetric, for example, the module structure consistency (i.e., the internal delays of modules of the same type are substantially consistent at different positions), the path correlation (i.e., the delays generated by paths passing through the same module or using the same line segment are substantially consistent), the distance correlation (i.e., the corresponding delays of two modules having a constant distance are substantially consistent at different positions of the FPGA), and the vertical symmetry (i.e., each column of the FPGA only includes one type of module, and the total delays after the modules are translated up and down are consistent); the delays of the same elements (e.g., the same Configurable Logic Block (CLB), the same basic programmable Logic unit Slice (which is located within the CLB), the same look-up Table (LUT), flip-flops (FF), Multiplexer (MUX), etc. circuit elements (which are located within Slice)) at different locations are substantially the same, and are only related to the locations of these modules, slices, or circuit elements and the arrangement of input and output pins, so that these delays can be recorded with less memory space. The time delay calculation can reduce redundant calculation based on the symmetry in the FPGA chip, reduce storage space related to recording time delay information, and reduce time for searching the time delay information, thereby accurately and efficiently estimating the time delay.

Drawings

FIG. 1 is a schematic diagram of an array structure of an FPGA chip in an embodiment of the invention;

FIG. 2 is a schematic diagram of connection line resources in an FPGA chip according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a distributed RC model in an embodiment of the present invention;

FIG. 4 is a flow chart of creating a delay model for an FPGA circuit in an embodiment of the present invention;

FIG. 5 is a schematic diagram of an input pin and an output pin in Slice according to an embodiment of the invention;

FIG. 6 is a schematic diagram of a path from a source Slice to a terminal Slice in an embodiment of the invention;

FIG. 7 is a schematic structural diagram of Slice in the embodiment of the present invention;

FIG. 8 is a schematic diagram of a path through a non-Slice module in an embodiment of the invention;

FIG. 9 is a schematic diagram of a non-Slice module and its connections according to an embodiment of the invention;

fig. 10 is a flowchart for acquiring the delay of the FPGA circuit in the embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the embodiments of the present invention more comprehensible, specific embodiments accompanied with figures are described in detail below.

As shown in fig. 1, the FPGA chip adopts a regular array structure; the center of the array may be the origin, with horizontal right and left directions being positive and negative directions of the X axis, respectively ("X direction"), and vertical up and down directions being positive and negative directions of the Y axis, respectively ("Y direction").

The dots in the array may be modules, and the modules include CLBs, Random Access Memories (RAMs), programmable Input Output Blocks (IOBs), Digital Signal Processors (DSPs), and the like.

Inside the FPGA chip, the largest number is the CLBs, which are the most basic modules; the 1 CLB generally comprises 2 slices, which can be used for realizing a combinational logic circuit and a sequential logic circuit; the Slice comprises a Slice L type, a Slice M type, a Slice X type and the like.

As shown in fig. 2, the FPGA chip further includes a plurality of Connection line resources, for example, Connection Boxes (CBs) for connecting the input and output terminals of the CLBs to the wiring resources, Switch Boxes (SBs) located at the intersections of the horizontal and vertical wiring channels for selecting the connected segments, and a plurality of segments (segments) connected by the CBs, the SBs describing a topological Connection relationship for converting any one segment to the rest of the segments through a selectable Programmable Interconnection Point (PIP), and a plurality of segments connected by the CBs, the SBs and the PIP may form a net (net) from one Slice to another Slice.

A segment may pass through multiple SB's, and the length of the segment may be defined according to the number of SB's passed, for example, the length of the segment may be X1, X2, X4, X6, X12, and X18, which respectively represent that the length of the segment passes through 1, 2, 4, 6, 12, and 18 SB's.

In the process of layout and wiring of the FPGA chip, the types of the used segment lengths are limited, wherein the segment with the longest length can be called a long segment, and the lengths of the rest segments are smaller than the long segment and can be called short segments.

The long line segment comprises a long line segment positioned in the X direction and a long line segment positioned in the Y direction, and the lengths of the long line segment and the long line segment can be equal or unequal; the short line segments include a short line segment located in the X direction and a short line segment located in the Y direction.

For example, the length of the long line segment in the X direction is 12, and the length of the long line segment in the Y direction is 18.

The types of segments (e.g., short segments, long segments) are based on their length and direction (e.g., X-direction, Y-direction), with different lengths or segments of different lengths belonging to different types.

In an embodiment of the present invention, the time delay of a short line segment or a long line segment may be calculated based on the resistance value and the capacitance value corresponding to one or more wires (Wire) in the line segment and formula (1).

Under the deep submicron manufacturing process, the influence of parasitic parameters (such as parasitic resistance and capacitance) of connecting lines or conducting wires on a path from a source point (source) to a destination point (sink) in a line network of an FPGA chip on time delay cannot be ignored. A resistance-capacitance model (RC model) can be used for approximation, but it is less accurate to consider the resistance and capacitance of a piece of wire as 1 resistance and 1 capacitance based on a lumped model.

The embodiment of the invention provides a distributed RC model.

As shown in fig. 3, a piece of conductive wire may be divided into N pieces, where Ri and Ci represent resistance and capacitance of a certain piece, and i is an integer not less than 1 and not more than N; the time delay of the wire can be calculated by the following formula:

τ1＝R1C1+…+(R1+…+Ri)Ci+…+(R1+…+RN)CN (1)

wherein τ 1 represents the time delay of the section of the wire, R1, Ri and RN represent the resistances of the 1 st, i th and N th sections of the wire, respectively, and C1, Ci and CN represent the capacitances of the 1 st, i th and N th sections of the wire, respectively.

If N is 1, the formula (1) is a calculation mode of the lumped model; the larger the value of N is, the more accurate the calculation result of the formula (1) is.

Fig. 4 is a specific flowchart of a method 100 for creating a delay model of an FPGA circuit according to an embodiment of the present invention, where the FPGA circuit includes multiple slices, and the delay model includes a path delay table.

In the embodiment of the invention, the FPGA chip performs layout and wiring based on the Slice rather than the CLB and other modules, so that the flexibility of layout and wiring is increased on one hand, and the accuracy of time delay calculation is improved on the other hand.

As shown in fig. 5, the 1 Slice includes a plurality of Input pins (Input pins), a plurality of Output pins (Output pins), LUTs, FFs, MUXs, and carry chains.

A path may be formed between any two slices in the FPGA chip, for example, a path from an Input pin or an Output pin of a source Slice (Slice _ source) to an Output pin or an Input pin of a terminal Slice (Slice _ sink).

As shown in fig. 6, the signal goes from Input pin of Slice _ source (i.e., Input of LUT therein), through Output pin thereof, first CB (CB1), SB, second CB (CB2) to Input pin of Slice _ sink (i.e., Input of LUT therein). The coordinates of Slice _ source are (X _ loc1, Y _ loc1), and the coordinates of Slice _ sink are (X _ loc2, Y _ loc 2).

Fig. 6 illustrates that the path from Slice _ source to Slice _ sink passes through only 2 CBs and 1 SB, it being understood that the path from Slice _ source to Slice _ sink may pass through multiple CBs, multiple SBs, multiple slices, several DSPs, and/or several RAMs, etc.

Method 100 may include

steps

110, 120, and 130.

In the execution of step 110, a path from the CB immediately adjacent to and downstream of the Output pin to the CB immediately adjacent to and upstream of the Input pin may be determined based on the coordinates of any two slices, the Output pin of one and the Input pin of the other.

Specifically, for any two Slice in the FPGA chip, one and the other can be respectively used as Slice _ source and Slice _ sink, and the coordinate of Slice _ source, the coordinate of Slice _ sink, the Output pin of Slice _ source, the Input pin of Slice _ sink, and a plurality of segments passing from Slice _ source to Slice _ sink can be determined, so that a path from the CB immediately adjacent to and downstream of the Output pin to the CB immediately adjacent to and upstream of the Input pin is obtained.

In various embodiments of the present invention, upstream and downstream are determined based on the direction of flow of the signal; that is, the direction toward Slice _ source is the upstream direction, and the direction toward Slice _ sink is the downstream direction.

In the execution of step 120, the path delay of the path may be calculated by the following formula:

Path_delay＝Long_delay+Remainder_delay (2)

where, Path _ delay represents Path delay, Long _ delay represents Long-line segment delay generated by a Long-line segment, and Remainder _ delay represents residual delay generated by a short-line segment after the Long-line segment is removed, and includes delay generated by converting at least one Long-line segment into a short-line segment (i.e. delay corresponding to the at least one Long-line segment).

The long-line delay is generated by one, two or more long lines, and can be calculated by the following formula:

Long_delay＝Nx*Long_delayX+Ny*Long_delayY (3)

The residual time delay is generated by a plurality of short line segments, wherein the time delay generated by converting at least one long line segment into the short line segment is included, and therefore the residual time delay is larger than the time delay generated by at least one long line segment; the remaining delay can be calculated by the following equation:

Remainder_delay＝Remainder_delayX+Remainder_delayY (4)

here, Remainder _ delayX represents the remaining delay in the X direction, Mx represents the number of types of X-direction short segments, Pi represents the number of i-th type X-direction short segments, Base _ delayX represents the basic delay of i-th type X-direction short segments, Remainder _ delayY represents the remaining delay in the Y direction, My represents the number of types of Y-direction short segments, Qi represents the number of i-th type Y-direction short segments, and Base _ delayYi represents the basic delay of i-th type Y-direction short segments.

Wherein the remaining delay may include a remaining delay in the X direction generated in the X direction and a remaining delay in the Y direction generated in the Y direction.

The following describes a manner of converting the delay of one X-direction long line segment into the remaining delay in the X direction; the delay of two or more long segments in the X direction can be converted into the remaining delay in the X direction in a similar manner.

If Nx1 is greater than 0, then the remaining delay in the X direction includes the delay caused by converting a long X-direction segment into a short X-direction segment by the following formula:

Nx2＝Nx1-1 (7)

Remainder_X2＝Remainder_X1+Lx (8)

In some embodiments, the remaining _ X1 does not include the time delay caused by the conversion of a long line segment into a short line segment before the conversion of a long line segment into a short line segment; that is, the original number Nx1 of the long line segments in the X direction is an integer obtained by dividing the distance Dx of the two slices in the X direction by Lx, and the length corresponding to the original remaining delay Remainder _ X1 in the X direction is the Remainder obtained by dividing Dx by Lx.

After an X-direction long line segment is converted into an X-direction short line segment, because the splicing of several X-direction short line segments is involved, and thus additional time delay (X-direction additional time delay) is introduced, the remaining _ X2 may further include the X-direction additional time delay, which may be no greater than 1.5 times of the time delay generated by one X-direction long line segment.

In some embodiments, if the remaining _ X1 is not less than the first length, no conversion of X-direction long segments to X-direction short segments may be performed; otherwise, conversion from the long line segment in the X direction to the short line segment in the X direction is performed, so that the types and the number of the short line segments required for combining the Remainder _ X2 after conversion are not too large, and the combination types and the corresponding time delay thereof can be saved through a small storage space.

In a specific implementation, the first length may not exceed an integer multiple of the X-direction long line segment. For example, the X-direction long line segment is 12, and the first length is 8.

The following describes a manner of converting the delay of one Y-direction long line segment into the remaining delay in the Y direction; the delay of two or more long segments in the Y direction can be converted into the remaining delay in the Y direction in a similar manner.

If Ny1 is greater than 0, then the remaining delay in the Y direction includes the delay resulting from converting a long Y-direction segment into a short Y-direction segment by the following equation:

Ny2＝Ny1-1 (9)

Remainder_Y2＝Remainder_Y1+Ly (10)

where Ly represents the time delay of one long line segment in the Y direction, Ny1 represents the original number of long line segments in the Y direction, Ny2 represents the new number of long line segments in the Y direction after one long line segment is converted into a short line segment in the Y direction, Remainder _ Y1 represents the original residual time delay in the Y direction, and Remainder _ Y2 represents the new residual time delay in the Y direction after one long line segment is converted into a short line segment in the Y direction.

In some embodiments, the remaining _ Y1 does not include the delay caused by the long line segment converting to the short line segment before the long line segment converting to the short line segment; that is, the original number Ny1 of the Y-direction long line segments is an integer obtained by dividing the distance Dy of two slices in the Y direction by Ly, and the length corresponding to the original residual delay remainder Y1 in the Y direction is the remainder obtained by dividing Dy by Ly.

After a Y-direction long line segment is converted into a Y-direction short line segment, because splicing a plurality of Y-direction short line segments is involved, thereby introducing an extra delay (Y-direction extra delay), the remaining _ Y2 may further include the Y-direction extra delay, which may be not more than 1.5 times of the delay generated by one Y-direction long line segment.

In some embodiments, if remaining _ Y1 is not less than the second length, no conversion of Y-direction long segments to Y-direction short segments may be performed; otherwise, the conversion from the long line segment in the Y direction to the short line segment in the Y direction is performed, so that the types and the number of the short line segments required for combining the Remainder _ Y2 are not too large after the conversion, and the combined types and the corresponding time delay can be saved through a small storage space.

In a specific implementation, the second length may not exceed an integer multiple of the Y-direction long line segment. For example, the Y-direction long line segment is 18, and the second length is 12.

In the execution of step 130, the coordinates of any two slices, the Output pin of one Slice, the Input pin of the other Slice, and the path delay corresponding to the path between the two slices can be stored in the path delay table.

Embodiments of the present invention contemplate that the path between a source Slice and a terminal Slice passes through multiple slices.

When the distance between two slices is short, one type of short line segment may be used, or several types of short line segments may be combined to connect the two slices (first combination manner). The first combination approach involves only a limited number of combinations of short line segments, with fewer types of combinations. In each combination type, the time delay between the two slices can be calculated through the time delay of the short line segment and the type and the number of the short line segment; and, these combination types and their corresponding delays can be preserved by a smaller storage space.

When the distance between two slices is long, a long line segment may be used, or a long line segment and a short line segment may be combined to connect the two slices (second combination manner). Compared with the first combination mode, the second combination mode has more combination types, and particularly when the distance between two slices is long and a large number of long line segments are needed for combination, the combination types are many. In each combination type, the time delay between the two slices can be calculated through the time delay of the short line segment and the long line segment and the types and the number of the short line segment and the long line segment; however, this requires significant storage space to hold these combination types and their corresponding latencies.

In order to reduce the storage space, the embodiment of the invention converts the long line segment into the short line segment for time delay calculation.

Specifically, embodiments of the present invention create a latency model that includes a path latency table in which the saved path latencies include a latency resulting from a long segment and a residual latency resulting from a short segment and including a latency resulting from the conversion of at least one long segment into a short segment. By converting at least one long line segment or the combination of the long line segment and the short line segment into the combination of the short line segment, the combination times of the second combination mode can be reduced, thereby reducing the storage space required for storing the combination types and the time delay corresponding to the combination types.

In an embodiment of the invention, the latency model may comprise an internal latency table.

Several paths can be determined from an Input pin inside each of the plurality of slices to its Output pin.

The 1 Slice may include 4 LUTs, several FFs and MUXs.

Fig. 7 illustrates 1 LUT (i.e., LUTA, and the remaining 3 LUTs not shown, which may represent LUTB, LUTC, and LUTD), 1 FF, and 1 MUX in 1 Slice.

Each LUT may have several inputs, for example 6 inputs of LUTA (from a1, a2 to a6), 6 inputs of LUTB (from B1, B2 to B6), 6 inputs of LUTC (from C1, C2 to C6), 6 inputs of LUTD (from D1, D2 to D6).

Each LUT may have 1 output, e.g., an output of the LUTA (Pin _ a), an output of the LUTB (Pin _ B), an output of the LUTC (Pin _ C), an output of the LUTD (Pin _ D).

The MUX has an output Pin _ MUX, the FF has an output Pin _ Q. Within 1 Slice, both MUX and FF may have a plurality, and accordingly, both outputs Pin _ MUX and Pin _ Q may also have a plurality, e.g., outputs Pin _ MUXA and Pin _ QA associated with LUTA, outputs Pin _ MUXB and Pin _ QB associated with LUTB, outputs Pin _ MUXC and Pin _ QC associated with LUTC, and outputs Pin _ MUXD and Pin _ QD associated with LUTA.

The Input end of each of the 4 LUTs may be referred to as Input pin of Slice, and the Output end of each of the 4 LUTs, the Output end of the MUX, and the Output end of the FF may be referred to as Output pin of Slice.

As shown in fig. 7, within 1 Slice, there are several lines from its Input pin to Output pin, including: a line (first line) from the input terminal of the LUT to the output terminal of the LUT, a line (second line) from the input terminal of the LUT to the output terminal of the MUX via the MUX, a line (third line) from the input terminal of the LUT to the output terminal of the MUX via the FF and the MUX, a line (fourth line) from the input terminal of the LUT to the output terminal of the FF via the FF; the first circuit and the second circuit are combinational logic circuits, and the third circuit and the fourth circuit are sequential logic circuits.

The internal delay from Input pin to Output pin can be calculated based on several paths respectively.

Within 1 Slice, each of the plurality of lines from each Input pin to each Output pin may be divided by a circuit element (e.g., LUT, FF, MUX) into a plurality of segments of Wire, each segment of Wire having a resistance and a capacitance, thereby forming a circuit similar to fig. 3, and the internal time delay of each line may be calculated by equation (1) respectively; the Input pin comprises respective Input ends of 4 LUTs, and the Output pin comprises respective Output ends of the 4 LUTs, an Output end of the MUX and an Output end of the FF.

The internal delay between the Input pin and the Output pin corresponding to a plurality of paths of each Slice and the two pins can be stored in an internal delay table.

In an embodiment of the invention, the latency model may include a pin latency table.

The Output pin delay of each Slice of the plurality of slices to the Output pin of the CB immediately adjacent to and downstream from the Slice can be calculated, and the Input pin delay of each Slice of the plurality of slices to the Input pin of the CB immediately adjacent to and upstream from the Slice can be calculated.

As described above, Slice includes an LUT, FF and MUX, Input pin includes an Input of the LUT, and Output pin includes an Output of the LUT, an Output of the FF, and an Output of the MUX.

Each Input Pin in any Slice has a CB immediately adjacent to it, and the time delay from the CB to the corresponding Input Pin section of the trace can be calculated (the CB is located upstream of the Input Pin as viewed from the signal transmission path), for example, the time delay of the section of the trace is calculated by formula (1); this delay is associated with the Input pin, which may be referred to as the Input pin delay.

As shown in fig. 6, the time delay from CB2 to Input pin of Slice _ sink is the Input pin time delay.

The time delay from each Output Pin in any Slice to the section of trace of the CB immediately adjacent to the Output Pin (the CB is located downstream of the Output Pin as viewed from the path of signal transmission) can be calculated, for example, the time delay of the section of trace is calculated by formula (1); this delay is associated with the Output pin, which may be referred to as the Output pin delay.

As shown in fig. 6, the delay from Output pin to CB1 of Slice _ source is the Output pin delay.

Because the section of the trace from the Output pin to the CB adjacent to and located downstream of the Output pin and the section of the trace from the Input pin to the CB adjacent to and located upstream of the Input pin are already determined after the FPGA chip is manufactured, and the relevant Output pin delay and Input pin delay are also determined, the Output pin and the Output pin delay corresponding to the Output pin and the Input pin delay corresponding to the Input pin can be stored in the pin delay table, so that the Output pin and the Input pin delay corresponding to the Input pin can be read when needed.

The Output pin and the Output pin delay corresponding thereto, and the Input pin delay corresponding thereto of each Slice may be stored in the pin delay table.

In an embodiment of the invention, the delay model may comprise a modified delay table.

The path from the Output pin to the Input pin can be determined based on the coordinates of any two slices, the Output pin of one Slice and the Input pin of the other Slice, wherein one Slice is Slice _ source and the other Slice is Slice _ sink.

Slice is included in the CLB, but not in the Slice module, and its type includes DSP and RAM.

There may be several non-Slice modules in the path from the source Slice to the terminal Slice, which may cause the time delay to vary. In order to accurately estimate the delay of the path, the modified delay generated by the non-Slice module needs to be considered.

As shown in fig. 8, on the path from Slice _ source to Slice _ sink, the Total _ delay of the path may include the modified delay Modify _ delay generated by the RAM and the DSP, through the RAM and the DSP.

The calculation of the corrected time delay is based on the type of the non-Slice module, and different types of non-Slice modules, such as RAM and DSP, have different corrected time delays; and based on the number of the non-Slice modules, the larger the number is, the larger the corresponding correction time delay is.

The modified delay for a path may be determined based on the type and number of non-Slice modules traversed over the path, etc. That is, the corrected time delays passing through the non-Slice modules of different types are calculated respectively, and then the corrected time delays of the path are obtained by adding the corrected time delays based on the number of the Slice modules of different types.

Specifically, the modified time delay through the non-Slice module may be calculated first.

As shown in fig. 9, the upstream and downstream of the non-Slice module have SB (i.e. SB1, SB2) adjacent thereto, respectively, and are connected to each other by Wire; wherein Wire _1 connects SB1 located upstream, Wire _2 connects SB2 located downstream, and Wire _1 and Wire _2 form a line segment passing through the non-Slice block.

The corrected time delay through the non-Slice module may be calculated by the following equation:

τ2＝In²(R1C1+(R1+R2)C2) (11)

where τ 2 represents the correction delay, In²Representing the square of the value of the logarithm base on e, R1 and C1 represent the resistance and capacitance values, respectively, for Wire1, and R2 and C2 represent the resistance and capacitance values, respectively, for Wire 2.

The modified delay table may include a first table and a second table.

Each line of the first table can record a number corresponding to each line segment passing through each non-Slice module on one path, and the number corresponds to the line number of the second table; each line of the second table records the resistance value and the capacitance value corresponding to each Wire in the line segment passing through the non-Slice module.

As illustrated in table 1, rows 1-5 correspond to 5 paths each having a line segment passing through one or more non-Slice modules, e.g., the first row includes 4 line segments, and the respective associated resistance and capacitance values can be found in rows 122, 133, 12, and 19 of the second table.

TABLE 1

The resistance and capacitance values corresponding to Wire in a line segment passing through a non-Slice block may be obtained from the corresponding row of the second table.

As shown in table 2, lines 1-5 correspond to 5 non-Slice modules or 5 line segments associated therewith, where line 2 represents the abscissa and ordinate of the non-Slice module, R1 and C1 represent the resistance and capacitance values of Wire _1 in the line segment passing through the non-Slice module, and R2 and C2 represent the resistance and capacitance values of Wire _2 in the line segment passing through the non-Slice module.

In some cases, one or both of Wire _1 and Wire _2 have a resistance value and/or a capacitance value of 0. For example, in each of the 3 rd to 5 th rows of table 2, the resistance value and the capacitance value of Wire _2 are both 0, and therefore, the values are not recorded in the table.

TABLE 2

After obtaining the resistance value and the capacitance value corresponding to Wire connected with a non-Slice module, calculating the correction time delay passing through the non-Slice module based on a formula (3); then, the corrected time delays of the non-Slice modules in one row of the first table can be respectively calculated, and the corrected time delays are accumulated, so that the corrected time delay of one path is obtained; then, similar calculation can be performed on each row of the first table, so that the corrected time delay of each path between any two slices in the FPGA chip can be obtained.

By setting two tables (a first table and a second table), each path can multiplex the correction time delay passing through the non-Slice module, which greatly saves the storage space and correspondingly reduces the time for searching the correction time delays.

Even non-Slice modules of the same type may have different location delays if they are in different locations. Thus, the modified time delay may include a position time delay determined based on the position of the non-Slice module. The position delay may be obtained based on a test.

The coordinates of any two slices, the Output pin of one Slice, the Input pin of the other Slice and the corrected time delay of the path can be stored in the corrected time delay table, so that the corrected time delay of the corresponding path can be found based on the coordinates of the two slices, the Output pin of one Slice and the Input pin of the other Slice.

Embodiments of the present invention further provide an apparatus for creating a delay model of an FPGA circuit, including a memory and a processor, where the memory stores computer instructions executable on the processor, and the processor executes the computer instructions to perform the steps of the method for creating a delay model of an FPGA circuit described above with reference to fig. 1 to 9.

The embodiment of the invention also provides a method for obtaining the FPGA circuit time delay according to the time delay model.

After layout and wiring are carried out on the FPGA chip, time sequence simulation can be carried out. Any one of the paths may be selected for analysis to estimate its delay. The delay may include a static delay and a dynamic delay.

The static time delay comprises the internal time delay and the pin time delay of the Slice, is independent of a path and is only influenced by the designed logic, and the internal time delay and the pin time delay of the Slice are static and unchangeable after the design is determined.

The dynamic delay includes path delay and correction delay, which are affected by the layout and routing algorithm, and different algorithms may make the path from the starting point to the end point different, and the correction delay may also be different, thereby obtaining different delay results.

As shown in fig. 10, a method 200 of obtaining FPGA circuit latency includes

steps

210, 220, and 230.

In the execution of step 210, the internal delay of the source Slice and the internal delay of the terminal Slice are respectively obtained from the internal delay table based on the Output pin of the source Slice and the Input pin of the terminal Slice.

In the execution of step 220, a path delay from a first connection box immediately adjacent to and downstream from the Output pin to a second connection box immediately adjacent to and upstream from the Input pin is obtained from the path delay table based on the coordinates of the source Slice and the Output pin, and the coordinates of the terminal Slice and the Input pin.

In the execution of step 230, the first total time delay from the source Slice to the terminal Slice is calculated by the following formula:

Total_delay1＝Inertal_delay+Path_delay (12)

where Total _ delay1 denotes a first Total delay, initial _ delay denotes an internal delay including an internal delay of the source Slice and an internal delay of the terminal Slice, and Path _ delay denotes a Path delay.

The total time delay from the source Slice to the terminal Slice may also include the pin time delay in the path.

The Output pin delay of the source Slice and the Input pin delay of the terminal Slice can be respectively obtained from the pin delay table based on the Output pin of the source Slice and the Input pin of the terminal Slice.

The second total time delay from the source Slice to the terminal Slice may be calculated by the following formula:

Total_delay2＝Inertal_delay+Pin_delay+Path_delay (13)

The total time delay from the source Slice to the terminal Slice may also comprise the modified time delay of the path.

The corrected delays from Output pin to Input pin can be obtained from the corrected delay table based on the coordinates of the source Slice and the Output pin, and the coordinates of the terminal Slice and the Input pin.

The third total time delay from the source Slice to the terminal Slice may be calculated by the following formula:

Total_delay3＝Inertal_delay+Pin_delay+Path_delay+Modify_delay (14)

The embodiment of the invention also provides equipment for acquiring the time delay of the FPGA circuit, which comprises a memory and a processor, wherein the memory is stored with a computer instruction capable of running on the processor, and the processor executes the steps of the method for acquiring the time delay of the FPGA circuit when running the computer instruction.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.

Claims

1. A method for creating a delay model of an FPGA circuit, wherein the FPGA circuit comprises a plurality of slices, the delay model comprises a path delay table, and the method comprises:

determining a path from a first junction box immediately adjacent and downstream of the output pin to a second junction box immediately adjacent and upstream of the input pin based on coordinates of any two slices, the output pin of one and the input pin of the other;

calculating the path delay of the path by the following formula:

the Path _ delay represents the Path delay, the Long _ delay represents the Long-line-segment delay generated by the Long-line segment, and the Remainder _ delay represents the residual delay generated by the short-line segment after the Long-line segment is removed, wherein the residual delay comprises the delay generated by converting at least one Long-line segment into the short-line segment;

and storing the coordinates of any two slices, the output pin of one Slice, the input pin of the other Slice and the path delay in the path delay table.

2. The method of claim 1, comprising calculating the long line segment delay by the formula:

long _ delay ═ Nx Long _ delay X + Ny Long _ delay Y, where Nx denotes the number of Long segments in the X direction, Long _ delay X denotes the time delay of the Long segments in the X direction, Ny denotes the number of Long segments in the Y direction, and Long _ delay Y denotes the time delay of the Long segments in the Y direction.

3. The method of claim 1, comprising calculating the residual delay by the formula:

Remainder_delay＝Remainder_delayX+Remainder_delayY，

4. The method of claim 3, wherein the short line segment type is determined based on a length and a direction of a line segment.

5. The method of claim 3, including, if Nx1 is greater than 0, making the remaining delay in the X direction include a delay resulting from converting a long X-direction line segment into a short X-direction line segment by the following formula:

Nx2＝Nx1-1，

Remainder_X2＝Remainder_X1+Lx，

wherein Lx represents the time delay of one long line segment in the X direction, Nx1 represents the original number of the long line segments in the X direction, Nx2 represents the new number of the long line segments in the X direction after one long line segment is converted into a short line segment in the X direction, Remainder _ X1 represents the original residual time delay in the X direction, and Remainder _ X2 represents the new residual time delay in the X direction after one long line segment is converted into a short line segment in the X direction.

6. The method of claim 5, wherein the remaining delay in the X direction comprises an extra delay in the X direction.

7. The method of claim 3, including, if Ny1 is greater than 0, making the remaining delay in the Y direction include the delay resulting from converting a long Y-direction segment into a short Y-direction segment by the following equation:

Ny2＝Ny1-1，

Remainder_Y2＝Remainder_Y1+Ly，

where Ly represents the length of one long line segment in the Y direction, Ny1 represents the original number of the long line segments in the Y direction, Ny2 represents the new number of the long line segments in the Y direction after one long line segment is converted into a short line segment in the Y direction, Remainder _ Y1 represents the original residual delay in the Y direction, and Remainder _ Y2 represents the new residual delay in the Y direction after one long line segment is converted into a short line segment in the Y direction.

8. The method of claim 7, wherein the residual latency in the Y-direction comprises an extra latency in the Y-direction.

9. The method of claim 1, wherein the latency model comprises an internal latency table, the method comprising:

determining a number of paths from an input pin to an output pin within each Slice of the plurality of slices;

calculating internal time delays from the input pins to the output pins respectively based on the paths; and storing the internal time delay between the input pin and the output pin corresponding to the paths of each Slice and the two pins in the internal time delay table.

10. The method of claim 9, wherein the latency model comprises a pin latency table, the method comprising:

calculating the time delay from the output pin of each Slice in the plurality of slices to the output pin of the first junction box which is adjacent to and located at the downstream of the Slice;

calculating an input pin delay of each Slice of the plurality of slices to an input pin of a second junction box immediately adjacent and upstream therefrom;

and storing the output pin time delay of each Slice and the output pin time delay corresponding to the output pin time delay, and the input pin time delay corresponding to the input pin time delay into the pin time delay table.

11. The method of claim 9 or 10, wherein the Slice comprises a LUT, a FF, and a MUX, wherein the input pins comprise inputs of the LUT, and wherein the output pins comprise outputs of the LUT, outputs of the FF, and outputs of the MUX.

12. The method of claim 10, wherein the delay model comprises a modified delay table, the method comprising:

determining a path from the output pin to the input pin based on the coordinates of any two slices, the output pin of one and the input pin of the other;

determining the types and the number of the non-Slice modules passing through the path;

obtaining a corrected time delay based on the type and the number of the non-Slice modules;

and storing the coordinates of any two slices, the output pin of one Slice, the input pin of the other Slice and the correction time delay of the path in the correction time delay table.

13. The method of claim 12, wherein the types of non-Slice modules include DSP and RAM.

14. The method of claim 12, wherein the modified delay table comprises a first table and a second table, the method comprising:

recording the corresponding line number of each line segment passing through each non-Slice module in a path in the second table through the related line of the first table;

respectively recording resistance values and capacitance values respectively corresponding to connecting lines in the line segments through each line of the second table;

calculating a corrected time delay through the non-Slice module by the following formula:

τ2＝In²(R1C1+(R1+R2)C2)，

wherein τ 2 represents the corrected time delay through the non-Slice module, In²The square of the value representing the logarithm of the base e, R1 and C1 represent the resistance and capacitance values, respectively, corresponding to the connection of the non-Slice module to the connection box immediately adjacent and upstream thereof, and R2 and C2 represent the resistance and capacitance values, respectively, corresponding to the connection of the non-Slice module to the connection box immediately adjacent and downstream thereof.

15. An apparatus for creating a latency model of an FPGA circuit, comprising a memory and a processor, the memory having stored thereon computer instructions executable on the processor, wherein the processor, when executing the computer instructions, performs the steps of the method of creating a latency model of an FPGA circuit of any one of claims 1 to 14.

16. The method for obtaining the delay of the FPGA circuit according to the delay model of claim 12, comprising:

respectively acquiring the internal time delay of a source Slice and the internal time delay of a terminal Slice from the internal time delay table based on an output pin of the source Slice and an input pin of the terminal Slice;

acquiring a path delay from a first connection box which is adjacent to and located at the downstream of the output pin to a second connection box which is adjacent to and located at the upstream of the input pin from the path delay table based on the coordinates and the output pin of the source Slice and the coordinates and the input pin of the terminal Slice;

calculating a first total time delay from the source Slice to the terminal Slice by the following formula:

Total_delay1＝inertal_delay+Path_delay，

wherein, Total _ delay1 represents the first Total delay, initial _ delay represents the internal delay, which includes the internal delay of the source Slice and the internal delay of the terminal Slice, and Path _ delay represents the Path delay.

17. The method of claim 16, comprising:

respectively acquiring the time delay of an output pin of a source Slice and the time delay of an input pin of a terminal Slice from the pin time delay table based on the output pin of the source Slice and the input pin of the terminal Slice;

calculating a second total time delay from the source Slice to the terminal Slice by the following formula:

Total_delay2＝Inertal_delay+Pin_delay+Path_delay，

wherein Total _ delay2 represents the second Total delay, and Pin _ delay represents the Pin delay, which includes the output Pin delay of the source Slice and the input Pin delay of the terminal Slice.

18. The method of claim 17, comprising:

acquiring a correction time delay from the output pin to the input pin from the correction time delay table based on the coordinate and the output pin of the source Slice and the coordinate and the input pin of the terminal Slice;

calculating a third total time delay from the source Slice to the terminal Slice by:

Total_delay3＝Inertal_delay+Pin_delay+Path_delay+Modify_delay，

wherein Total _ delay3 represents the third Total delay and modification _ delay represents the modified delay.

19. An apparatus for acquiring latency of an FPGA circuit, comprising a memory and a processor, the memory having stored thereon computer instructions executable on the processor, wherein the processor, when executing the computer instructions, performs the steps of the method of acquiring latency of an FPGA circuit of any one of claims 16 to 18.