KR100503551B1 - Crosstalk analysis method, method for designing/manufacturing electronic circuit device by using the same, and recorded medium of electronic circuit library therefor - Google Patents

Abstract

The delay time in the electronic circuit device in which the respective signal arrival times in the target wiring and the plurality of wirings adjacent to the target wiring dynamically change depending on the input signal pattern is analyzed by the delay time deterioration caused by the cross- It is a technique to calculate good. The delay time deterioration occurring in each pair of the target wiring and the adjacent wiring is calculated for each signal arrival time of the target wiring using the information of the delay time deterioration that can be searched by the relative signal arrival time between the target wiring and the adjacent wiring By adding them, the total delay time deterioration in the case where a plurality of adjacent wirings exist is calculated. It is possible to easily design a high-speed and large-scale electronic circuit device and to eliminate an extra margin at a delay time, so that the electronic circuit device can be efficiently designed and manufactured.

Description

TECHNICAL FIELD [0001] The present invention relates to a crosstalk analysis method, a method of designing or manufacturing an electronic circuit device using the same, and a recording medium of an electronic circuit library for the same. BACKGROUND ART [0002] Crosstalk analysis methods are disclosed in Japanese Unexamined Patent Appl. }

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of analyzing a crosstalk between a plurality of adjacent wirings in a semiconductor integrated circuit device or an electronic circuit device mounted on a printed circuit board or the like, a method of calculating a delay time, .

Conventionally, when a logic circuit is realized, a large or small electronic circuit having a certain logic function called a circuit cell or a block (also referred to as a circuit unit) is placed on a semiconductor integrated circuit chip or in a package or on a substrate, And the input / output terminals of the input / output terminals are connected by metal wiring.

It is economically advantageous to realize a semiconductor integrated circuit chip, a package module, and a substrate-based system to be designed in a smaller area. Therefore, it is preferable to make the integration density or the mounting density of the above-mentioned cell or block or wiring as large as possible Do. For this reason, miniaturization of processing technology has been promoted in the semiconductor integrated circuit, and in mounting technology, mounting in a package and mounting of a substrate have been promoted. However, attempts to store a large number of elements or wires in a small area have caused various problems. One problem is the problem of signal cross talk.

Signal crosstalk is interference of signals generated between wirings when a plurality of wirings are disposed at physically close positions. Generally, an integrated circuit or a system is designed so that a function to be processed by a circuit is finished within a predetermined delay time so that the integrated circuit or system can operate at a target frequency given by a specification.

At this time, if the design is performed without considering the crosstalk, a change in the delay time caused by the influence of the signal interference is overlooked, so that a situation occurs that the semiconductor integrated circuit chip or system does not operate at the target frequency. To avoid such a situation, there is a need for a method for precisely analyzing the deterioration of the delay time caused by crosstalk.

Methods of analyzing this crosstalk are disclosed in Japanese Patent Laid-Open Nos. 7-98727, 11-40677, and 11-154709.

Although the above-described conventional technique is effective as a crosstalk analysis method, it is based on a limited condition. Therefore, there are various limitations in application to the actual design of the above-described fine and large-scale electronic circuit device. It is difficult to apply it to design.

For example, there is a restriction on the signal transition time of the adjacent wirings, and a combination of the signal arrival time on the wiring under consideration and the signal arrival time on the adjacent wiring greatly affects the delay time. Another limitation is that the signal arrival time to each wiring varies dynamically depending on the input pattern. Particularly, a crosstalk in a high-speed and large-scale electronic circuit device in which a plurality of adjacent wirings are present It is difficult to efficiently and accurately calculate the delay time due to the delay time.

SUMMARY OF THE INVENTION The present invention provides a novel crosstalk analysis method for solving such a problem, and aims at enabling to design and manufacture a high-speed and large-scale electronic circuit device more realistically and efficiently.

More specifically, the present invention relates to an electronic circuit device in which a plurality of different wirings are arranged adjacent to each other in parallel on a single target wiring, and the complicated delay time deterioration due to the cross talk caused by these plural adjacent wirings on the target wiring And a new method of efficiently and precisely estimating the quality of the image.

(Disclosure of the Invention)

As described above, what is difficult in the analysis of the crosstalk is that the influence is changed by the arrival time of the signal.

Therefore, the inventors of the present invention have proposed a new analysis method for solving such a constraint as Proceedings of IEEE International Conference on ASIC / SOC Conference 1999, p.9-13 "Relative Window Method Using Cross-talk Delay Analysis" ).

That is, as shown in Fig. 1, a signal arrival time (hereinafter, referred to as VSAT: Victim Signal Arrival Time) in a wiring 3 (hereinafter referred to as a description wire or a victim) (Hereinafter referred to as ASAT: Aggressor Signal Arrival Time) in the interconnection 4 (hereinafter referred to as an interconnection or an aggressor) which interferes with the interconnection The delay time deterioration occurs (hereinafter, the size is referred to as delay time deterioration value).

Here, the case where the signals arriving at the nodes of the wiring are in an out-phase-transition relationship as shown in the left side of Fig. 1 is handled. Even if the signals are in phase-transition relation, the basic method is the same, but in the case of the in-phase, the delay time becomes smaller than in the case of the reverse phase.

In this cited document 1, a relative signal arrival time (hereinafter referred to as RSAT: Relative Signal Arrival Time) in which ASAT is relatively calculated based on VSAT is used to handle the influence of the signal delay time. Here, a graph or table of delay time deterioration values with the relative signal arrival time (RSAT) on the abscissa as shown in Fig. 2 is used as a driver for driving a victim and an aggressor (for example, ), And the deterioration value of the delay time is calculated by citing the graph or the table whenever it actually occurs.

In addition, this problem is difficult, and there is a point that it changes dynamically (dynamically) depending on an input pattern (including a path) of a signal that VSAT and ASAT itself reach. Figure 3 shows this. For example, in a change of an input pattern, a signal is transmitted from the input node in1 to the node n2 via the node n1, and the signal arrival time at the point n2 in this case is 0.40 ns. However, in the case of another input pattern change, the signal is transferred from in3 to n2. In this case, the signal arrival time at n2 point becomes 0.10 ns, and it changes at the previous value. For this reason, since the RSAT can not be uniquely determined, the degradation graph or table as shown in Fig. 2 can not be simply applied.

In Reference 1, this problem is addressed by using a concept called a relative window.

4 (a), 4 (b) and 4 (c) show the method. VSAT and ASAT vary dynamically by the input pattern, so they can not be obtained at any point in time. Therefore, as shown in Fig. 4A, VSAT and ASAT are calculated as windows having a range (or width) of time in which each signal is likely to actually arrive. Each is called a VSAT window and an ASAT window.

Next, since RSAT can not be determined uniquely, RSAT is calculated as a window having a width (hereinafter referred to as a relative window) as shown in Fig. 4 (b). Here, the relative window is a range from when RSAT becomes minimum to when it becomes maximum. The minimum RSAT is when ASAT is minimum and VSAT is maximized. On the other hand, the maximum RSAT is when the ASAT is the maximum and the VSAT is the minimum. That is, Min (RSAT) = Min (ASAT) -Max (VSAT) and Max (RSAT) = Max (ASAT) -Min (VSAT).

4 (c), the maximum delay deterioration value within the range of the relative window (RSAT) is calculated using the relative window (RSAT) thus obtained and the deterioration value graph or table prepared in advance The quantified delay time degradation value can be obtained.

The delay time deterioration value thus obtained matches very well with the simulation result in an actual circuit, and the accuracy is high.

In general, in a wiring portion in a large scale semiconductor integrated circuit or an electronic circuit device mounted on a substrate, the number of adjacent wirings to a target wiring is not necessarily limited to one. That is, a situation occurs in which a plurality of adjacent wirings cause crosstalk with respect to one target wiring.

However, it has been found that when there is a plurality of adjacent wirings with respect to such one target wiring, there is a problem when trying to apply the crosstalk analysis technique of the cited document 1.

5 (a) to 5 (d), a case where two adjacent wirings exist for one target wiring is taken as an example. Based on the analysis method actually calculated by the present inventor, .

5A shows a range of signal arrival times (hereinafter referred to as VSAT, ASAT1, and ASAT2) of one target wiring and two adjacent wirings on the time axis. 5 (b) and 5 (c), the vertical axis represents the delay deterioration value, and a range (hereinafter referred to as a cross talk range) causing a delay time deterioration between the one attention wiring and each adjacent wiring and the relative window Is shown for each of the adjacent wirings.

First, the deterioration value of the delay time is calculated by using the analysis method of the cited document 1 for each adjacent wiring, and the delayed deterioration value characteristic diagrams of Figs. 5 (b) and 5 (c) DD1 as the maximum delay time degradation value serving as a worst case between the first adjacent wiring (the address bus 1) and the target wiring (the big team) and between the second adjacent wiring The DD2 is obtained as the maximum delay time deterioration value in the worst case in the case of the first embodiment.

Next, as shown in FIG. 5 (d), the total sum of delay time deterioration values (DD (total) = ΣDDi = DD1 + DD2 ).

Even when a plurality of adjacent wirings exist, it is possible to estimate the delay deterioration value by performing the above calculation. However, this method has the following problems.

That is, the delay time deterioration value may be considerably larger than the worst value that may actually occur. This will be described with reference to Fig. 5 described above.

Now, as shown in Fig. 5 (a), the conditions under which the worst case and the aggressor (1) cause the worst case are Tv1 = 5.0 ns, and the conditions under which the worst case and the aggressor (2) Tv2 = 7.5 ns. As described above, merely adding the delay time deterioration value in each worst case means that it is assumed that these two conditions are occurring at the same time. Obviously, if it is considered that the worst case of the delay time deterioration value occurs simultaneously with respect to the pair of the target wiring and the adjacent wiring, the total value of the delay time deterioration values is the worst. However, in reality, these two conditions do not occur at the same time. This is because, in both cases, the Big Tim is the same wiring, the signal arrival time (VSAT) can not take two different values at the same time (no difference in propagation time of signals) It is not necessary to take a value.

Considering such a case, the above-mentioned method of simultaneously causing the worst case between the adjacent wirings and the target wiring takes into consideration a case that can not actually occur, and therefore, the delay deterioration value is calculated to be larger than necessary. This situation can be a serious problem especially in cases where the number of adjacent wires is large.

In the present invention, each signal arrival time in the target wiring and the adjacent wiring is dynamically (dynamically) changed in response to not only a case where a plurality of adjacent wirings exist, but also an input pattern change (including a route change) A method for efficiently analyzing the delay time deterioration value caused by the crosstalk more precisely.

More specifically, the present invention relates to a method of calculating a deterioration of a delay time caused by a crosstalk caused by a plurality of adjacent wirings with respect to one target wiring, a margin of an extra delay time that can not occur in the operation of an actual electronic circuit So that the electronic circuit device can be designed and manufactured.

Outline of representative ones of inventions disclosed in the present application will be briefly described as follows.

That is, the present invention can be applied not only to a case where a plurality of adjacent wirings (arcs) exist for one target wiring (big team) but also to a target wiring (adjacent chip) (Referred to as MA-RWM (Multi-Aggressor Relative Window Method), distinct from the RWM) of the delay time deterioration caused by the crosstalk when the signal arrival time of the signal is changed dynamically will be.

In the analysis of the delay time deterioration, the VSAT as the absolute time is not considered only by simply applying the method shown in the reference 1, so that the case where the VSAT is not originally included is included in the analysis. However, And the delay time deterioration characteristics of the respective adjacent wirings on the specific target wiring are obtained by the dynamic signal arriving change in each adjacent wiring, The crosstalk in the case where a plurality of arcs exist can be analyzed with high accuracy.

1 is a diagram showing delay deterioration that varies depending on a combination of signal arrival times (VSAT and ASAT) in two wirings each consisting of one target wiring and one adjacent wiring,

FIG. 2 is a characteristic diagram showing the deterioration of the delay depending on the relative signal arrival time (RSAT)

3 is a diagram showing a change in signal arrival time depending on an input pattern change (signal transmission path change)

4 (a) to 4 (c) are diagrams showing a delay deterioration analysis procedure using a window of RSAT,

5A to 5D are diagrams for explaining analysis of crosstalk caused by a plurality of adjacent wirings for one target wiring,

6 is a view showing steps in a crosstalk analysis procedure according to the present invention,

7 (a) to (f) are diagrams for explaining a crosstalk analysis method according to the present invention,

8 (a) to (f) are diagrams for explaining another analysis method according to the present invention,

9 is a diagram for explaining a design system of a semiconductor integrated circuit or a substrate circuit using an analysis method of delay time deterioration according to the present invention,

10 (a) to 10 (d) are views for explaining an embodiment of the present invention,

11 (a) to (f) are diagrams for explaining the embodiment of the present invention together with FIG. 10,

12 (a) and 12 (b) are views for explaining another embodiment of the present invention,

13 (a) to 13 (f) are views for explaining another embodiment of the present invention,

14 (a) to 14 (c) are diagrams for explaining still another embodiment of the present invention,

15 is a view for explaining another embodiment of the present invention,

16A and 16B are diagrams for explaining library information used in the present invention,

17 (a) to 17 (d) are views for explaining another embodiment of the present invention,

18 is a view for explaining an example of a design system of the present invention and a display display used therefor,

19 is a view for explaining another example of a design system and display of the present invention,

20 is a characteristic diagram in comparison with actual circuit simulation results for explaining the effect of the present invention,

21 is a circuit diagram for explaining an example of applying the present invention when there are three accumulators,

22 (a) to 22 (c) are diagrams for explaining the effect when the present invention is applied to the example of FIG. 21,

23 is a characteristic diagram actually measured for explaining the effect of the present invention.

(Best Mode for Carrying Out the Invention)

An embodiment of the present invention in a crosstalk analysis method in a case where a plurality of wirings are disposed adjacent to one target wiring will be described with reference to Figs. 6 and 7 (a) to (f).

By analyzing the signal arrival time (VSAT) in the target wiring (the big team), it is possible to obtain a plurality of adjacent wirings (arcs) based on the VSAT that can actually occur, It is possible to obtain a worst case of delay deterioration due to the use of a plurality of VSATs which can not occur simultaneously.

First, in the first step, as shown in the frame 601 of Fig. 6, the connection information of the logic block or the logic cell which defines the logical relationship between the logic input of the electronic circuit device to be processed and the logic output, The physical space information of the wiring used is input to the delay time calculation system.

Next, in the second step, as shown in the frame 602, in the calculation of the signal arrival time at at least one node in the logic circuit, calculation of a range in which the signal arrival time at the node can be taken is calculated I do. This step can be calculated by, for example, executing the following procedures (b-1) to (b-4).

(b-1): calculating or retrieving a delay time between input / output of a logic cell or a logical block through which a signal passes from a known node to a target node at a signal arrival time.

(b-2): a step of calculating or searching the delay time of the wiring portion connecting between the logic blocks or the logic cells in the same path as the above (b-1).

(b-3): a step of adding the sum of the delay times obtained in the steps (b-1) and (b-2) to the known signal arrival time of the route,

(b-1), (b-2) and (b-3) are executed for each of the signal propagation paths Steps to calculate the range.

In the third step, as in the case of the frame 603 in Fig. 6, the wirings belonging to the node and the wirings adjacent to the node which have been inspected in the second step are determined from the physical space information of the wirings inputted in the first step, .

As the predetermined condition in this third step, for example, it is possible to use the length of the adjacent wirings. When the capacitive coupling or the inductance coupling per unit length between the target wiring and the adjacent wiring is large, the condition of the parallel length is set to be short, and when the capacitive coupling or the inductance coupling per unit length is small, It is possible. In addition, when the strength of the driver circuit for driving adjacent wirings, that is, the load driving capability, is larger than the predetermined strength, all of the wirings can be viewed as adjacent wirings, or conversely, when the driver circuit has small strength, .

(D-1) to (d-4) using the range of the signal arrival time of the target node obtained by executing the second step as shown in the frame 604 of Fig. 6 in the fourth step, And calculates the deterioration value at the signal arrival time of the target node in consideration of the influence of the adjacent wiring.

(d-1): For the combination of the drive circuit of the target wiring and the drive circuit of the adjacent wiring extracted in the step (c), the delay time deterioration value due to the crosstalk under typical (or typical) And maintaining this as a searchable data format by a time difference relative to the signal arrival time of the target node and the neighboring node (frame 6041 in Fig. 6).

(d-2): a step (frame 6042) of calculating a range of a signal arrival time at a node to which the adjacent wiring extracted in the step (c) belongs.

(d-3): The range of the signal arrival time of the adjacent node calculated in the step (d-2) is converted into the range of the relative signal arrival time with reference to the signal arrival time of the target node, A step (frame 6043) of selecting a maximum value from the delay time deterioration value data obtained in the step (d-1) among the reaching time ranges and maintaining this as a searchable data format for each signal arrival time of the target node.

(d-4): In the step (d-1), with respect to the combination of the plurality of wirings adjacent to the target wiring, the signal arriving time at the target node, Adding the respective delay time deterioration values to each other, and maintaining this delay time degradation value for each signal arrival time of the target node (frame 6044).

It is also preferable that the step (d-1) is preliminarily calculated and stored in a library form according to the kind of the drive circuit and intensity classification used. When such a library is stored in a storage medium on a computer, it becomes possible to use the data immediately after searching for the analysis of the delay time deterioration for each individual design. Such a library may also be described in a data book in a silicon foundry service called a so-called standard cell series or a gate array series.

However, it is common that a case actually encountered for each design does not completely match the condition in which the library is acquired. Therefore, it is preferable to use the information of the library in accordance with the conditions to be encountered.

For example, in the case where the parallel length in the facing condition is a certain multiple of the parallel length in the condition in which the library is acquired (it is not necessarily an integral multiple, and may be a real number), the delay deterioration value described in the library is multiplied by It is possible. Such correction need not always be performed at the same ratio, but it is also possible to perform correction using a calculation formula suitable for a plurality of experimental values.

Also, the condition for acquiring the library is not necessarily one condition. It is also considered to use a combination of libraries acquired under a plurality of conditions in order to mimic the confronting condition.

Next, as shown in (d-2) to (d-4) above, the step of calculating the delay time deterioration value in consideration of the VSAT as the absolute time is described specifically with reference to Figs. 7A to 7F Explain.

Fig. 7A shows the signal arrival time and its range (hereinafter referred to as VSAT, ASAT1, and ASAT2) that can occur in the target wiring on the time axis and two adjacent wirings on the time axis as shown in Fig.

7B and 7C are graphs of delay time deterioration characteristics between a relative signal arrival time (RSAT) on the abscissa and a delay time deterioration value on the ordinate, (RSAT) at which the delay time degradation occurs when the VSAT is minimum (i.e., Tv1 = 5.0 ns in Fig. 7 (a)) between each of the two adjacent wirings (RSAT window) is shown in bold line at the bottom of the chart.

In addition, as the VSAT is increased, arrows are shown at the bottom of the diagram to show how the window of the RSAT moves. That is, the bold lines on the lower left of (b) and (c) of FIG. 7 indicate the range (in the case where VSAT is the maximum) (i.e., Tv2 = 7.5 ns in FIG. RSAT window).

Here, the range that the RSAT can take at the minimum time and the maximum time of the VSAT is described in order to facilitate understanding. However, as indicated by an arrow in the diagram, the entire range of the VSAT is swept, A range (RSAT window) of RSAT is calculated for each execution (that is, for each signal arrival time to the target wiring primary team).

7 (d) and 7 (e) are graphs showing the relationship between the VSAT absolute time (that is, the signal arrival time that can be taken in the target wiring) as a horizontal axis and the maximum Values plotted on the vertical axis and the delay time degradation characteristics of the adjacent wirings (the arcs 1 and 2) on the target wiring (the big team) are shown by the execution angle base of the VSAT.

7F shows the characteristics of the delay time deterioration value with respect to all the adjacent wirings (here, with respect to the arithmetic operation (1) and the arithmetic operation (2) Signal arrival time) as a reference.

The delay time deterioration value DDtotal 2 is obtained by calculating the maximum value (DD2 in this example) of the delay time deterioration value within the window of VSAT (the operating angle is 5 to 8 ns) using the graph f thus obtained Can be obtained.

Here, as described above, it is possible to obtain the deterioration value for one VSAT that can actually occur without adding the maximum deterioration of two VSATs, which can not be compatible with each other.

As a result, the delay time degradation value DDtotal2 calculated by the method of the present invention becomes a value smaller than the delay time degradation value (DDtotal = DD1 + DD2) obtained by the conventional method, and the precision is improved.

Here, in order to confirm the effectiveness of this method, the delay time deterioration in an actual electronic circuit having the crosstalk from the above-mentioned two accumulators will be described in comparison with a measurement result by a simulation at a circuit level. The results are shown in Fig. 20, and the graph of the delay time degradation value calculated by the MA-RWM of the present invention as shown in the diagram substantially coincides very well with the result of circuit simulation.

In addition, since the delay time deterioration value is obtained for each signal arrival time of the VSAT, it can be seen that the case where the delay time deterioration value becomes the maximum is not necessarily the worst case when viewed from the signal transmitted to the next block or cell. In other words, it can be seen that the worst case in the case of the signal transmitted to the next step is the case where the sum of the signal arrival time (VSAT) of the target wiring and the delay time deterioration value becomes the maximum.

A method for efficiently processing the analysis of the delay time deterioration value due to crosstalk on the computer using the above technique of the present invention will be described below.

The delay time degradation graph or table is represented by plots giving the correspondence between the relative signal arrival time (RSAT) and the delay time degradation value as shown in FIG. In order to generate the graph information shown in (d), (e), and (f) of FIG. 7 using this, it is necessary to perform calculations as many as the number of plots. Therefore, when the delay time analysis is performed in consideration of crosstalk using the present invention, the calculation time may become bulky depending on the target circuit scale.

A method for solving this is shown in Figs. 8 (a) to 8 (f). FIG. 8A shows the relationship between VSAT and windows of ASAT1 and ASAT2 as shown in FIG. 7A. 8B and 8C show the delay time degradation table approximated by several straight lines instead of being plotted as shown in Figs. 7B and 7C. In the same figure, several characteristic points for determining a straight line are shown.

(D) (e) and (f) in FIG. 8 are diagrams showing the VSAT absolute time (signal arrival time that can be taken in the target wiring) as abscissa, as shown in (d) The maximum value of the delay time deterioration value in the ASAT window based on the VSAT is represented by the vertical axis and the sum of the values is shown in FIG. And connecting them by a straight line.

In this case, since it is not necessary to perform addition on many plots in order to obtain the delay time deterioration value, calculation using a computer or the like can be performed at a high speed. In addition, with respect to the retrieval of the maximum value in the VSAT range, the fact that the addition result of the value given by the straight line is likely to be the maximum is only in the characteristic point, and therefore, .

9, the present invention uses an automatic designing apparatus 901 including an arithmetic processing unit, a storage unit, and a man-machine interface, as shown in 902 as described above, Not only the delay time itself can be calculated but also the circuit or system having a performance superior to the conventional one can be provided by changing the configuration of the logic circuit or changing the arrangement or wiring position as indicated by 903 by using the information obtained therefrom .

Other objects and novel features of the present invention will be apparent from the following Examples. Hereinafter, various embodiments of the present invention will be described with reference to the drawings.

Example 1:

10 (a) to 10 (d) and 11 (a) to (f).

10 (a) shows a state in which a logic circuit is physically connected to a wiring. The wiring (corresponding to the node E) serving as the output of the gate circuit g2 corresponds to two wirings (corresponding to the nodes J and N) which are the outputs of the other two gate circuits g5 and g6. Thereby causing crosstalk 1001 and 1002 from a plurality of (two in the figure) adjacent wirings (arrays) 1004 and 1005 to one attention wiring (big team) 1003 .

Here, the parallel length of the target wiring and the adjacent wiring is given as shown in Fig. 10 (b). In addition, it is assumed that the signal delay time from the node A to the node F is set to 1.7 ns in the design of the entire system. It is assumed that the signal delay time between input and output of each gate circuit is given as shown in FIG. 10 (c).

First, when it is assumed that there is no crosstalk, the signal arrival time at each node in Fig. 10A is calculated as shown in Fig. 10D.

Here, for example, when the signal arrival time of the node E which is a target wiring is viewed, the minimum signal arrival time is 0.6 ns and the maximum signal arrival time is 1.2 ns. The reason why the signal arrival time can not be uniquely determined as described above is as described above. Similarly, for the node J and the node N which are adjacent wires, the signal arrival time is not uniquely determined and has a window (or time width) between the minimum signal arrival time and the maximum signal arrival time.

Next, the steps of calculating delay time degradation due to crosstalk using these signal arrival time information will be described with reference to Figs. 11 (a) to 11 (f).

11A shows a signal arrival time VSAT of a target wiring (node E) and two adjacent wirings (node J and node N) based on the information of Fig. ) Are the windows of the signal arrival times ASAT1 and ASAT2.

As shown in FIG. 11 (b), a pair of a 2-input NAND circuit and a 2-input NOR circuit for driving a target wiring and an adjacent wiring are set so that a relative (relative) A graph or table showing the relationship between the signal arrival time (RSAT) and the delay deterioration value is given as a library. In this manner, it is preferable that circuit data is prepared using the adjacent parallel length as a parameter. It is also preferable that a plurality of other adjacent parallel lengths are set as described in the later-described embodiments, and the data of the RSAT and the delay time deterioration value at that time are given by an experiment, a circuit simulation or the like in advance as an electronic circuit library.

11 (c) shows a similar library for a pair of a 2-input NAND circuit and a 2-input OR circuit for driving a target wiring and an adjacent wiring. In the circuit shown in FIG. 10 (a) Since the actual adjacent parallel length of the wiring is 400 mu m, the graph of the delay deterioration value registered in the library made under the condition of the adjacent parallel length of 500 mu m is reduced and corrected to a value in the case of 400 mu m. In the lower part of the graphs of (b) and (c), arrows are used to indicate that the window of the relative signal arrival time when the VSAT is the minimum moves to the window when the VSAT is the maximum.

11 (d) and 11 (e) show the maximum delay deterioration value in the window range for each VSAT in the range that the VSAT can take. (D) and (e) show the delay time deterioration characteristics which are caused by signals arriving at the target wiring by the arriving signals at the adjacent wirings 1 and 2, respectively.

The characteristics of the plurality of (d) and (e) are superimposed on the basis of the absolute time of VSAT or the operating angle (that is, the signal arrival time in the target wiring), and the delay time Fig. 11 (f) shows the addition of the degradation values.

The maximum value of the delay time deterioration value thus obtained is 0.325 ns when VSAT = 1.0 ns in the characteristic diagram of (f).

As a result, assuming that there is no crosstalk, the delay time at the node F is 1.5 ns. However, since the maximum value of the delay time deterioration obtained by the above calculation is 0.325 ns, Is 1.5 ns + 0.325 ns = 1.825 ns, which indicates that the design time limit of 1.7 ns is not satisfied.

If more detailed analysis is possible, the delay time deterioration value for each VSAT is known as shown in FIG. 11 (f) in the present invention.

In other words, the VSAT at the node E in the above case is 1.0 ns, and this increases by 0.325 ns to 1.325 ns, and the delay time at the node F is added by 0.3 ns to become 1.625 ns. 11 (f), the VSAT at the node E increases by 0.3 ns to 1.4 ns, and the delay time at the node F becomes 0.3 ns is added and becomes 1.7 ns. 11 (f), the VSAT at the node E increases by 0.233 ns to 1.433 ns at the node E, and the delay time at the node F becomes 0.3 ns is added to 1.733 ns.

From these, it can be seen that the maximum constraint violation at the node F due to crosstalk is 1.733ns-1.7ns = 0.033ns when VSAT = 1.2ns.

Thus, by using the present invention as described above, the designer can confirm that the designed circuit does not operate correctly within the design constraint time when there is crosstalk, It is possible to reduce time and cost required for designing and manufacturing an actual LSI, time and cost required for modification of the design, and the like.

Example 2:

An example of the case of correcting the wiring after the delay time calculation in the first embodiment will be described based on Figs. 12 (a) and (b) and Figs. 13 (a) to 13 (f).

The circuit of Fig. 12 (a) is the same circuit as that shown in Fig. 10 (a). First, by analyzing the delay time deterioration value by the crosstalk as described in the first embodiment, it can be understood that this circuit does not satisfy the constraint condition.

Here, in order to correct the violation of the constraint condition, attention is paid to the crosstalk 1201 with the second adjacent interconnection, and a gate circuit 1203 for delaying the signal arrival time at the adjacent interconnection portion as shown in Fig. 12 (b) And 1204 are inserted to modify or modify the circuit. How these variations or modifications solve the constraint violation will be described with reference to Figs. 13 (a) to 13 (f).

Fig. 13 (a) shows a state in which the signal arrival time at the second adjacent wiring node P changes due to the above circuit deformation. As a result, the operation of the RSAT window in the lower part of Fig. 13 (c) and the characteristic of the delay time degradation value for each VSAT in Fig. 13 (e) change.

13 (f) is obtained by superimposing the delay time deterioration value due to the crosstalk from two adjacent wirings based on the signal arrival time at the target wiring. Here, the maximum delay time deterioration value is 0.2 ns, whereby the delay time at point F when crosstalk is taken into consideration is 1.5 ns + 0.2 ns = 1.7 ns, and it is possible to satisfy the constraint condition of the original design Able to know.

If more detailed analysis is required, the VSAT at the node E in the case of the maximum delay deterioration value is 1.0 ns, which increases by 0.2 ns to 1.2 ns, and the delay at the node (F) The time is added by 0.3 ns to 1.525 ns, and it can be understood that the constraint condition 1.7 ns can be satisfied.

13 (f), the VSAT at node E increases by 0.175 ns to 1.375 ns, and the delay time at node F is 0.175 ns. 0.3 ns is added to become 1.675 ns. It can be seen from these results that the constraint condition 1.7 ns can be satisfied at the node F due to crosstalk.

As described above, after calculating the delay time in the analyzing method of the present invention, it is possible to easily solve the problem by moving the signal arrival time on the time axis in the adjacent wiring causing the constraint violation.

Various methods can be used for moving the signal arrival time on the time axis. For example, the delay gate may be inserted as in the above example, or the delay element may be a combination of resistance and capacitance. It is also possible to delay the arrival time of the signal by moving the gate position to be the driving circuit and locating it at a part distant from the crosstalk part intentionally. It is also possible to insert a delay element on the signal transmission path of the target wiring.

For example, when the circuit shown in Fig. 14 (a) is modified or modified to a circuit as shown in Fig. 14 (b) or 14 (c), a graph showing the VSAT- It is easy to know that the amount of deterioration is reduced.

Example 3:

It is another object of the present invention to realize a semiconductor integrated circuit, an in-package circuit and a printed circuit board having excellent characteristics for analyzing delay time deterioration due to the influence of crosstalk from a plurality of adjacent wirings by using the crosstalk analysis method of the present invention An example thereof will be described with reference to Fig. In the case of a semiconductor integrated circuit, crosstalk can occur in the wiring between the logic cells or in the wiring between the blocks, as indicated by 1505 and 1506 in the figure, and when a plurality of chips are connected in the package in the package, Crosstalk can occur. Also, as shown in 1507 and 1508 in the drawings, the same crosstalk may also occur in the circuit on the printed circuit board and also in the wiring between the semiconductor packages and the wiring between the individual elements.

In such a case, according to the present invention, it becomes possible to create a semiconductor integrated circuit, an in-package circuit, and a circuit on a substrate in which the delay time considering crosstalk is described as specification data in a data block or the like. Moreover, it is possible to reduce the influence of various crosstalk described above by using the above-described technique, and to produce an improved semiconductor integrated circuit, an in-package circuit, and a circuit on a board as represented by a circuit diagram on the lower left side of Fig. Do.

Example 4:

It is also possible to carry out experiments or circuit simulations in advance (step 6041 in Fig. 6) described in the head portion (d-1) of the embodiment of the present invention, 16A and 16B illustrate examples of data formats in which data is recorded and stored in a recording medium such as an optical device or a magnetic device so as to be writable on the recording medium.

16 (a) shows a case in which the driving circuit of the target wiring (the big team) has the 2-fold strength of the NAND2 gate (the load driving ability) and the driving circuit of the adjacent wiring (the accumulator) (Library) of the relative signal arrival time and the delay time deterioration value in combination with the case of the case where the relative signal arrival time and the delay time degradation value are combined. 16 (b) is a graph showing the relationship between the strength of the gate of the NAND gate and the strength of the gate of the inverter (INV) when the drive circuit of the target wiring (the big team) (Library) of the relative signal arrival time and the delay time degradation value in the combination of the relative signal arrival time and the delay time degradation value.

As described above, the conditions for various combinations of circuit blocks connected to the output portion of the wiring and the load driving capability of the driving circuit (driver) of the output stage constituting the cell (referred to as a circuit unit) .

As described above, the condition for retrieving the library is not necessarily one, but rather it is preferable to acquire a plurality of conditions. 16 (a) and 16 (b), as an example in the embodiment of the present invention, a library obtained for a plurality of adjacent parallel lengths with a condition of an adjacent parallel length of 500 m and a condition of 1,000 m is shown. When the adjacent parallel length actually encountered is, for example, between 500 mu m and 1,000 mu m, it is possible to obtain the delay time deterioration value in the form of interpolating library data of both. This can avoid the problem that the delay time deterioration value is not accurately calculated in an actual case where the adjacent parallel length is largely different from 500 mu m when the library is acquired under the condition that only the adjacent parallel length is 500 mu m as a single condition have.

As a condition for creating the library as shown in Fig. 16, the wiring length on the side closer to the driver circuit than the wiring portion causing crosstalk in the target wiring (big team) or a plurality of adjacent wiring (argram) It is also possible to obtain the library by changing the wiring length (rear wiring length) on the side far from the drive circuit (reception side). Fig. 17 (a) shows an example of a case of acquiring a library in the case where there is no pre-wiring length or post-wiring length. On the other hand, Fig. 17 (b) shows a case where a library is acquired by setting the length of the electric wire wiring to a certain length. Likewise, FIG. 17 (c) shows a case where a library is acquired by setting the length of a posterior wire to a certain length.

As such, when the electric wiring length and the rear wiring length are present, the delay time deterioration value tends to become larger as compared with the case where they are not present. 17 (d) shows an example of such a delay time deterioration value. 17 (a), the delay time deterioration value in the case where there is no electric wiring line or rear wiring line length is given as a curve 1701 in Fig. 17 (d). 17 (b), the delay time deterioration value increases as the curve 1702 in FIG. 17 (d) shows an increase in the amount of deterioration or deterioration It is common.

Therefore, if a library is acquired by changing a plurality of electric wiring traces or rear wiring traces, for example, if it is necessary to analyze various cases in which the electric wiring traces or rear trace wiring lengths are different, the curves 1701 and 1702 can be interpolated It becomes possible to generate the characteristic curve 1703 of the delay time deterioration information.

Further, it is not necessary to say that it is more efficient if a larger number of conditions can be prepared in advance, such as a combination of the above-described various conditions as a library.

Example 5:

Further, by using the design system using the crosstalk analysis method of the present invention, the designer can more easily calculate the delay time in consideration of the influence of the crosstalk, complete the circuit configuration and the system configuration for avoiding or reducing crosstalk Lt; / RTI > Such an example will be described with reference to FIG.

For example, as shown in the diagram, when there are a plurality of registers and there is a crosstalk from each to the target wiring, the design system 1801 coupled to the calculator described in 901 of Fig. As shown in 1802 and 1803 on the display screen, the delay time deterioration characteristic diagram due to the crosstalk from each adjacent wiring line is displayed while being separately displayed for the calculation of the delay time, It is very effective to display the characteristic diagram representing the total value of the influence from each adjacent wiring line side by side on the screen. That is, the plurality of characteristics of the delay time deterioration value based on the operating angle of the VSAT (i.e., the signal arrival time in the target wiring) described in Figs. 7, 8, 11, or 13D- And displays the figure on one screen. Further, these plurality of characteristic diagrams may be displayed on separate screens as necessary, but it is easier for designers to display them on the same screen.

In this way, the designer can easily find the magnitude of the effect that each adjacent wiring has on the target wiring, including the change in the dynamic signal arrival time, so that it becomes easy to find a place where a countermeasure should be made, (For example, a method as shown in Figs. 14 (a) to 14 (c), or a method of increasing the inter-wiring distance of some crosstalk points, etc.) ), It is possible to immediately observe and confirm how the sum of the delay time deterioration values due to crosstalk will become as a result of the countermeasures, so that the problem can be effectively solved in a shorter time.

In another example as shown in Fig. 19, how the effect of the delay time deterioration due to crosstalk from each adjacent interconnection (argram) is as library information (curves 1904 and 1907 in the diagram) (1905, 1908) of how the wiring is changed due to the influence of the wiring length of the electric wire (1906, 1909) by the influence of the rear wiring length (1906, 1909) It is also preferable that it is possible.

By using such a design system, not only the delay time deterioration value due to the crosstalk caused by each of the arcs can be easily detected as shown in Fig. 18, but the designer can know that the delay time degradation value is large due to the electric wiring length and the rear wiring length It becomes possible to take an appropriate countermeasure against it.

Such a design system may be mounted not only in a stand alone computer that is not connected to a network but also in a remote computer through a network such as the Internet. In such a case, the process for analyzing the delay time and avoiding or reducing the crosstalk described in the present invention is executed on a computer existing in a remote place, and the input to the computer and the calculation result, which is an output from the computer, Or through a display or input system.

Example 6:

As described above, the crosstalk analysis method (MA-RWM) according to the present invention and the method of designing and manufacturing the electronic circuit device using the same have been described mainly with reference to the case where there are two addresses in order to simplify the understanding. As such, the invention can exert its effects by applying electronic circuit devices having many more elements to an object. This will be described below with reference to Figs. 21 and 22 (a) to 22 (c).

Fig. 21 shows a specific example when three neighboring wirings, that is, agressors 1, 2 and 3, were tested in an electronic circuit arranged close to one target wiring victim. In the figure, AL is the adjacent adjacency length, and each of the arcs shows a situation in which crosstalk 1, 2, and 3 are generated with respect to the target wiring. This circuit has the following relationship between the VSAT window and the ASAT window: To simulate circuits in the states of cases 1 and 2 shown in Figs. 22 (a) and 22 (b).

Fig. 22 (c) shows a case where the delay time deterioration value is calculated by an actual circuit simulation for each of these cases, the case where the delay time degradation value is calculated by the simple method using the RWM, and the case using the MA-RWM of the present invention It is divided into a table and the result is summarized.

From this result, when the VSAT window is narrow and a plurality of window arrays are close to each other as in Case 1 shown in Fig. 4A, the RWM method calculates an error of about 4% and a relatively accurate delay deterioration value from the circuit simulation I can understand what I can do. However, when the VSAT window is large and a plurality of window arrays are relatively spaced apart as in case 2 shown in Fig. 2 (b), the delay time deterioration value is calculated with a very large error (or error) .

On the other hand, in the MA-RWM method of the present invention, it is obvious that the error (or error) is small in either case and the delay time degradation value consistent with the circuit simulation result can be calculated.

As a result of various simulation experiments, it was also confirmed that the error of the delay time deterioration value obtained by the RWM method and the MA-RWM method of the present invention depends on the number of accumulations. In other words, as shown in FIG. 23, in the case of a single number of errors, the error is almost the same as that of the two methods. However, when the number of argrams becomes two or more, a simple RWM method The MA-RWM method of the present invention can produce an error greater than 50%, whereas the delay time deterioration value can be calculated with an error smaller than 10%. It can also be understood from this that the larger the number of the adjacent wirings of the present invention is, for example, the larger the size of the electronic circuit device, the more remarkable the application effect is.

Although the present invention has been described in detail with reference to various exemplary embodiments, the present invention is not limited to the semiconductor integrated circuit device, the electronic circuit device mounted in the package, the electronic circuit device mounted on the substrate, and the electronic circuit system using them, A signal processing processor, an image processing processor, a semiconductor memory, a system module, a computer system, a portable system, and the like having a configuration in which the input / output of the signal delay time is connected to the input / It can be applied to the design and manufacture of devices.

By using the present invention, the analysis of the delay time deterioration considering the crosstalk in which the respective signal arrival times of the target wiring and the adjacent wiring dynamically changes depending on the input pattern as well as when there are a plurality of adjacent wirings, It is done well. It is also possible to realize a system for verifying operation at a certain frequency after considering crosstalk. Particularly, by applying the present invention to a so-called critical path in an electronic circuit device, a high-performance integrated circuit or a substrate-based system in which a countermeasure against crosstalk is made can be efficiently realized.

Claims (10)

A method for analyzing crosstalk of a signal on a plurality of adjacent wirings adjacent to one target wiring on the target wiring, the method comprising the steps of: determining a range in which each of the target wiring and the plurality of adjacent wirings can be taken And the delay time deterioration of each of the adjacent wirings on the target wiring is calculated based on the signal arrival time of the target wiring. In the electronic circuit device having the second and third adjacent wirings disposed adjacent to the first wiring connected to the output portion of the first electronic circuit unit and connected to the output portions of the second and third electronic circuit units respectively Calculating a range of each signal arrival time in each of the wirings based on a signal delay characteristic of each of the electronic circuit units when calculating the crosstalk on the first wiring by the second and third adjacent wirings Based on a signal arrival time of the first wiring and a relative-signal arrival time obtained by relatively measuring a signal arrival time of the second and third wirings on the basis of a signal arrival time of the first wiring, The delay time deterioration value due to the crosstalk affecting the first wiring line is calculated in accordance with the timing of the signal and the delay time deterioration value is added to the first wiring line based on the signal arrival time Calculation of the cross talk of the electronic circuit device as set. A method of analyzing crosstalk of a signal on a plurality of adjacent wirings adjacent to one target wiring on a target wiring, the method comprising the steps of: determining a range of a signal arrival time to each of the adjacent wirings based on a signal arrival time to the target wiring Wherein the plurality of adjacent wirings are connected to each other by the crosstalk to calculate the maximum delay time deterioration value for each of the adjacent wirings on the basis of the signal arrival time to the target wiring, And the total delay time deterioration affecting the target wiring is calculated. A method for manufacturing an electronic circuit device, characterized by manufacturing an electronic circuit device having a plurality of adjacent wirings by using the crosstalk calculating method according to any one of claims 1 to 3. A delay time is calculated in an electronic logic circuit device which is realized by using an automatic designing apparatus having an arithmetic processing unit, a storage unit, and a man-machine interface and in which a plurality of adjacent wirings causing cross- A method for calculating a signal delay time deterioration value by the crosstalk of an electronic circuit device, the method comprising the steps of: calculating a delay time of an electronic circuit device from a program stored on the storage device As a method, (a) a step of inputting connection information of a logic circuit block or logic circuit cell for determining a logical relationship between a logic input and a logic output and physical space information of a wiring used for the connection, (b) calculating in a calculation of a signal arrival time at at least one node in the logic circuit, a range in which a signal arrival time at the node can be taken, (c) extracting from the physical space information of the wiring inputted in the step (a) the wiring belonging to the node which is considered in (b) and the wiring adjacent to the node based on a predetermined condition, (d-1), (d-2), (d-3), and (d-4) using the range of the signal arrival time of the target node obtained by executing the step (b) A step (d) of calculating a delay time deterioration value of a target node in consideration of the influence of adjacent wirings, (d-1): a delay time deterioration value due to crosstalk with respect to a combination of the driving circuit of the driving circuit of the adjacent wiring extracted in the driving circuit of the target wiring and the step (c) As a data format which can be searched for by the relative visual difference of the video data, (d-2): calculating a range of a signal arrival time at a node to which the adjacent wiring extracted in the step (c) belongs, (d-3): The range of the signal arrival time of the adjacent node calculated in the step (d-2) is converted into a range of the relative signal arrival time with reference to the signal arrival time of the target node, A step of selecting a maximum value of the delay time deterioration value obtained in the step (d-1) among the range of reaching times and maintaining the maximum value as a searchable data format for each signal arrival time of the target node, (d-4): For the combination of the plurality of wirings adjacent to the target wiring, the delay time deterioration values held in the step (d-3) are added to each other for each signal arrival time of the target node, As a delay time degradation value for each signal arrival time, The delay time of the electronic circuit device. A logic circuit design system using an automatic designing apparatus having an arithmetic processing unit, a storage unit, and a man-machine interface, wherein a delay time is calculated using the delay time calculation method according to claim 5, And the delay time deterioration amount can be reduced by changing the signal arrival time by changing the configuration of the logic circuit, the arrangement of the circuit, and the position of the wiring. The design method of an electronic circuit device having a plurality of adjacent wirings adjacent to one target wiring, the method comprising the steps of: determining, based on a range of possible dynamic signal arrival times at nodes of the target wiring and nodes of the plurality of adjacent wirings The delay time deterioration of each of the adjacent wirings on the target wiring is obtained and the delay time deterioration of the adjacent wirings is summed on the basis of the signal arrival time of the target wiring, Calculating a cumulative delay time deterioration, calculating a total signal delay time at a node of the target wiring, and designing the electronic circuit device based on the calculation result. The designing method of an electronic circuit device having a plurality of adjacent wirings adjacent to a single target wiring, the method comprising the steps of: A graph image that shows the delay time deterioration characteristics of each of the wirings on the target wiring with reference to the signal arrival time on the target wiring and a graph in which the delay time degradation characteristics are summed based on the signal arrival time on the target wiring And analyzing delay time deterioration characteristics due to crosstalk caused by the plurality of adjacent wirings on the nodes of the target wiring by using a design tool in which an image is displayed on the screen. The electronic circuit library used for calculating the delay time deterioration value due to the crosstalk caused by the adjacent wiring on the target wiring is stored so as to be readable by a computer. The library is a logic cell for driving the target wiring and the adjacent wiring, The combination of the logic blocks and / or the combination of the load driving capability of the driving logic cell or the driving logic block is set such that, in the case of a plurality of adjacent parallel lengths of the adjacent interconnection and the characteristic interconnection in which the crosstalk occurs, And the delay time deterioration value can be obtained in accordance with the difference in signal arrival time at the node belonging to the adjacent wiring and the target wiring. The electronic circuit library used for calculating the delay time deterioration value due to the crosstalk caused by the adjacent wiring on the target wiring is stored so as to be readable by a computer. The library is a logic cell for driving the target wiring and the adjacent wiring, A delay time due to crosstalk according to the difference in signal arrival time at the nodes belonging to the target wiring and the adjacent wiring for a combination of the logic blocks and / or a combination of the load driving capability of these driving logic cells or the driving logic block When wiring is added to at least one of a side close to the drive logic cell or the drive logic block and a side farther from the drive logic cell or the drive logic block relative to the adjacent parallel portions of the respective lines of the target wiring and the adjacent wiring, It is possible to prevent the crosstalk caused by the crosstalk according to the difference in signal arrival time at the node belonging to the wiring and the adjacent wiring Recording medium of the electronic circuit, it characterized in that the library to be able to obtain a time value deterioration.