US7329944B2 - Leadframe for semiconductor device - Google Patents

Leadframe for semiconductor device Download PDF

Info

Publication number
US7329944B2
US7329944B2 US11/386,920 US38692006A US7329944B2 US 7329944 B2 US7329944 B2 US 7329944B2 US 38692006 A US38692006 A US 38692006A US 7329944 B2 US7329944 B2 US 7329944B2
Authority
US
United States
Prior art keywords
leadframe
layer
semiconductor device
alloy
layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US11/386,920
Other languages
English (en)
Other versions
US20060214272A1 (en
Inventor
Kazumitsu Seki
Harunobu Sato
Muneaki Kure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Assigned to SHINKO ELECTRIC INDUSTRIES CO., LTD. reassignment SHINKO ELECTRIC INDUSTRIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KURE, MUNEAKI, SATO, HARUNOBU, SEKI, KAZUMITSU
Publication of US20060214272A1 publication Critical patent/US20060214272A1/en
Application granted granted Critical
Publication of US7329944B2 publication Critical patent/US7329944B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49582—Metallic layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to a leadframe used for a semiconductor device and, more particularly, to a leadframe for a semiconductor device which shows improved adhesion with sealing resin as well as improved solder wettability.
  • a leadframe for a semiconductor device is used for mounting a semiconductor device, which is fabricated by sealing a semiconductor chip with resin material so as to be integrated with the leadframe, on a substrate or the like.
  • the leadframe has a stage section where a semiconductor chip is mounted; an inner lead section which is connected to the stage section and electrically connected to electrodes of the semiconductor chip through wire bonding; and an outer lead section, or the like, which is connected to the inner lead section and acts as an external connection terminal when the semiconductor device is mounted on the substrate, or the like.
  • Such a leadframe is required for adhesion with a resin material used for sealing the chip. Also required is a superior bondability of an outer lead which is used for bonding the leadframe to a substrate so that a semiconductor device is mounted thereon by means of soldering or the like.
  • FIG. 6 is a plan view showing an example leadframe for a semiconductor device.
  • Reference numeral 22 designates a dam bar.
  • the semiconductor chip (not shown) is mounted on the stage section 16 of the leadframe 10 .
  • This semiconductor chip and the inner leads 14 are bonded by means of wires.
  • the semiconductor chip, the wires, and the inner leads 14 are sealed with resin, to thus complete a semiconductor device.
  • soldering is usually utilized.
  • a leadframe, where a coating film has been formed over the outer leads 12 in advance also called “exterior solder coating film”
  • a leadframe enabling mounting a semiconductor device on a substrate without involvement of an exterior solder coating film had been known, which is comprised of a substrate for use with a leadframe, generally being called as a Pd-PPF (Palladium Pre-Plated Leadframe), a nickel (Ni) plating layer of a ground layer, an intermediate layer of a palladium (Pd) or Pd alloy coating film, and a surface layer of gold (Au) plating film or silver (Ag) coating film, those being sequentially formed on the substrate as disclosed in JP-A Hei 4-115558.
  • Pd-PPF Palladium Pre-Plated Leadframe
  • Ni nickel
  • Au gold
  • silver silver
  • a leadframe which is disclosed in JP-A Hei 4-337657 as another related-art example of a leadframe for a semiconductor device having a leadframe substrate being coated with exterior plating of material other than solder, is comprised of: an Ni-based plating layer provided on a base material of the leadframe; a Pd or Pd alloy plating layer provided on at least inner lead sections and outer lead sections on the base material; and an Au plating layer provided on the Pd or Pd alloy plating layer. Further, JP-A Hei 11-111909 also discloses a leadframe coated with substantially similar plating.
  • JP-A 2001-110971 discloses a leadframe having a Ni-based protective coating layer provided on a base material of the leadframe, an intermediate layer of Pd or Pd alloy plating, and an outermost layer formed by plating the intermediate layer with Pd and Au one after another.
  • soldering material used for mounting a semiconductor device on a substrate, or the like, in view of environmental protection.
  • a related-art leadframe (a so-called Au/Pd/Ni leadframe) is formed by sequentially forming, on a base material for a leadframe, an Ni plating layer, a Pd or Pd alloy plating layer, and an Au plating layer.
  • a semiconductor chip is mounted on the leadframe and sealed with a resin material, to thus produce a semiconductor device.
  • the fusing point of the employed lead-free solder is higher than that of the related-art tin-lead solder. For this reason, a reflow temperature must be increased.
  • the fusing point of Sn—Ag—Cu solder which has recently come to be used, is 217° C., and a temperature of about 240° to 250° is used for reflowing of the solder.
  • sealing resin When the reflow temperature has increased, sealing resin is easily exfoliated from the leadframe because of a difference in coefficient of thermal expansion between a metallic material of the leadframe base material and the sealing resin. Because of contribution of hygroscopicity of epoxy-based resin, which is commonly used as sealing resin, moisture easily intrudes into cracks caused by exfoliation. The moisture is vaporized in subsequent thermal treatment, or the like, which in turn becomes a cause of serious defects, such as cracks in the sealing resin, fractures of the semiconductor chip, or the like.
  • a leadframe for a semiconductor device of the present invention is a leadframe for a semiconductor device having a stage section where a semiconductor chip is to be mounted, an inner lead section connected to the stage section, and an outer lead section connected to the inner lead section, the leadframe including: (1) a nickel (Ni) layer; (2) a palladium (Pd) or palladium alloy layer; (3) a tin (Sn) or tin alloy layer or a zinc (Zn) or zinc alloy layer; and (4) a gold (Au) layer, all of which are formed on a base material forming the leadframe, in sequence from the surface of the leadframe.
  • the thickness of (2) the Pd or Pd alloy layer ranges from 0.005 to 0.05 ⁇ m; the thickness of (3) the Sn or Sn alloy layer or the Zn or Zn alloy layer ranges from 0.001 to 0.05 ⁇ m; and the thickness of (4) the Au layer ranges from 0.001 to 0.1 ⁇ m.
  • a combination of (3) the Sn or Sn alloy layer or the Zn or Zn alloy layer and (4) the Au layer, being formed over (2) the Pd or Pd alloy layer, might be also repeated twice or more time.
  • the preferred thickness of the layer ( 3 ) and the preferred thickness of the layer ( 4 ) correspond to the thickness of the layer ( 3 ) and that of the layer ( 4 ).
  • the total thickness of the layers ( 3 ) preferably falls within a range of 0.001 to 0.05 ⁇ m
  • the total thickness of the layers ( 4 ) preferably falls within a range of 0.001 to 0.1 ⁇ m.
  • the layers ( 1 ) to ( 4 ) may be formed over the entire surface of the base material forming the leadframe, or the layers ( 1 ) to ( 4 ) may be formed over a portion of the base material forming the leadframe. In the latter case, the layers ( 1 ) to ( 4 ) are formed in at least the outer lead section.
  • the present invention can provide a leadframe for a semiconductor device which shows improved adhesion to sealing resin, without impairing solder wettability and spreadability required to mount a semiconductor device on a substrate or the like.
  • FIGS. 1A and 1B shows a cross-sectional view for describing the layered structure of a leadframe for a semiconductor device of the present invention
  • FIG. 2 is a graph showing results of a test for adhesion between a leadframe and a sealing resin
  • FIG. 3 is a perspective view for describing a sample used for the adhesion test
  • FIG. 4 is a graph showing a result of solder wettability and spreadability test
  • FIG. 5 is a perspective view for describing a sample used in the solder wettability and spreadability test.
  • FIG. 6 is a plan view of a related-art leadframe.
  • an Ni layer 1 , a Pd or Pd alloy layer 2 , an Sn or Sn alloy layer (or a Zn or Zn alloy layer) 3 , and an Au layer 4 are formed on a base material B, in this sequence from the surface thereof, of the leadframe.
  • the layered structure corresponds to a structure embodied by interposing an amphoteric metal layer, such as Sn, Sn alloy layer, Zn, or Zn alloy layer between a top layer of Au and the intermediate Pd layer of a related-art Pd-PPF (a so-called Au/Pd/Ni leadframe)
  • an amphoteric metal layer such as Sn, Sn alloy layer, Zn, or Zn alloy layer between a top layer of Au and the intermediate Pd layer of a related-art Pd-PPF (a so-called Au/Pd/Ni leadframe)
  • the base material B, the Ni layer 1 , the Pd or Pd alloy layer 2 , and the Au layer 4 which are included in the leadframe of the present invention, are basically analogous with those used in the related-art Pd-PPF.
  • the base material B can be formed from a material used for an ordinary leadframe; e.g., Cu or a Cu alloy, an Fe—Ni alloy, or the like.
  • the Ni layer 1 located on the base material B can be formed to a thickness of 0.05 to 3 ⁇ m. At a thickness of less than 0.05 ⁇ m, solder wettability, which is required during mounting, is difficult to ensure, for reasons of diffusion of Cu. When the thickness exceeds 3 ⁇ m, cracks arise in plating during forming of outer leads, whereupon the base material becomes exposed.
  • the Pd or Pd alloy layer 2 on the Ni layer 1 can be formed to the range of thickness of 0.005 to 0.05 ⁇ m. At a thickness of less than 0.005 ⁇ m, solder wettability, which is required for mounting, is difficult to ensure, for reasons of diffusion of Ni. When the thickness exceeds 0.05 ⁇ m, Pd cannot be completely fused and diffused into solder during mounting operation, whereby wettability and spreadability are deteriorated.
  • the Au layer 4 of the outermost layer can be formed to a thickness of 0.001 to 0.1 ⁇ m.
  • the thickness is less than 0.001 ⁇ m, solder wettability, which is required during mounting, is difficult to ensure, because of diffusion of Sn and Zn.
  • the thickness exceeds 0.1 ⁇ m, Au forms an alloy layer with Sn during mounting operation, which in turn deteriorates adhesion strength.
  • the layer 3 interposed between the Pd or Pd alloy layer 2 and the Au layer 4 is formed from Sn or an Sn alloy or Zn or a Zn alloy.
  • Sn alloy signifies an alloy formed from Sn and another type of metal
  • Zn alloy signifies an alloy formed from Zn and another type of metal.
  • an alloy formed from Sn and Zn (a Sn—Zn alloy) is included in both categories, and the Sn—Zn alloy is a preferable as an Sn alloy or a Zn alloy used in the present invention.
  • the thickness of the Sn or Sn alloy (or Zn or Zn alloy) layer 3 preferably ranges from 0.001 to 0.05 ⁇ m.
  • a thickness of less than 0.001 ⁇ m is insufficient for preventing a drop in adhesion, which would be caused by a difference in coefficient of thermal expansion between the leadframe and sealing resin.
  • the thickness exceeds 0.05 ⁇ m an effect of enhancing defect prevention is saturated.
  • the thickness of Sn or Sn alloy layer (or Zn or Zn alloy layer) 3 falls within a range of 0.005 to 0.05 ⁇ m.
  • the layers 1 to 4 can be formed by means of an arbitrary method for forming a thin film. For instance, a widely-known method, such as electroplating, electroless deposition, sputtering, or the like, can be utilized. Generally, electroplating is preferable.
  • a Ni substrate layer of 0.5 ⁇ m in thickness is situated on a Cu alloy or Fe—Ni alloy base material, and an intermediate Pd layer having a thickness of 0.015 ⁇ m is provided on the Ni substrate layer.
  • An Sn layer having a thickness of 0.01 ⁇ m is provided on the intermediate Pd layer, and an Au layer, which is the top layer and has a thickness of 0.007 ⁇ m, is provided on the Sn layer.
  • a combination of the Sn or an Sn alloy (or Zn or a Zn alloy) layer 3 with the Au layer 4 provided thereon may be single or plural. Put another way, a plurality of Sn or Sn alloy (or Zn or Zn alloy) layers and Au layers can be formed on the Pd or Pd alloy layer 2 one after another.
  • FIG. 1B shows an example of leadframe having a plurality of Sn or Sn alloy (or Zn or Zn alloy) layers and Au layers.
  • the Sn or Sn alloy (or Zn or Zn alloy) layers 3 a , 3 b and the Au layers 4 a , 4 b which are formed alternately, are situated on the Pd or Pd alloy layer 2 .
  • a total thickness of the Sn or Sn alloy (or the Zn or Zn alloy) layer preferably falls within a range of 0.001 to 0.05 ⁇ m.
  • the layers provided on the base material B may be formed over the entire surface of the base material B or on portions of the same. In the latter case, the layers are formed in at least the outer lead section or the stage section.
  • FIG. 2 shows results of a test of adhesion between a leadframe and sealing resin.
  • the adhesion test was conducted through use of a test leadframe sample prepared by sequentially forming, on a Cu base material, an Ni layer of 1 ⁇ m in thickness, Pd and Sn layers of 0.01 ⁇ m in thickness, and an Au layer of 0.007 ⁇ m by means of plating. The thickness of the Sn layer was changed within the range of 0.005 to 0.1 ⁇ m.
  • CEL 9200 manufactured by Hitachi Chemical Co., Ltd.
  • the test leadframe was subjected to heat treatment for one hour at 175° C.
  • a truncated cone (a bottom surface having a diameter of 3.568 mm, an upper surface having a diameter of 3 mm, and a height of 3 mm) was formed from sealing resin 32 on a test leadframe 31 having undergone pre-treatment.
  • Shearing force parallel to the surface of the leadframe was exerted on the truncated cone as indicated by arrow F, and shearing strength achieved when the leadframe 31 was exfoliated from the resin 32 was measured. Measurement was performed on a per-sample basis, after the truncated cone had been formed from resin and after the truncated cone had been heated for ten seconds at 300° C. subsequent to molding (simulating solder reflow conditions employed during mounting of a semiconductor device).
  • FIG. 4 shows results of the test for solder wettability and spreadability on the leadframe.
  • the test for solder wettability and spreadability was carried out through use of the test leadframe sample which is the same as that employed for the previously-described adhesion test. Holes of a metal mask laid on the test leadframe were filled with paste, and the metal mask was removed.
  • solder paste 52 was formed and applied on a test leadframe 51 in the form of a pad having a diameter of 1.57 mm and a height of 0.15 mm.
  • the employed solder paste was Sn—Ag—Cu-based solder paste M705-221CM5-42-11 manufactured by Senju Metal Industry Co., Ltd.
  • solder paste was heated for one minute at 230° C. to thus reflow.
  • the diameter of the reflow in an arbitrary direction was measured. An average of five sets of data was determined.
  • Solder wettability and spreadability was computed as a ratio of a diameter achieved before reflow to a mean radius achieved after reflow. Similar tests were conducted through use of the test leadframe sample heated for 30 seconds at 400° C. before application of paste. In the sample, where the Sn layer sandwiched between the Pd layer and the Au layer has a thickness of 0.1 ⁇ m, the diameter was reduced when the leadframe was coated with a paste after having been heated at 400° C., and deterioration of solder wettability and spreadability was exhibited.
  • the desirable thickness of the Sn layer is found to preferably range from 0.001 to 0.05 ⁇ m.
  • the reason why the adhesion to the sealing resin is enhanced while the superior solder wettability and spreadability are ensured by the present invention is considered to be as follows.
  • the Sn layer is situated below the surface Au layer, portions of Au of the Au layer diffuse to the Sn layer, and portions of Sn of the Sn layer diffuse to the Au layer, because of solid-phase diffusion, by means of heating which is achieved at the solder reflow temperature during mounting. Consequently, Sn as well as Au are also present on the surface of the Au layer that is the top layer. Au on the surface, solder wettability and spreadability are ensured. Meanwhile, Sn appearing on the surface is oxidized in moderation, which contributes to enhancement of adhesion to the sealing resin.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Die Bonding (AREA)
US11/386,920 2005-03-25 2006-03-22 Leadframe for semiconductor device Active US7329944B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005088191A JP2006269903A (ja) 2005-03-25 2005-03-25 半導体装置用リードフレーム
JP2005-088191 2005-03-25

Publications (2)

Publication Number Publication Date
US20060214272A1 US20060214272A1 (en) 2006-09-28
US7329944B2 true US7329944B2 (en) 2008-02-12

Family

ID=37015725

Family Applications (1)

Application Number Title Priority Date Filing Date
US11/386,920 Active US7329944B2 (en) 2005-03-25 2006-03-22 Leadframe for semiconductor device

Country Status (5)

Country Link
US (1) US7329944B2 (ko)
JP (1) JP2006269903A (ko)
KR (1) KR101224935B1 (ko)
CN (1) CN100508174C (ko)
MY (1) MY138096A (ko)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070090501A1 (en) * 2005-10-20 2007-04-26 Seishi Oida Lead frame
US8796049B2 (en) * 2012-07-30 2014-08-05 International Business Machines Corporation Underfill adhesion measurements at a microscopic scale
US11239594B2 (en) * 2019-08-05 2022-02-01 Autonetworks Technologies, Ltd. Electrical contact material, terminal fitting, connector, and wire harness

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7727816B2 (en) * 2006-07-21 2010-06-01 Stats Chippac Ltd. Integrated circuit package system with offset stacked die
US7618848B2 (en) * 2006-08-09 2009-11-17 Stats Chippac Ltd. Integrated circuit package system with supported stacked die
CN102817055B (zh) * 2012-08-15 2015-03-25 中山品高电子材料有限公司 引线框超薄镀钯镀金工艺
KR102009937B1 (ko) 2013-12-09 2019-08-12 주식회사 엘지생활건강 마이크로니들용 조성물
DE102015102759A1 (de) * 2015-02-26 2016-09-01 Heraeus Deutschland GmbH & Co. KG Leistungselektronik-Modul und Verfahren zur Herstellung eines Leistungselektronik-Moduls
DE102017108422A1 (de) * 2017-04-20 2018-10-25 Osram Opto Semiconductors Gmbh Verfahren zum Befestigen eines Halbleiterchips auf einem Leiterrahmen und elektronisches Bauelement
CN111199940B (zh) * 2018-11-16 2022-03-25 泰州友润电子科技股份有限公司 一种用于引线框架的涂覆料涂覆方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04115558A (ja) 1990-09-05 1992-04-16 Shinko Electric Ind Co Ltd 半導体装置用リードフレーム
JPH04337657A (ja) 1991-05-14 1992-11-25 Hitachi Cable Ltd 半導体装置用リードフレーム
US5384204A (en) * 1990-07-27 1995-01-24 Shinko Electric Industries Co. Ltd. Tape automated bonding in semiconductor technique
JPH11111909A (ja) 1997-10-07 1999-04-23 Seiichi Serizawa 半導体装置用リードフレーム
US6150711A (en) * 1997-02-20 2000-11-21 Samsung Aerospace Industries, Ltd Multi-layer plated lead frame
JP2001110971A (ja) 1999-10-01 2001-04-20 Samsung Aerospace Ind Ltd 半導体パッケージ用リードフレーム及びその製造方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57103342A (en) * 1981-11-02 1982-06-26 Nec Corp Semiconductor device
JPS6341057A (ja) * 1986-08-07 1988-02-22 Furukawa Electric Co Ltd:The Ａｇ被覆電子部品用リ−ド材
JPH1074879A (ja) * 1996-08-30 1998-03-17 Mitsui High Tec Inc 半導体装置用リードフレーム
JP2000133763A (ja) * 1998-10-26 2000-05-12 Dainippon Printing Co Ltd 樹脂封止型半導体装置用の回路部材およびその製造方法
JP2000277679A (ja) * 1999-03-25 2000-10-06 Denso Corp 半導体装置

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5384204A (en) * 1990-07-27 1995-01-24 Shinko Electric Industries Co. Ltd. Tape automated bonding in semiconductor technique
JPH04115558A (ja) 1990-09-05 1992-04-16 Shinko Electric Ind Co Ltd 半導体装置用リードフレーム
JPH04337657A (ja) 1991-05-14 1992-11-25 Hitachi Cable Ltd 半導体装置用リードフレーム
US6150711A (en) * 1997-02-20 2000-11-21 Samsung Aerospace Industries, Ltd Multi-layer plated lead frame
JPH11111909A (ja) 1997-10-07 1999-04-23 Seiichi Serizawa 半導体装置用リードフレーム
JP2001110971A (ja) 1999-10-01 2001-04-20 Samsung Aerospace Ind Ltd 半導体パッケージ用リードフレーム及びその製造方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070090501A1 (en) * 2005-10-20 2007-04-26 Seishi Oida Lead frame
US8283759B2 (en) * 2005-10-20 2012-10-09 Panasonic Corporation Lead frame having outer leads coated with a four layer plating
US8796049B2 (en) * 2012-07-30 2014-08-05 International Business Machines Corporation Underfill adhesion measurements at a microscopic scale
US11239594B2 (en) * 2019-08-05 2022-02-01 Autonetworks Technologies, Ltd. Electrical contact material, terminal fitting, connector, and wire harness

Also Published As

Publication number Publication date
KR20060103173A (ko) 2006-09-28
CN100508174C (zh) 2009-07-01
KR101224935B1 (ko) 2013-01-22
JP2006269903A (ja) 2006-10-05
MY138096A (en) 2009-04-30
US20060214272A1 (en) 2006-09-28
CN1838407A (zh) 2006-09-27

Similar Documents

Publication Publication Date Title
US7329944B2 (en) Leadframe for semiconductor device
JP2746840B2 (ja) 集積回路パッケージとリードフレーム
TWI533426B (zh) 導線架及半導體裝置
JP3998703B2 (ja) 半導体装置用リードフレーム
KR100318818B1 (ko) 리드프레임에대한보호피막결합
JP2006520103A (ja) 被覆ワイヤーで形成された、フリップチップ用被覆金属のスタッドバンプ
US6519845B1 (en) Wire bonding to dual metal covered pad surfaces
US6080494A (en) Method to manufacture ball grid arrays with excellent solder ball adhesion for semiconductor packaging and the array
TWI381505B (zh) 導線架與利用此導線架製造半導體封裝的方法
US8786084B2 (en) Semiconductor package and method of forming
US8071472B2 (en) Semiconductor device with solder balls having high reliability
US5958607A (en) Lead frame for semiconductor device
JPH10294337A (ja) 半導体装置及びその製造方法
US20020113322A1 (en) Semiconductor device and method to produce the same
JP2001060760A (ja) 回路電極およびその形成方法
US6232651B1 (en) Lead frame for semiconductor device
KR20100050640A (ko) 반도체 패키지 제조용 리드프레임 및 이의 도금 방법
JPS61140160A (ja) 半導体用リ−ドフレ−ム
TWI436465B (zh) 銲線接合結構、銲線接合方法及半導體封裝構造的製造方法
KR101167650B1 (ko) 반도체 장치용 리드 프레임
JPH06260577A (ja) 配線電極の被膜構造
JP2006352175A (ja) 半導体集積回路装置
JPS60119765A (ja) 樹脂封止型半導体装置およびそれに用いるリ−ドフレ−ム

Legal Events

Date Code Title Description
AS Assignment

Owner name: SHINKO ELECTRIC INDUSTRIES CO., LTD., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SEKI, KAZUMITSU;SATO, HARUNOBU;KURE, MUNEAKI;REEL/FRAME:017404/0463

Effective date: 20060228

FEPP Fee payment procedure

Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

Year of fee payment: 12