US7307469B2 - Step-down power supply - Google Patents

Step-down power supply Download PDF

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US7307469B2
US7307469B2 US11/176,285 US17628505A US7307469B2 US 7307469 B2 US7307469 B2 US 7307469B2 US 17628505 A US17628505 A US 17628505A US 7307469 B2 US7307469 B2 US 7307469B2
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power supply
voltage
node
supply voltage
load
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US20060017496A1 (en
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Hitoshi Yamada
Mineo Noguchi
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Lapis Semiconductor Co Ltd
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Oki Electric Industry Co Ltd
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/462—Regulating voltage or current wherein the variable actually regulated by the final control device is dc as a function of the requirements of the load, e.g. delay, temperature, specific voltage/current characteristic
    • G05F1/465—Internal voltage generators for integrated circuits, e.g. step down generators
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B3/00—Sharpening cutting edges, e.g. of tools; Accessories therefor, e.g. for holding the tools
    • B24B3/36—Sharpening cutting edges, e.g. of tools; Accessories therefor, e.g. for holding the tools of cutting blades
    • B24B3/54—Sharpening cutting edges, e.g. of tools; Accessories therefor, e.g. for holding the tools of cutting blades of hand or table knives
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24D—TOOLS FOR GRINDING, BUFFING OR SHARPENING
    • B24D7/00—Bonded abrasive wheels, or wheels with inserted abrasive blocks, designed for acting otherwise than only by their periphery, e.g. by the front face; Bushings or mountings therefor
    • B24D7/18—Wheels of special form

Definitions

  • the present invention relates to a step-down power supply that lowers the voltage of externally supplied power to provide a load with power at a voltage equal to a reference voltage.
  • FIG. 13 shows a simple step-down power supply 400 that can be integrated into, for example, a semiconductor memory chip.
  • the output of a differential amplifier or comparator 401 is coupled through a control node G 0 to the gate of a p-channel metal-oxide-semiconductor (PMOS) transistor 402 .
  • PMOS metal-oxide-semiconductor
  • Power supplied from an external source at a voltage VCC is fed through the PMOS transistor 402 to drive internal load circuits 405 such as the sense amplifiers that amplify voltages from memory cells.
  • the differential amplifier 401 compares the internal power supply voltage VDD with a reference voltage (Vref) and adjusts the conductivity (current-driving capability) of the PMOS transistor 402 so as to hold VDD at the reference voltage level.
  • Vref reference voltage
  • the differential amplifier 401 detects the fall and increases the conductivity of the PMOS transistor 402 , thereby restoring VDD to the reference level. This feedback control takes place, however, with a certain delay. If the current draw increases abruptly, as illustrated in FIG. 14 , VDD falls too rapidly for the differential amplifier 401 to keep up, and an unavoidable voltage droop occurs. The size of the droop can be reduced by enlarging the differential amplifier 401 and PMOS transistor 402 to increase their current-driving capability, but the attendant increase in chip size and current consumption by the step-down power supply 400 is undesirable.
  • Japanese Patent Application Publication No. H11-214617 suggests the modification shown in FIG. 15 , in which a pull-down circuit 403 is added to pull the control node G 0 down to the ground level (VSS) when the sense amplifiers in a memory circuit are turned on.
  • the pull-down circuit 403 receives a sense amplifier activation signal (SA_ON).
  • SA_ON goes high
  • an internal pull-down signal in the pull-down circuit 403 goes high for a predetermined interval, turning on a transistor (not shown) that connects node G 0 to ground (VSS).
  • the conductivity of the PMOS transistor 402 then increases rapidly and the VDD voltage droop is much reduced, as illustrated in FIG. 16 .
  • FIG. 17 shows another conventional step-down power supply.
  • This step-down power supply 1 receives power from an external source at a voltage VCC, such as 3.3 V, for example, lowers the external power supply voltage to generate an internal power supply voltage VDD equal to a reference voltage Vref, such as 2.5 V, for example, and provides the internal power supply voltage to a load circuit 2 .
  • the step-down power supply 1 comprises a reference voltage generator 10 , a control circuit 30 , and a stepped-down voltage output circuit 40 .
  • the reference voltage generator 10 generates the reference voltage Vref.
  • the control circuit 30 switches a step-down control signal S 30 between a high level and a low level according to the amount of current drawn by the load circuit 2 .
  • the stepped-down voltage output circuit 40 receives the reference voltage Vref and the step-down control signal S 30 and outputs the internal power supply voltage VDD.
  • the stepped-down voltage output circuit 40 comprises PMOS transistors 41 , 42 , 47 , n-channel metal-oxide-semiconductor (NMOS) transistors 43 , 44 , 45 , and a constant-current source 46 .
  • PMOS transistor 41 has its source connected to the VCC power source, its drain connected to a node N 42 , and its gate connected to a node N 41 .
  • PMOS transistor 42 has its source connected to the VCC power source and its drain and gate connected to node N 41 .
  • NMOS transistor 43 has its source connected to a node N 43 , its drain connected to node N 42 , and its gate connected to a node N 45 .
  • NMOS transistor 44 has its source connected to node N 43 , its drain connected to node N 41 , and its gate connected to a node N 44 .
  • NMOS transistor 45 has its source connected to ground (VSS), its drain connected to node N 43 , and its gate connected to a node N 46 .
  • PMOS transistor 47 has its source connected to the VCC power source, its drain connected to node N 44 , and its gate connected to node N 42 .
  • the constant-current source 46 is connected between node N 43 and ground.
  • Node N 45 receives the reference voltage Vref.
  • Node N 46 receives the step-down control signal S 30 .
  • Node N 44 outputs the internal power supply voltage VDD.
  • PMOS transistors 41 and 42 form a current mirror structure with identical source potentials and identical gate-source voltages.
  • the source-drain currents I 41 and I 42 of PMOS transistors 41 and 42 are identical, and the potentials at nodes N 41 and N 42 are both equal to VCC ⁇ Vtp, where Vtp is the source-drain voltage of PMOS transistors 41 and 42 .
  • the response speed of this feedback control loop depends on the rate at which the gate capacitances of the transistors, especially PMOS transistor 47 , can be charged and discharged. This depends on the magnitude of currents I 41 , I 42 , I 43 , and I 44 ; that is, the response speed of the stepped-down voltage output circuit 40 depends on its current consumption.
  • the step-down control signal S 30 is driven low, turning off NMOS transistor 45 and reducing the current consumption of the stepped-down voltage output circuit 40 .
  • the step-down control signal S 30 is driven high, turning on NMOS transistor 45 to increase the current flow through the stepped-down voltage output circuit 40 and provide a faster feedback response.
  • I 47 IVDD
  • the steady-state potential at node N 42 is VCC ⁇ Vtp 1 , where Vtp 1 is comparatively small.
  • the relatively slow response in this state is illustrated in FIG. 18 : if the reference voltage Vref rises from its normal level V 40 to a higher level V 41 while the step-down control signal S 30 is low, the internal power supply voltage VDD rises comparatively slowly from V 40 to the new level V 41 . During this rise, the potential at node N 42 temporarily drops.
  • the step-down control signal S 30 is high, NMOS transistor 45 is turned on, the sum (I 43 +I 44 ) of currents I 43 and I 44 increases from I 46 to I 45 +I 46 , and the sum (I 41 +I 42 ) of currents I 41 and I 42 also increases from I 46 to I 45 +I 46 .
  • the potential at node N 42 in this state is now VCC ⁇ Vtp 2 , where Vtp 2 is comparatively large. If the reference voltage Vref rises from its normal level V 40 to a higher level V 41 in this state, the internal power supply voltage VDD rises comparatively quickly from V 40 to the new level V 41 , as shown at the bottom of FIG. 18 , but the potential at node N 42 still drops temporarily, and the drop is greater than the corresponding drop in the standby-state when S 30 is low.
  • FIG. 18 shows that the stepped-down voltage output circuit 40 responds faster to a change in the reference voltage Vref when the step-down control signal S 30 is high than when S 30 is low. Similarly, the response to a change in the current IVDD drawn by the load circuit 2 is faster when the S 30 is high than when S 30 is low.
  • the voltage changes in FIG. 18 can be explained as follows.
  • the gate-source voltage of NMOS transistor 43 becomes higher than the gate-source voltage of NMOS transistor 44
  • the drain-source current I 43 of NMOS transistor 43 becomes greater than the drain-source current I 44 of NMOS transistor 44 (I 43 >I 44 ).
  • the voltage at node N 42 falls below VCC ⁇ Vtp 1 . This increases the gate-source voltage and therefore the conductivity of PMOS transistor 47 , thereby increasing the internal power supply voltage VDD.
  • a problem with the conventional step-down power supply in FIG. 15 is that if the response of the feedback control system including the differential amplifier is slow, after being pulled down, the control node G 0 cannot return quickly to its normal potential level, and may remain at a comparatively low level even after the current drawn by the internal load circuits 405 has fallen back to the original level. As a result, the conductivity of PMOS transistor 402 is too high, and the internal power supply voltage VDD increases, as shown in FIG. 19 . This problem is observed when the rapid rise in current draw that occurs when the internal load circuit is activated is immediately followed by a decline in the current draw.
  • the conventional step-down power supply in FIG. 17 is apt to malfunction when the level of the step-down control signal changes.
  • the cause of the malfunction will be described with reference to FIG. 20 , which shows voltage, current, and timing waveforms illustrating the operation of the stepped-down voltage output circuit 40 .
  • the load circuit 2 draws current IVDD equal to I 1 in the standby state and I 2 in the active state.
  • IVDD abruptly increases from I 1 to I 2 , causing the step-down control signal S 30 to go high.
  • the current flowing between node N 43 and ground (VSS) abruptly increases from I 46 to I 46 +I 45 and the voltage at node N 43 abruptly decreases from a value Vtn to a lower value Vtn ⁇ , where a depends on the characteristics of the PMOS and NMOS transistors used.
  • the voltage drop at node N 43 is coupled through the gate-source capacitance of NMOS transistor 43 to node N 45 , causing the reference voltage Vref to decrease temporarily from V 40 to a lower value V 40 ⁇ V 1 .
  • the voltage at node N 42 likewise decreases temporarily to a value lower than both VCC ⁇ Vtp 3 (the normal value in the standby state) and VCC ⁇ Vtp 4 (the normal value in the active state).
  • the internal power supply voltage VDD also drops temporarily, mimicking the change in the reference voltage Vref. After a certain delay, the reference voltage generator 10 restores the reference voltage Vref to V 40 and the internal supply voltage VDD also returns to V 40 .
  • the step-down control signal S 30 goes low, the current flowing between node N 43 and ground to decreases from I 46 +I 45 to I 46 , and the voltage at node N 43 increases from Vtn ⁇ to Vtn.
  • the voltage rise at node N 43 is coupled through the gate-source capacitance of NMOS transistor 43 to node N 45 , causing the reference voltage Vref to rise temporarily to V 40 + ⁇ V 2 .
  • the internal power supply voltage VDD likewise rises to V 40 + ⁇ V 2 , while node N 42 rises to a level higher than both VCC ⁇ Vtp 3 and VCC ⁇ Vtp 4 .
  • the reference voltage generator 10 restores the reference voltage Vref to V 40 , node N 42 returns to VCC ⁇ Vtp 3 , and the internal power supply voltage VDD returns to V 40 .
  • a first object of the present invention is to provide a step-down power supply that includes a pull-down circuit to handle sharp increases in the current drawn by internal load circuits, but does not allow the internal power supply voltage VDD to increase after the pull-down circuit has operated.
  • a second object of the invention is to enable a step-down power supply to operate with reduced current consumption when its load circuit is in the standby state, without having the internal power supply voltage temporarily increase or decrease at transitions between the active and standby states.
  • the invention provides several step-down power supplies meeting these objects. All of these step-down power supplies lower an external power supply voltage with respect to a ground voltage to generate an internal power supply voltage equal to a reference voltage, and supply the internal power supply voltage to an internal load circuit.
  • One step-down power supply meeting the first object receives a load activation signal indicating activation of the internal load circuit.
  • a differential amplifier compares the internal power supply voltage with the reference voltage and adjusts the voltage at a control node if the internal power supply voltage differs from the reference voltage.
  • a driver having a control terminal connected to the control node receives the external power supply voltage and outputs the internal power supply voltage responsive to the voltage at the control node.
  • a pull-down circuit supplies the ground voltage to the control node for a first predetermined time in response to the load activation signal.
  • a pull-up circuit supplies the external power supply voltage to the control node for a second predetermined time following the first predetermined time.
  • this step-down power supply prevents the internal power supply voltage from rising or falling significantly when the internal load circuit is activated.
  • Another step-down power supply meeting the first object receives a chip activation signal indicating activation of a semiconductor chip including the internal load circuit.
  • the power supply has a differential amplifier and a driver, which operate as described above.
  • a leak circuit supplies the ground voltage to the control node for a predetermined time in response to the chip activation signal, thereby causing current to leak from the control node to ground.
  • the leaking of current to ground for the predetermined time causes the differential amplifier to bring down the voltage at the control node before the internal load circuit is activated.
  • the control node voltage only has to fall a little farther to enable the driver to start supplying the necessary current at the correct internal power supply voltage.
  • the internal power supply voltage therefore quickly reaches the correct level and is then held there by feedback through the differential amplifier, without falling significantly below or rising significantly above the correct level.
  • a step-down power supply meeting the second object of the invention includes a reference voltage generator for generating a reference voltage, a stepped-down voltage output circuit that generates the internal power supply voltage, holds the internal power supply voltage at the reference voltage level, and provides the internal power supply voltage to the internal load circuit, and a control circuit that generates a step-down control signal.
  • the step-down control signal is switched between a first voltage level and a second voltage level according to the amount of current drawn by the internal load circuit.
  • the stepped-down voltage output circuit includes first, second, and third elements, each having an input terminal, an output terminal, and a control terminal.
  • the first element conducts current from its input terminal to its output terminal with conductivity controlled by the reference voltage, which is received at its control terminal.
  • the second element conducts current from its input terminal, which is connected to the output terminal of the first element, to ground responsive to the step-down control signal, which it receives at its control terminal.
  • the third element receives the external power supply voltage at its input terminal and supplies current to the internal load circuit from its output terminal, operating with a conductivity controlled by the voltage at its control terminal, which is connected to the input terminal of the first element.
  • the stepped-down voltage output circuit also has a capacitor connected between the control terminals of -the first and second elements.
  • the step-down control signal rises or falls, the voltage at the output terminal of the first element falls or rises in the opposite direction.
  • This voltage change is capacitively coupled through the first element, from its output terminal to its control terminal, and could perturb the reference voltage, but the effect is canceled by the coupling of the opposite change in the step-down control signal through the capacitor connected to the control terminals of the first and second elements.
  • the reference voltage therefore remains substantially constant. Consequently, the internal power supply voltage remains substantially constant.
  • Another step-down power supply meeting the second object of the invention includes a reference voltage generator, a control circuit, and a stepped-down voltage output circuit with first, second, and third elements that conduct current as described above.
  • the stepped-down voltage output circuit also has a circuit that applies the ground voltage to the control terminal of the third element for a first predetermined time when the step-down control signal is switched from the first level to the second level, and applies the external power supply voltage to the control terminal of the third element for a second predetermined time when the step-down control signal is switched from the second voltage level to the first voltage level.
  • the changes in level of the step-down control signal temporarily perturb the reference voltage by the capacitive coupling through the first element noted above, during these temporary fluctuations of the reference voltage, the control terminal of the third element is brought to an appropriate fixed level, so the internal power supply voltage does not fluctuate significantly.
  • Yet another step-down power supply meeting the second object of the invention also includes a reference voltage generator, a control circuit, and a stepped-down voltage output circuit with first, second, and third elements that conduct current as described above.
  • the stepped-down voltage output circuit also has a circuit that raises the reference voltage by a first predetermined amount for a first predetermined time when the step-down control signal is switched from the first level to the second level, and lowers the reference voltage by a second predetermined amount for a second predetermined time when the control signal is switched from the second level to the first level.
  • FIG. 1 is a circuit diagram of a step-down power supply illustrating a first embodiment of the invention
  • FIG. 2A shows the internal circuit configuration of the pull-down circuit in FIG. 1 ;
  • FIG. 2B shows the internal circuit configuration of the pull-up circuit in FIG. 1 ;
  • FIG. 3 is a voltage, current, and timing waveform diagram illustrating the operation of the first embodiment
  • FIG. 4 is a circuit diagram of a step-down power supply illustrating a second embodiment of the invention.
  • FIG. 5 shows the internal circuit configuration of the one-shot circuit in FIG. 4 ;
  • FIG. 6 is a voltage, current, and timing waveform diagram illustrating the operation of the second embodiment
  • FIG. 7 is a circuit diagram of a step-down power supply illustrating a third embodiment of the invention.
  • FIG. 8 is a voltage, current, and timing waveform diagram illustrating the operation of the stepped-down voltage output circuit in FIG. 7 ;
  • FIG. 9 is a circuit diagram of a step-down power supply illustrating a fourth embodiment of the invention.
  • FIG. 10 is a voltage, current, and timing waveform diagram illustrating the operation of the stepped-down voltage output circuit in FIG. 9 ;
  • FIG. 11 is a circuit diagram of a step-down power supply illustrating a fifth embodiment of the invention.
  • FIG. 12 is a voltage, current, and timing waveform diagram illustrating the operation of the stepped-down voltage output circuit in FIG. 11 ;
  • FIG. 13 is a circuit diagram of a conventional step-down power supply
  • FIG. 14 is a voltage, current, and timing waveform diagram illustrating the operation of the conventional step-down power supply shown in FIG. 13 ;
  • FIG. 15 is a circuit diagram of another conventional step-down power supply
  • FIG. 16 is a voltage, current, and timing waveform diagram illustrating the operation of the conventional step-down power supply shown in FIG. 15 ;
  • FIG. 17 is a circuit diagram of a further conventional step-down power supply
  • FIG. 18 is a voltage and timing waveform diagram illustrating the operation of the stepped-down voltage output circuit in FIG. 17 ;
  • FIG. 19 is a voltage, current, and timing waveform diagram illustrating the operation of the conventional step-down power supply in FIG. 15 ;
  • FIG. 20 is another voltage, current, and timing waveform diagram illustrating the operation of the stepped-down voltage output circuit in FIG. 17 .
  • FIG. 1 A step-down power supply that meets the first object of the present invention is shown in FIG. 1 .
  • This step-down power supply 200 which comprises a differential amplifier 201 , a PMOS transistor 202 , a pull-down circuit 203 , and a pull-up circuit 204 , is integrated into a semiconductor memory chip with internal load circuits 205 including sense amplifiers that amplify memory cell voltages.
  • the step-down power supply 200 receives power from an external source at a voltage VCC and supplies the power at a lower internal voltage VDD to the load circuits 205 .
  • the PMOS transistor 202 functions as the load driver, receiving VCC at its input terminal or source terminal and supplying VDD from its output terminal or drain terminal to an internal power supply node to which the load circuits 205 are connected.
  • the differential amplifier 201 compares the internal power supply voltage VDD with a reference voltage Vref and adjusts the conductivity of the PMOS transistor 202 so as to hold VDD equal to Vref.
  • the output terminal of the differential amplifier 201 is connected to the control terminal or gate terminal of the PMOS transistor 202 through a control node G 0 .
  • the power supply voltage drop (VCC ⁇ VDD) in the PMOS transistor 202 varies in response to the gate voltage of the PMOS transistor 202 (the voltage at the control node G 0 ) and the amount of current conducted (IVDD).
  • Transistor input, output, and control terminals will be referred to hereinafter simply as the source, drain, and gate.
  • the source and drain are the current-conducting terminals, one being the input terminal, the other the output terminal. Either the source or drain may be the input terminal.
  • the gate is the control terminal that controls the conductivity of the transistor.
  • the pull-down circuit 203 receives a sense amplifier activation signal (SA_ON), generated by an external control circuit not shown in the drawing, and responds by temporarily pulling down the voltage of the control node G 0 .
  • SA_ON sense amplifier activation signal
  • the pull-up circuit 204 then temporarily pulls up the voltage of the control node G 0 .
  • the pull-down circuit 203 includes a pull-down signal generator 203 a , an AND gate 203 b , and an NMOS transistor 203 c .
  • the pull-down signal generator 203 a generates a pull-down pulse signal having a predetermined high pulse width when the sense amplifier activation signal SA_ON goes high.
  • the AND gate 203 b takes the logical AND of the pull-down pulse signal and the sense amplifier activation signal SA_ON.
  • the NMOS transistor 203 c has its gate connected to the output of the AND gate 203 b , its drain connected to the control node G 0 , and its source connected to ground (VSS).
  • the pull-up circuit 204 includes a pull-up signal generator 204 a , a NAND gate 204 b , and a PMOS transistor 204 c .
  • the pull-up signal generator 204 a generates a pull-up pulse signal having a predetermined high pulse width when a delay time equal to the pulse width of the pull-down signal has elapsed after the sense amplifier activation signal SA_ON goes high.
  • the NAND gate 204 b takes the logical NOT-AND of the sense amplifier activation signal SA_ON and the pull-up signal.
  • the PMOS transistor 204 c has its gate connected to the output of the NAND gate 204 b , its drain connected to the control node G 0 , and its source connected to the external VCC source.
  • step-down power supply 200 The operation of the step-down power supply 200 will be described with reference to FIG. 3 .
  • the pull-down signal generator 203 a in the pull-down circuit 203 When the sense amplifier activation signal SA-ON goes high, the pull-down signal generator 203 a in the pull-down circuit 203 generates a pull-down pulse signal with a predetermined high pulse width.
  • the AND gate 203 b receives the SA_ON signal and the pull-down pulse signal and outputs a high voltage to the gate of NMOS transistor 203 c .
  • NMOS transistor 203 c promptly turns on, pulling the voltage at the control node G 0 sharply down and quickly increasing the conductivity of the PMOS transistor 202 . This action prevents the decrease in the internal power supply voltage VDD that would otherwise result from the abrupt increase in the amount of current drawn by the load circuits 205 when the sense amplifiers starts operating.
  • the pull-up signal generator 204 a brings the pull-up signal high.
  • the NAND gate 204 b outputs a low voltage to the gate of PMOS transistor 204 c , which promptly turns on, increasing the voltage at the control node G 0 and decreasing the conductivity of PMOS transistor 202 .
  • the internal power supply voltage VDD does not rise, despite the initial pull-down operation.
  • the pull-down signal generator 203 a and pull-up signal generator 204 a are replaced by inverting delay lines comprising, for example, an odd number of inverters connected in cascade.
  • FIG. 4 Another step-down power supply that meets the first object of the present invention is shown in FIG. 4 .
  • This step-down power supply 300 which comprises a differential amplifier 301 , a PMOS transistor 302 , a one-shot circuit 303 , and an NMOS transistor 304 , is integrated into a semiconductor memory chip with internal load circuits 305 .
  • an external control circuit not shown in the drawing asserts a chip activation signal such as a chip select (CS) signal for activating the chip as a whole.
  • CS chip select
  • the step-down power supply 300 receives power from an external source at a voltage VCC and supplies the power at a lower internal voltage VDD to the load circuits 305 .
  • the differential amplifier 301 and PMOS transistor 302 are interconnected at a control node G 0 and operate in the same way as the corresponding differential amplifier and PMOS transistor in the first embodiment to hold the internal power supply voltage VDD equal to a reference voltage Vref.
  • the chip activation signal (CS) When the chip activation signal (CS) is asserted, the one-shot circuit 303 outputs a leak signal with a predetermined high pulse width to the gate of NMOS transistor 304 .
  • NMOS transistor 304 responds by turning on, allowing current to leak from the internal power supply node or VDD node to ground (VSS) for a predetermined time interval.
  • the one-shot circuit 303 and NMOS transistor 304 form a leak circuit.
  • the one-shot circuit 303 includes a delay line 303 a and an exclusive-OR gate 303 b .
  • the delay line 303 a contains an even number of inverters connected in cascade, and outputs a delayed CS signal.
  • the exclusive-OR gate 303 b receives both the CS signal and the delayed CS signal and outputs the leak signal.
  • the operation of the step-down power supply 300 will be described with reference to FIG. 6 .
  • the dotted lines indicate the VDD and G 0 waveforms that could be produced without the one-shot circuit 303 and NMOS transistor 304 .
  • the G 0 potential When the CS signal goes-high, noise effects may cause VDD to remain near the VCC level, in which case the G 0 potential also remains near the VCC level.
  • the load circuits 305 are activated and suddenly start to draw a large amount of current, VDD falls steeply.
  • the G 0 potential also falls, but as the fall starts from a level near VCC, at first PMOS transistor 302 remains substantially turned off.
  • the fall in the G 0 potential slightly lags the fall in VDD, due to the limited response speed of the differential amplifier 301 .
  • the presence of the one-shot circuit 303 and NMOS transistor 304 changes the behavior of VDD and G 0 from the dotted waveforms in FIG. 6 to the waveforms indicated by solid lines.
  • the one-shot circuit 303 drives the leak signal high for a predetermined interval, turning on NMOS transistor 304 to let current leak from the VDD node to ground (VSS) before the current drawn by the load circuits 305 increases.
  • the internal supply voltage VDD decreases, but the leakage through NMOS transistor 304 is not large enough to cause a sharp decrease in the VDD level, and the differential amplifier 301 has time to bring the voltage at the control node G 0 down to a point near the cut-off potential of PMOS transistor 302 before VDD goes below its normal level.
  • VDD drops further, but the resulting further drop in the G 0 level quickly increases the conductivity of PMOS transistor 302 . This increase is sufficient to halt the drop in the VDD level at a point near the reference voltage level. Thereafter, VDD remains substantially steady at this level.
  • the initial leakage of current from the VDD node to ground gives the differential amplifier a head start that prevents the response of the step-down power supply from being degraded by noise and other unwanted effects that may arise when the chip is activated.
  • FIG. 7 A step-down power supply that meets the second object of the present invention is shown in FIG. 7 .
  • This step-down power supply 1 receives power from an external source at a voltage VCC, such as 3.3 V, for example, and supplies the power at a lower internal voltage VDD equal to a reference voltage Vref, such as 2.5 V, for example, to a load circuit 2 .
  • the step-down power supply 1 comprises a reference voltage generator 10 , a stepped-down voltage output circuit 20 , and a control circuit 30 .
  • the reference voltage generator 10 generates the reference voltage Vref.
  • the control circuit 30 switches a step-down control signal S 30 between high and low logic levels according to the amount of current IVDD drawn by the load circuit 2 .
  • the step-down control signal S 30 is high when IVDD is high and low when IVDD is low. Descriptions of the internal structure of the reference voltage generator 10 and control circuit 30 will be omitted so as not to obscure the invention with unnecessary detail.
  • the stepped-down voltage output circuit 20 receives the reference voltage Vref and step-down control signal S 30 and outputs the internal power supply voltage VDD.
  • the stepped-down voltage output circuit 20 comprises PMOS transistors 21 , 22 , 27 , NMOS transistors 23 , 24 , 25 , and a constant-current source 26 .
  • PMOS transistor 21 has its source connected to the external VCC source, its drain connected to a node N 22 , and its gate connected to a node N 21 .
  • PMOS transistor 22 has its source connected to the external VCC source, and its drain and gate connected to node N 21 .
  • NMOS transistor 23 has its source connected to a node N 23 , its drain connected to node N 22 , and its gate connected to a node N 25 .
  • NMOS transistor 24 has its source connected to node N 23 , its drain connected to node N 21 , and its gate connected to a node N 24 .
  • NMOS transistor 25 has its source connected to ground (VSS), its drain connected to node N 23 , and its gate connected to a node N 26 .
  • PMOS transistor 27 has its source connected to the external VCC source, its drain connected to node N 24 , and its gate connected to node N 22 .
  • the constant-current source 26 is connected between node N 23 and ground (VSS).
  • a capacitor 28 is connected between node N 25 and node N 26 .
  • Node N 26 receives the step-down control signal S 30 .
  • Node N 25 receives the reference voltage Vref.
  • Node N 24 is the internal power supply node from which the internal power supply voltage VDD is output through the control circuit 30 to the load circuit 2 .
  • NMOS transistor 23 functions as the first element
  • NMOS transistor 25 functions as the second element
  • PMOS transistor 27 functions as the third element.
  • the step-down power supply 1 in FIG. 7 is identical to the conventional step-down power supply in FIG. 17 except for the additional capacitor 28 .
  • step-down power supply 1 in FIG. 7 is illustrated by the waveforms in FIG. 8 , using the same notation as in FIG. 20 .
  • the load circuit 2 draws current IVDD equal to I 1 in the standby state and I 2 in the active state.
  • IVDD abruptly increases from I 1 to I 2 , causing the step-down control signal S 30 to go high.
  • the current flowing between node N 23 and ground (VSS) abruptly increases from I 26 to I 26 +I 25 and the voltage at node N 23 abruptly decreases from a value Vtn to a lower value Vtn ⁇ , where ⁇ depends on the characteristics of the PMOS and NMOS transistors used.
  • the voltage drop at node N 23 is coupled through the gate-source capacitance of NMOS transistor 23 to node N 25 , but the voltage rise on the S 30 signal line is also coupled to node N 25 , through capacitor 28 .
  • the effects of the coupled voltage drop and the coupled voltage rise substantially cancel out, so that the reference voltage Vref at node N 25 remains substantially unchanged at V 40 , instead of falling temporarily by the amount ⁇ V 1 shown in FIG. 20 .
  • the increased current flow through PMOS transistor 21 drops the voltage at node N 22 abruptly from VCC ⁇ Vtp 3 (its normal value in the standby state) to a lower level.
  • the potential drop at node N 22 is even greater than the corresponding potential drop at node N 42 in FIG. 20 , because node N 25 remains at the V 40 level, but feedback in the stepped-down voltage output circuit 20 quickly brings node N 22 up to its normal value in the active state (VCC ⁇ Vtp 4 ).
  • the internal power supply voltage VDD temporarily drops by an amount ⁇ V 3 , but this amount is far smaller than the drop ⁇ V 1 in FIG. 20 , and VDD also quickly returns to the V 40 level.
  • the step-down control signal S 30 goes low, causing the current flowing between node N 23 and ground (VSS) to decrease from I 26 +I 25 to I 26 and the voltage at node N 23 to increase from Vtn ⁇ to Vtn.
  • the voltage rise at node N 23 is coupled through the gate-source capacitance of NMOS transistor 23 to node N 25 , but the effect of this rise is canceled by the effect of the drop in the S 30 voltage, which is coupled to node N 25 through capacitor 28 .
  • the reference voltage Vref at node N 25 remains substantially constant at V 40 , and the internal power supply voltage VDD rises by just ⁇ V 4 (an amount far smaller than corresponding rise ⁇ V 2 in FIG. 20 ) before quickly being restored to the V 40 level.
  • the effect of the additional capacitor 28 interconnecting nodes N 25 and N 26 is thus to keep the reference voltage Vref at its normal V 40 level when the step-down control signal S 30 switches between the high level and the low level, thereby greatly reducing the temporary fluctuations in the internal power supply voltage VDD that occur at transitions of the load circuit 2 between the active state and the standby state.
  • the load circuit 2 accordingly does not suffer temporary degradation of its response speed, timing margin, or input voltage margin to a degree that might lead to malfunction.
  • This step-down power supply 1 comprises a reference voltage generator 10 , a control circuit 30 , a stepped-down voltage output circuit 50 , and a pulse generator 60 .
  • the reference voltage generator 10 and control circuit 30 operate as in the third embodiment, the reference voltage generator 10 generating a reference voltage Vref, the control circuit 30 generating a step-down control signal S 30 that switches between high and low logic levels according to an amount of current IVDD drawn by the load circuit 2 .
  • the pulse generator 60 receives the step-down control signal S 30 and generates a pair of pulse signals S 60 N and S 60 P.
  • S 60 N is normally low but goes high for a predetermined interval t 1 when the step-down control signal S 30 goes high.
  • S 60 P is normally high but goes low for a predetermined interval t 2 when the step-down control signal S 30 goes low.
  • a description of the internal structure of the pulse generator 60 will be omitted, as pulse-generating circuits are well known.
  • the stepped-down voltage output circuit 50 receives the reference voltage Vref, the step-down control signal S 30 , and the pulse signals S 60 N and S 60 P, and outputs the internal power supply voltage VDD.
  • the stepped-down voltage output circuit 50 comprises PMOS transistors 51 , 52 , 57 , 58 , NMOS transistors 53 , 54 , 55 , 59 , and a constant-current source 56 .
  • PMOS transistor 51 has its source connected to an external VCC source, its drain connected to a node N 52 , and its gate connected to a node N 51 .
  • PMOS transistor 52 has its source connected to the external VCC source and its drain and gate connected to node N 51 .
  • NMOS transistor 53 has its source connected to a node N 53 , its drain connected to node N 52 , and its gate connected to a node N 55 .
  • NMOS transistor 54 has its source connected to node N 53 , its drain connected to node N 51 , and its gate connected to node N 54 .
  • NMOS transistor 55 has its source connected to ground (VSS), its drain connected to node N 53 , and its gate connected to a node N 56 .
  • PMOS transistor 57 has its source connected to the external VCC source, its drain connected to node N 54 , and its gate connected to node N 52 .
  • PMOS transistor 58 has its source connected to the external VCC source, its drain connected to node N 52 , and its gate connected to a node N 57 .
  • NMOS transistor 59 has its source connected to ground (VSS), its drain connected to node N 52 , and its gate connected to a node N 58 .
  • the constant-current source 56 is connected between ground (VSS) and node N 53 .
  • Node N 55 receives the reference voltage Vref, and node N 56 receives the step-down control signal S 30 .
  • Node N 57 receives the pulse signal S 60 P, and node N 58 receives the pulse signal S 60 N.
  • Node N 54 is the internal power supply node from which the internal power supply voltage VDD is output through the control circuit 30 to the load circuit 2 .
  • NMOS transistor 53 functions as the first element
  • NMOS transistor 55 functions as the second element
  • PMOS transistor 57 functions as the third element.
  • the stepped-down voltage output circuit 50 is identical to the conventional stepped-down voltage output circuit in FIG. 17 except for the additional PMOS transistor 58 and NMOS transistor 59 .
  • step-down power supply 1 in FIG. 9 The operation of the step-down power supply 1 in FIG. 9 is illustrated by the waveforms in FIG. 10 , using the same notation as in FIG. 20 .
  • the load circuit 2 draws current IVDD equal to I 1 in the standby state and I 2 in the active state.
  • IVDD abruptly increases from I 1 to I 2 , causing the step-down control signal S 30 to go high.
  • the current flowing between node N 53 and ground (VSS) abruptly increases from I 56 to I 56 +I 55 and the voltage at node N 53 abruptly decreases from a value Vtn to a lower value Vtn ⁇ , where ⁇ depends on the characteristics of the PMOS and NMOS transistors used.
  • the voltage drop at node N 53 is coupled through the gate-source capacitance of NMOS transistor 53 to node N 55 , where the reference voltage Vref decreases temporarily from V 40 to V 40 ⁇ V 1 , as in FIG. 20 .
  • the pulse generator 60 activates pulse signal S 60 N, supplying a high pulse to node N 58 , and NMOS transistor 59 is turned on for the duration (t 1 ) of this pulse.
  • the voltage at node N 52 is therefore pulled down from VCC ⁇ Vtp 3 to VSS for a period of time t 1 . Because this drop in the potential at node N 52 is greater than the corresponding drop in the potential of node N 42 in FIG. 20 , PMOS transistor 57 is turned on more fully, and the internal power supply voltage VDD decreases by just ⁇ V 5 instead of by the larger amount ⁇ V 1 in FIG. 20 .
  • VDD has already returned to the V 40 level.
  • normal feedback control in the stepped-down voltage output circuit 50 operates to return the potential at node N 52 to its usual level (VCC ⁇ Vtp 4 ) in the active state, and hold the internal power supply voltage VDD at the same level as the reference voltage Vref, which has by then also returned to V 40 .
  • the step-down control signal S 30 goes low, causing the current flowing between node N 53 and ground (VSS) to decrease from I 56 +I 55 to I 56 and the voltage at node N 53 to increase from Vtn ⁇ to Vtn.
  • the voltage rise at node N 53 is coupled through the gate-source capacitance of NMOS transistor 53 to node N 55 , causing the reference voltage Vref to increases temporarily from V 40 to V 40 + ⁇ V 2 , as in FIG. 20 .
  • the pulse generator 60 activates pulse signal S 60 P, supplying a low pulse to node N 57 , and PMOS transistor 58 is turned on for the duration (t 2 ) of this pulse.
  • the voltage at node N 52 is therefore pulled up from VCC ⁇ Vtp 4 to VCC for a period of time t 2 , during which PMOS transistor 57 is substantially turned off.
  • the internal power supply voltage VDD increases by ⁇ V 6 , but this is far smaller than the corresponding increase ⁇ V 2 in FIG. 20 , and the small amount of current IVDD still drawn by the load circuit 2 pulls VDD back down toward the normal V 40 level.
  • normal feedback in the stepped-down voltage output circuit 50 operates to return the potential at node N 52 to its usual level (VCC ⁇ Vtp 3 ) in the standby state, and hold the internal power supply voltage VDD at the same level as the reference voltage Vref, which has by then also returned to V 40 .
  • Time t 2 is longer than time t 1 , because when the load circuit 2 is active, feedback control by the stepped-down voltage output circuit 50 must commence comparatively quickly to maintain the proper VDD level, while when the load circuit 2 is inactive and not drawing significant current, VDD will remain near the proper level even if PMOS transistor 57 is left switched off for a while.
  • PMOS transistor 58 and NMOS transistor 59 are turned on for predetermined periods, during which the node N 52 is held at the ground level VSS or the external power supply level VCC to suppress the temporarily drop or rise in the internal power supply voltage VDD that would otherwise occur due to fluctuations in the reference voltage Vref immediately after a transition of the load circuit 2 between the active and standby states.
  • the load circuit 2 accordingly does not suffer temporary degradation of its response speed, timing margin, or input voltage margin to a degree that might lead to malfunction.
  • This step-down power supply 1 comprises a control circuit 30 , a reference voltage selector 70 , a reference voltage generator 80 , and a stepped-down voltage output circuit 90 .
  • the control circuit 30 generates a step-down control signal S 30 that switches between high and low levels according to the amount of current drawn by the load circuit 2 as in the third and fourth embodiments.
  • the reference voltage selector 70 receives the step-down control signal S 30 and outputs three reference-voltage select signals S 90 , S 91 , and S 92 .
  • the reference voltage generator 80 generates three different reference voltages Vrefh, Vrefm, and Vrefl.
  • the stepped-down voltage output circuit 90 receives the step-down control signal S 30 , the reference voltages Vrefh, Vrefm, and Vrefl, and the reference-voltage select signals S 90 , S 91 , and S 92 and outputs the internal power supply voltage VDD.
  • the stepped-down voltage output circuit 90 comprises PMOS transistors 91 , 92 , 97 , 98 , 99 , 100 , NMOS transistors 93 , 94 , 95 , and a constant-current source 96 .
  • PMOS transistor 91 has its source connected to the external VCC source, its drain connected to a node N 92 , and its gate connected to a node N 91 .
  • PMOS transistor 92 has its source connected to the external VCC source and its drain and gate connected to node N 91 .
  • NMOS transistor 93 has its source connected to a node N 93 , its drain connected to node N 92 , and its gate connected to a node N 95 .
  • NMOS transistor 94 has its source connected to node N 93 , its drain connected to node N 91 , and its gate connected to a node N 94 .
  • NMOS transistor 95 has its source connected to ground (VSS), its drain connected to node N 93 , and its gate connected to a node N 96 .
  • the constant-current source 96 is connected between ground (VSS) and node N 93 .
  • PMOS transistor 97 has its source connected to the external VCC source, its drain connected to node N 94 , and its gate connected to node N 92 .
  • PMOS transistor 98 has its source connected to a node N 97 , its drain connected to node N 95 , and its gate connected to a node N 9 C.
  • PMOS transistor 99 has its source connected to a node N 98 , its drain connected to node N 95 , and its gate connected to a node N 9 B.
  • PMOS transistor 100 has its source connected to node N 99 , its drain connected to node N 95 , and its gate connected to a node N 9 A.
  • Node N 96 receives the step-down control signal S 30
  • node N 97 receives reference voltage Vrefh
  • node N 98 receives reference voltage Vrefm
  • node N 99 receives reference voltage Vrefl.
  • Node N 9 A receives reference-voltage select signal S 90
  • node N 9 B receives reference-voltage select signal S 91
  • node N 9 C receives reference-voltage select signal S 92 .
  • Node N 94 is the internal power supply node from which the internal power supply voltage VDD is output through the control circuit 30 to the load circuit 2 .
  • NMOS transistor 93 functions as the first element
  • NMOS transistor 95 as the second element
  • PMOS transistor 97 as the third element.
  • the stepped-down voltage output circuit 90 is identical to the conventional stepped-down voltage output circuit in FIG. 17 except for the additional NMOS transistors 98 , 99 , 100 .
  • step-down power supply 1 in FIG. 11 The operation of the step-down power supply 1 in FIG. 11 is illustrated by the waveforms in FIG. 12 .
  • the reference voltage generator 80 outputs a voltage V 40 as reference voltage Vrefm, a voltage V 40 + ⁇ as reference voltage Vrefh, and a voltage V 40 ⁇ as reference voltage Vrefl, where ⁇ is a predetermined positive value.
  • S 90 and S 92 are normally inactive (high) and S 91 is normally active (low), so node N 95 normally receives reference voltage Vrefm (V 40 ).
  • the step-down control signal S 30 goes high. This causes the current between node N 93 and ground (VSS) to increase from I 96 to I 96 +I 95 , decreasing the voltage at node N 93 from Vtn to Vtn ⁇ . Because of the gate-source capacitance of NMOS transistor 93 , the voltage drop at node N 93 is coupled to node N 95 . In FIG.
  • the step-down control signal S 30 goes low, causing the current flowing between node N 93 and ground (VSS) to decrease from I 96 +I 95 to I 96 and the voltage at node N 93 to increase from Vtn ⁇ to Vtn.
  • the voltage rise at node N 53 is coupled through the gate-source capacitance of NMOS transistor 53 to node N 95 .
  • the temporary increase in the reference voltage applied to node N 95 from the normal level of V 40 to V 40 + ⁇ cancels out the voltage drop that would occur at node N 95 because of the gate-source capacitive coupling through NMOS transistor 93 immediately after the load circuit 2 enters the active state.
  • the temporary decrease in the reference voltage applied to node N 95 from V 40 to V 40 ⁇ cancels out the voltage rise that would occur at node N 95 because of the gate-source capacitive coupling through NMOS transistor 93 immediately after the load circuit 2 enters the standby state.
  • the load circuit 2 accordingly does not suffer temporary degradation of its response speed, timing margin, or input voltage margin to a degree that might lead to malfunction.
  • the gates of NMOS transistors 23 , 53 , and 93 receive the reference voltage directly, but the reference voltage may be received through a resistor connected between the gate of the transistor and the reference voltage generator.
  • a resistor may be connected between the transistor gate and ground (VSS). Similar resistors may be inserted between the drain of PMOS transistors 47 , 57 , and 97 and the gates of NMOS transistors 24 , 54 , and 94 , and/or between the gates of these NMOS transistors and ground (VSS).
  • the resistors may be PMOS or NMOS transistors sized to provide a specified on-resistance.
  • the capacitor 28 in the third embodiment may be a PMOS or NMOS transistor with interconnected source-and drain electrodes.
  • either PMOS transistor 58 or NMOS transistor 59 may be eliminated, and the pulse generator 60 may output only a single pulse signal to the remaining one of these two transistors.
  • Nodes N 97 , N 98 , and N 99 are electrically connected to node N 95 in the fifth embodiment by PMOS transistor switches, but NMOS transistor switches may be used, or a PMOS transistor and an NMOS transistor connected in parallel may be used for each switch.
  • the number of different reference voltages used in the fifth embodiment may be increased from three to four or more.

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US20080231351A1 (en) * 2007-03-20 2008-09-25 Kabushiki Kaisha Toshiba Voltage step-down circuit
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CN1728519A (zh) 2006-02-01
KR20060042151A (ko) 2006-05-12
JP4354360B2 (ja) 2009-10-28
US7468624B2 (en) 2008-12-23
JP2006039816A (ja) 2006-02-09
US20080018388A1 (en) 2008-01-24
KR101128356B1 (ko) 2012-03-26
US20060017496A1 (en) 2006-01-26

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