US7047474B2 - Decoding concatenated codes via parity bit recycling - Google Patents

Decoding concatenated codes via parity bit recycling Download PDF

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US7047474B2
US7047474B2 US10/325,833 US32583302A US7047474B2 US 7047474 B2 US7047474 B2 US 7047474B2 US 32583302 A US32583302 A US 32583302A US 7047474 B2 US7047474 B2 US 7047474B2
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message data
decoder
decoding
data
parity
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US20040123217A1 (en
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Do-Jun Rhee
Masaki Sato
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Priority to KR10-2003-0028597A priority patent/KR100524961B1/ko
Priority to TW092113291A priority patent/TWI262658B/zh
Priority to CNB031411398A priority patent/CN100428635C/zh
Priority to FR0307155A priority patent/FR2849304B1/fr
Priority to JP2003207455A priority patent/JP4284125B2/ja
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N7/00—Television systems
    • H04N7/015—High-definition television systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/253—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with concatenated codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes
    • H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, Bose-Chaudhuri-Hocquenghem [BCH] codes using error location or error correction polynomials
    • H03M13/1515—Reed-Solomon codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
    • H03M13/256—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with trellis coding, e.g. with convolutional codes and TCM
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2948—Iterative decoding

Definitions

  • a concatenated code is a doubly-encoded type of code having an inner code and an outer code.
  • the inner code encodes the outer code.
  • the inner code corrects most of the errors introduced by the communications channel and is typically a convolution code.
  • the outer code corrects the majority of decoding errors (which typically are bursty) that occur during the first decoding.
  • the Reed-Solomon (R-S) code is commonly used as the outer code.
  • FIG. 1 is a block diagram of a typical concatenated code system 100 according to the Background Art.
  • the system 100 includes: an outer encoder 102 ; an optional interleaver 104 ; an inner encoder 106 ; a modulator 108 ; a communications channel 110 ; a demodulator 112 ; an inner decoder 114 ; an optional de-interleaver 116 (present if the interleaver 104 is present); and an outer decoder 118 .
  • FIG. 2 is a block diagram of a concatenated code iterative decoder 200 according to the Background Art that is compliant with the Advanced Television Standards Committee (ATSC) 8-VSB (vestigial sidebands) standard.
  • the decoder 200 includes: a first inner, trellis-coded modulation (TCM) decoder 202 ; an optional de-interleaver 204 (that itself has a symbol de-interleaver 206 and a convolutional de-interleaver 208 ); a first outer, R-S decoder 210 ; an optional interleaver 212 (that itself has a convolutional interleaver 214 and a symbol interleaver 216 ); an inner TCM encoder 218 ; a second inner TCM decoder 220 ; a second optional de-interleaver 222 (present if interleaver 212 is present) (the de-interleaver 222 including a symbol de-interleaver 224 and a
  • the decoder 200 is designed to work with a channel exhibiting additive white Gaussian noise (AWGN).
  • AWGN additive white Gaussian noise
  • the ATSC standard for 8-VSB requires a decoder to successfully decode a signal that is received having a maximum segment error rate (SER) of 1.93 ⁇ 10 ⁇ 4 at a minimum energy per symbol (E S /N O ), or signal to noise ratio (SNR), of 14.9 dB.
  • SER segment error rate
  • E S /N O minimum energy per symbol
  • SNR signal to noise ratio
  • the decoder 200 will decode a signal having an SNR of 14.9 or greater. For an SNR below 14.9 dB, the decoder 200 will fail to decode the received signal, yet such failure does not prevent the decoder 200 from being considered ATSC-compliant.
  • An embodiment of the invention provides a method, apparatus and article of manufacture for decoding concatenated codes.
  • Such a method includes: receiving data representing concatenated codes; first inner decoding the received data resulting in first inner message data and parity data; first outer decoding the first inner message data, resulting in reliability information and first outer message data; second inner decoding the first outer message data, resulting in second inner message data; and second outer decoding the second inner message data.
  • the second inner decoding is a function of: the reliability information from the first outer decoding; the first outer message data; and the parity data from the first inner decoding.
  • FIG. 1 is a block diagram of a typical concatenated code system according to the Background Art.
  • FIG. 2 is a block diagram of a concatenated code iterative decoder according to the Background Art.
  • FIG. 3 is a block diagram of a concatenated code decoder according to an embodiment of the invention.
  • FIG. 4 is a block diagram of an iterative decoder of concatenated codes according to an embodiment of the invention.
  • FIG. 5 is a Table representing a qualitative assessment information according to an embodiment of the invention.
  • FIG. 6 is an example of a trellis diagram for inner decoders according to an embodiment of the invention.
  • FIG. 7 is a Table of branch metric values according to an embodiment of the invention.
  • FIG. 8 is a block diagram of a pipelined iterative decoder of concatenated codes according to an embodiment of the invention.
  • FIGS. 9A and 9B are unified modeling language (UML) sequence diagrams of concatenated code decoding actors and actions according to an embodiment of the invention.
  • UML unified modeling language
  • FIG. 10 is a more detailed block diagram of a second inner decoder according to an embodiment of the invention.
  • Actions in a UML sequence diagram are depicted with arrows of different styles.
  • A would indicate an action that expects a response action.
  • A would indicate a response action.
  • A would indicate an action for which the response is implied.
  • a would indicate an action for which no response is expected.
  • An embodiment of the invention represents a recognition of the following.
  • Terrestrial broadcasting environments are really not AWGN channels. Rather, the received signals include the directly received version of the transmitted signal as well as reflections (indirectly received versions) of the transmitted signal.
  • a signal that would arrive at a 14.9 dB level via an AWGN channel is more likely to arrive as a 14.6 dB signal in the real terrestrial broadcasting environments.
  • Another embodiment of the invention represents a recognition of the following. If there are errors in the first outer decoded message data from the first outer decoder 210 , then parity data generated by the inner TCM encoder 218 (a re-encodation! will have errors. And the second inner TCM decoder 220 cannot correct such errors.
  • Another embodiment of the invention represents a recognition that decoder performance, in terms of the minimum SNR signal that can be decoded, can be enhanced without necessarily changing the architecture of the encodation according to the Background.
  • FIG. 3 is a block diagram of a concatenated code decoder 300 according to an embodiment of the invention.
  • the decoder 300 includes: a first inner, e.g., TCM, decoder 302 ; a delay unit 304 ; an optional first de-interleaver 306 (that itself can include a first symbol de-interleaver 308 and a first convolutional de-interleaver 310 ); a first outer, e.g., R-S, decoder 312 ; an optional interleaver 314 (that itself can include a convolutional interleaver 316 and a symbol interleaver 318 ); a second inner, e.g., TCM, decoder 320 ; an optional second de-interleaver 322 (that itself can include a second symbol de-interleaver 324 and a second convolutional de-interleaver 326 ); and a second outer, e.g., R-S, decoder
  • parity data from the first inner decoder 302 is not discarded but instead is provided to the delay unit 304 .
  • the delay unit 304 then provides the parity data (after suitable delay) to the second inner decoder 320 .
  • the delay unit 304 time-aligns the parity data to the first outer message data from the first outer decoder 312 .
  • a suitable delay by the delay unit 304 can compensate for the delay introduced by the R-S decoder 312 and (if present) the first de-interleaver 306 , resulting in time re-alignment between the parity data and the first outer message data.
  • the second inner decoder 320 receives reliability information from the first outer decoder 312 .
  • reliability information concerns the reliability of the parity data from the first inner decoder 302 and the reliability of the first outer message data generated by the first outer decoder 312 .
  • Such reliability information can be a qualitative assessment (e.g., low, middle or high) as depicted in the Table of FIG. 5 , to be discussed below.
  • the decoder 312 when the number of errors in the received packet is greater than the error correcting capability of the decoder 312 (e.g., more than 8 errors for 8-VSB), then the decoder 312 does not correct any of the errors in the packet. In this circumstance, the decoder 312 can generate a signal indicating that the corresponding packet is uncorrectable. But when the errors are not so great in number as to preclude correction, then the decoder 312 can generate a signal indicating corrected symbol error position via the generation of an error location polynomial.
  • the error correcting capability of the decoder 312 e.g., more than 8 errors for 8-VSB
  • Performance of the decoder 300 according to an embodiment of the invention is improved relative to the Background by inputting the parity data from the first inner decoder 302 and the reliability information from the first outer decoder 312 , as well as the first outer message data from the first outer decoder 312 .
  • the decoder 300 can decode a signal having at least a 14.6 dB (if not lower) SNR.
  • FIG. 6 is an example of a trellis diagram 600 (here, 4-states are possible in two registers of an encoder) representing the algorithm of the encoders corresponding to the inner decoders 302 and 320 .
  • FIG. 6 shows transmitted data with states according to the encoding algorithm.
  • the particular trellis 600 is provided merely to further discussion and is not limiting.
  • Reference number 602 points to a starting state, namely, of the two registers of the encoder.
  • Ref. no. 604 points to a transition from one state to another upon receiving new input data in the encoder.
  • Ref. no. 608 points to an ending state reached during the transition 604 .
  • Ref. no. 606 points to the two possible output values resulting from the transition 604 .
  • the corresponding encoder goes from state 00 to state 10
  • either ⁇ 3 or 5 will be output, i.e., transmitted.
  • Decoding in the decoders 302 / 320 can be done by selecting from among multiple branch metric candidate values for each possible branch in the trellis 600 relative to the inputted data (the received symbol currently under consideration), then performing an Add-Compare-Select (ACS) process, and then performing a Traceback process.
  • ACS Add-Compare-Select
  • Traceback process The ACS and Traceback processes are known. But selecting from among multiple branch metric candidate values, etc., represents an embodiment of the invention.
  • the branch metric values can be based upon the Euclidian distance in the case of soft data, or the Hamming distance in the case of hard data.
  • the parity data from the first inner decoder 302 and the first outer message data can be soft decision data in the sense that it has an 8-bit quantization, i.e., it is 8-bit data representing 0–255 levels.
  • the branch metric values of the trellis 600 in the second inner decoder 320 can be weighted according to the reliability information from the first outer decoder 312 and the parity data from the first inner decoder 302 .
  • FIG. 7 is a Table depicting an example of such weightings. Values in the first column, “8-VSB level,” represent the values that a received symbol can take. Such values correspond to the combination of the associated parity bit value and the values of the associated two bits of message data.
  • Within each group of columns is a column corresponding to Case 1 , Case 2 and Case 3 .
  • a case is a set of data that can be accessed, e.g., via a look-up table (LUT).
  • Values in each case of the Table of FIG. 7 can be determined as follows. For each possible branch, each of the 8 possible VSB levels is evaluated. For a given one of the 8-VSB levels, the Euclidean distance from each of the two possible outputs to the given level is determined and the smaller of the two distances is selected and stored as the corresponding value in the column representing a portion of the case.
  • the branch metric values of the Case 1 columns of FIG. 7 correspond to a situation in which the reliability of the first outer decoder 312 is qualitatively assessed as being “middle” and the reliability of the parity data from the first inner decoder 302 is “middle.” Similar correspondences exist with the Case 2 and Case 3 columns.
  • FIG. 4 is a block diagram of an iterative decoder 400 for decoding concatenated codes according to an embodiment of the invention.
  • the decoder 400 includes a first inner, e.g., TCM, decoder 402 ; a delay unit 404 ; an optional first de-interleaver 406 (that itself can include a first symbol de-interleaver 408 and a first convolutional de-interleaver 410 ); a first outer, e.g., R-S, decoder 412 ; an optional interleaver 414 (that itself can include a convolutional interleaver 416 and a symbol interleaver 418 ); a second inner,.
  • decoder 420 e.g., TCM, decoder 420 ; an optional second de-interleaver 422 (that itself can include a second symbol de-interleaver 424 and a second convolutional de-interleaver 426 ); and a second outer, e.g., R-S, decoder 428 .
  • the units 404 and 414 – 428 can be considered to be a unit 430 that can be replicated/piplelined until a desired coding gain and bit error rate (BER) are achieved.
  • the unit 430 is a replicable unit 430 .
  • FIG. 8 depicts a block diagram of an iterative decoder 800 for decoding concatenated codes according to an embodiment of the invention.
  • the decoder 800 includes the replicable unit 430 and a similar replicable unit 830 .
  • the replicable unit 830 includes: a delay unit 804 ; an optional second interleaver 814 (that itself can include a second convolutional interleaver 816 and a second symbol interleaver 818 ); a third inner, e.g., TCM, decoder 820 ; an optional third de-interleaver 822 (that itself can include a third symbol de-interleaver 824 and a third convolutional de-interleaver 826 ); and a third outer, e.g., R-S, decoder 828 .
  • a delay unit 804 an optional second interleaver 814 (that itself can include a second convolutional interleaver 816 and a second symbol interleaver 818 ); a third inner, e.g., TCM, decoder 820 ; an optional third de-interleaver 822 (that itself can include a third symbol de-interleaver 824 and a third convolutional de-interleaver 8
  • FIGS. 9A and 9B are UML sequence diagrams of concatenated code decoding actors and actions according to an embodiment of the invention.
  • FIGS. 9A and 9B can be used to explain the operation of the iterative decoder of FIG. 8 .
  • concatenated codes are supplied from a source of such concatenated codes at action 902 .
  • An example of a source 802 can be a demodulator 112 that receives signals through a communications channel 110 .
  • the first inner decoder 402 receives the concatenated codes, decodes them and provides first inner message data to the optional first de-interleaver 406 at action 904 .
  • the first inner decoder 402 recycles the first parity data by providing it to the first delay unit 404 at action 906 .
  • the first de-interleaver 406 provides de-interleaved first inner message data to the first outer decoder 412 at action 907 .
  • the first inner message data can be provided directly to the first outer decoder 412 from the first inner decoder 402 .
  • the first outer decoder 412 decodes the de-interleaved first inner message data, resulting in first outer message data, which is provided to the optional interleaver 414 at action 908 .
  • the first outer decoder 412 also generates reliability information and provides it to the second inner decoder 420 at action 910 .
  • the first delay unit 404 delays the first parity data and provides it to the second inner decoder 420 at action 912 .
  • the interleaver 414 interleaves the first outer message data and provides the interleaved first outer message data to the second inner decoder 420 at action 914 .
  • the interleaver 414 can be omitted.
  • the first outer message data can be provided directly to the second inner decoder 420 from the first outer decoder 412 .
  • the second inner decoder 420 operates upon the reliability information and the first parity data while decoding the first outer message data, resulting in second inner message data, which the second inner decoder 420 provides to the optional second de-interleaver 422 at action 916 .
  • the second inner decoder 420 recycles the second parity data that it generates by providing the second parity data to the second delay unit 804 at action 918 .
  • the second de-interleaver 422 provides de-interleaved second inner message data to the second outer decoder 428 at action 920 .
  • the second inner message data can be provided directly to the second outer decoder 428 from the second inner decoder 420 .
  • the second outer decoder 428 decodes the de-interleaved second inner message data, resulting in second outer message data, which is provided to the optional second interleaver 814 at action 922 .
  • the second outer decoder 428 generates reliability information and provides it to the third inner decoder 820 at action 924 .
  • the second delay unit 804 delays the second parity data and provides it to the third inner decoder 820 at action 926 .
  • the second interleaver 814 interleaves the second outer message data and provides the interleaved second outer message data to the third inner decoder 820 at action 927 .
  • the interleaver 814 can be omitted.
  • the second outer message data can be provided directly to the third inner decoder 820 from the second outer decoder 428 .
  • the third inner decoder 820 operates upon the reliability information from the second outer decoder 428 and the second parity data from the second inner decoder 420 while decoding the second outer message data from the second outer decoder 428 , resulting in third inner message data, which the third inner decoder 820 provides to the optional third de-interleaver 822 at action 928 .
  • the third inner decoder 820 recycles the parity data that it generates by outputting the third parity data to a third delay unit (not depicted) at action 918 if a third replicable unit (not depicted) were present.
  • the third de-interleaver 822 provides de-interleaved third inner message data to the third outer decoder 828 at action 930 .
  • the third outer decoder 828 decodes the de-interleaved third inner message data, resulting in third outer message data, which is outputted. If a third replicable unit (not depicted) were present, then the following actions would also be included.
  • the third outer message data would be provided to an optional interleaver (not depicted) at action 932 . Also, the third outer decoder 828 would generate reliability information and would provide it to a fourth inner decoder (not depicted) at action 934 .
  • FIG. 10 is a more detailed block diagram of a second inner decoder, e.g., 420 , according to an embodiment of the invention.
  • An R-S decoder can have: a logic unit 1006 to assess whether the corresponding packet has a sufficiently small number of errors to be considered a correctable or uncorrectable packet, resulting in the UP output signal; and a logic unit 1008 to identify what bytes in a packet have been corrected (e.g., via generation of an error location polynomial), resulting in the CS signal.
  • the decoder 420 includes: a logic unit 1010 to select one LUT, from among multiple case-specific LUTs (see FIG. 7 ) of branch metric values, based upon the values of the UP signal and the CS signal (such as are shown in FIG. 5 ); a logic unit 1012 to index into the LUT selected by the logic unit 1010 in order to obtain branch metric values corresponding to four transmitted data pairs; an Add Compare Select (ACS) 1014 ; and a Trace Back (TB) unit 1016 .
  • the branch metric values obtained by the unit 1012 are added by the unit 1014 to the cumulative metric, the sums compared against each other, and the sum having the lowest magnitude selected.
  • ACS unit 1014 and the TB unit 1016 are known, no further discussion is provided.
  • inner and outer decoders have been discussed in terms of the inner decoders being TCM decoders and the outer decoders being R-S decoders.
  • Other combination of inner and outer decoders can be used, e.g., a Viterbi decoder with a convolutional code as the inner decoder and an R-S decoder as the outer decoder, or an R-S decoder as both the inner and outer decoders.

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US10/325,833 2002-12-23 2002-12-23 Decoding concatenated codes via parity bit recycling Expired - Fee Related US7047474B2 (en)

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Application Number Priority Date Filing Date Title
US10/325,833 US7047474B2 (en) 2002-12-23 2002-12-23 Decoding concatenated codes via parity bit recycling
KR10-2003-0028597A KR100524961B1 (ko) 2002-12-23 2003-05-06 패리티 비트를 재순환시키는 연속 코드 디코더 및 그 방법
TW092113291A TWI262658B (en) 2002-12-23 2003-05-16 Decoding concatenated codes via parity bit recycling
CNB031411398A CN100428635C (zh) 2002-12-23 2003-06-11 通过重复利用奇偶校验比特对级联码进行解码的方法和装置
FR0307155A FR2849304B1 (fr) 2002-12-23 2003-06-13 Procede et dispositif de decodage de codes concatenes par recyclage de bits de parite
JP2003207455A JP4284125B2 (ja) 2002-12-23 2003-08-13 パリティビットを再循環させる連続コードデコーダ及びその方法

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