US5973987A - Semiconductor memory device delaying ATD pulse signal to generate word line activation signal - Google Patents

Semiconductor memory device delaying ATD pulse signal to generate word line activation signal Download PDF

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US5973987A
US5973987A US09/267,161 US26716199A US5973987A US 5973987 A US5973987 A US 5973987A US 26716199 A US26716199 A US 26716199A US 5973987 A US5973987 A US 5973987A
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signal
output
memory cell
chip select
address
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Kiyoyasu Akai
Masayuki Yamashita
Motoi Ashida
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Renesas Electronics Corp
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Mitsubishi Electric Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/18—Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

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  • the present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device that delays a pulse signal from an ATD (Address Transition Detection) buffer to generate a word line activation signal.
  • ATD Address Transition Detection
  • ATD buffers are provided at various places that generate a one-shot pulse signal according to change of an address signal, a chip select signal, a read/write enable signal, and an input data signal.
  • a word line activation signal WLE is generated by a timing generator that delays the trailing edge of a pulse signal supplied from the ATD buffer as illustrated in FIG. 17.
  • a pulse signal LATD1 input to the timing generator is generated in response to change of a row address signal by an ATD buffer provided for a row address buffer, and an ATD signal LATD2 is generated in response to change of a column address signal by an ATD buffer provided for a column address buffer.
  • FIG. 18 is a block diagram illustrating a structure of an address buffer (row address buffer or column address buffer).
  • the address buffer generates internal address signals A and /A in response to an external address signal EAD when a chip select signal /CS is active (at a logical low level), and an address signal atd is supplied to a corresponding ATD buffer.
  • Word line activation signal WLE is supplied to a row decoder shown in FIG. 19.
  • the row decoder selectively activates word lines WL1-WL4 in response to internal address signals A1, /A1, A2, and /A2 when word line activation signal WLE is active (at a logical high level).
  • the timing generator generally includes multiple stages of delay circuits RDLs as shown in FIG. 17.
  • the pulse width of a signal output from delay circuit RDL remarkably increases as the power supply voltage decreases as indicated by (2) of FIG. 20.
  • FIGS. 21A-21R represents internal waveforms of the SRAM in the case that the power supply voltage is relatively high.
  • the pulse width of delay circuit RDL is relatively small, and the pulse width of word line activation signal WLE is accordingly in the range of an address cycle.
  • word lines WL2 and WL3 corresponding to the skew addresses do not rise since word line activation signal WLE is at a logical low or L level.
  • the current trend of miniaturization and reduced voltage of a semiconductor memory device requires that the operation of the memory device is ensured on one chip in a range of a higher supply voltage to a lower supply voltage.
  • Word line activation signal WLE fixed at H level thus causes word lines WL2 and WL3 corresponding to skew addresses, in addition to selected word lines WL1 and WL4, to rise.
  • word lines WL2 and WL3 corresponding to the skew addresses rise, it follows that data could be read at this instant from memory cells corresponding to the skew addresses, to delay access to a memory cell corresponding to a selected address. Further, in the case of the write cycle, writing could be done wrongly.
  • One object of the present invention is to provide a semiconductor memory device that can prevent delay of access to a memory cell and erroneous writing to a memory cell in a range of a higher supply voltage to a lower supply voltage.
  • a semiconductor memory device includes a memory cell array, an address buffer, an address change detect circuit, a first delay circuit, a drive signal inactivate circuit, and a decoder.
  • the memory cell array includes a plurality of memory cells arranged in rows and columns.
  • the address buffer generates an internal address signal in response to an external address signal.
  • the address change detect circuit generates a pulse signal in response to change of the external address signal.
  • the first delay circuit delays the trailing edge of the pulse signal from the address change detect circuit to generate a drive signal.
  • the drive signal inactivate circuit inactivates the drive signal for a prescribed period.
  • the decoder selects a row or column of the memory cell array in response to the internal address signal when the drive signal is active.
  • the address buffer includes a second delay circuit. The second delay circuit delays the external address signal for a prescribed period to output it as an internal address signal such that the internal address signal changes during the period in which the drive signal is inactive.
  • the drive signal is surely rendered inactive for a prescribed period regardless of the supply voltage, and during the inactive period of the drive signal, the internal address signal changes. Therefore, even if there is skew between internal address signals, a row or column corresponding to any skew address is never selected by a row decoder. As a result, reading of data at an instant from a memory cell corresponding to the skew address never happens and delay of access to a memory cell and an erroneous writing to a memory cell can be prevented in a range of a higher supply voltage to a lower supply voltage.
  • the first delay circuit includes multiple stages of delay circuits and the drive signal inactivate circuit includes a logic circuit.
  • the multiple stages of delay circuits delay the trailing edge of a pulse signal from the address change detect circuit.
  • the logic circuit receives an output from one of the multiple stages of delay circuits that is placed in an intermediate stage and receives an output from a delay circuit in the last stage.
  • the logic circuit In the semiconductor memory device described above, the logic circuit generates a drive signal which is inactive during the period from the leading edge of the pulse signal from the address change detect circuit to the trailing edge of the output from the delay circuit in the intermediate stage of the multiple stages of delay circuits.
  • the internal address signal changes in the inactive period of the drive signal. Therefore, even if skew occurs between internal address signals, a row or column corresponding to a skew address is never selected by a row decoder. As a result, reading of data at an instant from a memory cell corresponding to the skew address never happens and delay of access to a memory cell and incorrect writing to a memory cell can be prevented.
  • the semiconductor memory device further includes a third delay circuit.
  • the third delay circuit delays a chip select signal for a prescribed period to output it such that the delayed chip select signal as the output signal changes in the inactive period of the drive signal.
  • the address buffer generates the internal address signal in response to the external address signal when the chip select signal is active, and fixes the internal address signal when the chip select signal is inactive.
  • the decoder selects a row or column of the memory cell array in response to the internal address signal when the delayed chip select signal and the drive signal are active.
  • the delayed chip select signal changes in the inactive period of the drive signal to prevent a row or column corresponding to the fixed internal address signal from being selected by the row decoder. Accordingly, it is possible to prevent delay of access to an memory cell and erroneous writing to a memory cell.
  • the semiconductor memory device further includes a fourth delay circuit and an output buffer.
  • the fourth delay circuit delays a read/write enable signal for a prescribed period to output it such that the delayed read/write enable signal as the output signal changes in the inactive period of the drive signal.
  • the output buffer buffers a data signal from a memory cell when the delayed read/write enable signal is active to output the buffered one.
  • the data signal is output from the output buffer after the internal address signal is defined.
  • the semiconductor memory device further includes a fourth delay circuit and an input buffer.
  • the fourth delay circuit delays a read/write enable signal for a prescribed period to output it such that the delayed read/write enable signal as the output signal changes in the inactive period of the drive signal.
  • the input buffer buffers an externally supplied data signal when the delayed read/write enable signal is active.
  • the delayed read/write enable signal changes in the inactive period of the drive signal, the data signal is written from the input buffer into a memory cell after the internal address signal is defined. Accordingly, delay of access to a memory cell and incorrect writing can be prevented.
  • FIG. 1 is a block diagram illustrating an entire structure of an SRAM according to the first embodiment of the invention.
  • FIG. 2 is a block diagram illustrating structures of a memory cell array and a multiplexer shown in FIG. 1.
  • FIG. 3 is a circuit diagram illustrating a structure of a memory cell shown in FIG. 2.
  • FIG. 4 is a circuit diagram showing a structure of the memory cell shown in FIG. 2.
  • FIG. 5 is a timing chart representing a reading operation of data from the memory cell shown in FIG. 2 and a writing operation of data into the memory cell.
  • FIG. 6 is a block diagram showing a structure of a timing generator shown in FIG. 1.
  • FIG. 7 is a block diagram illustrating a structure of a row address buffer shown in FIG. 1.
  • FIGS. 8A and 8B are timing charts representing an operation of an ATD buffer shown in FIG. 1.
  • FIG. 9 is a block diagram showing a structure of a row decoder shown in FIG. 1.
  • FIG. 10 is a block diagram illustrating a structure of a column decoder shown in FIG. 1.
  • FIGS. 11A-11S are timing charts representing an operation of the SRAM according to the first embodiment of the present invention.
  • FIG. 12 is a block diagram illustrating an entire structure of an SRAM according to the second embodiment of the present invention.
  • FIG. 13 is a block diagram illustrating a structure of a chip select control circuit shown in FIG. 12.
  • FIG. 14 is a block diagram illustrating a structure of a read/write control circuit shown in FIG. 12.
  • FIGS. 15A-15X are timing charts representing an operation of the SRAM according to the second embodiment of the present invention.
  • FIG. 16 is a block diagram illustrating a modification of the chip select control circuit in FIG. 13 and the read/write control circuit in FIG. 14.
  • FIG. 17 is a block diagram illustrating a structure of a timing generator in a conventional SRAM.
  • FIG. 18 is a block diagram illustrating a structure of an address buffer in the conventional SRAM.
  • FIG. 19 is a block diagram illustrating a structure of a row decoder in the conventional SRAM.
  • FIG. 20 shows a relation between the power supply voltage and the pulse width of an output signal in a delay circuit.
  • FIGS. 21A-21R are timing charts representing an operation of the conventional SRAM in the case that the supply voltage is high.
  • FIGS. 22A-22R are timing charts representing an operation of the conventional SRAM in the case that the supply voltage is low.
  • FIG. 1 is a block diagram illustrating an entire structure of an SRAM according to the first embodiment of the present invention.
  • the SRAM includes a memory cell array MCA, a row address buffer RAB, a column address buffer CAB, a row decoder RD, a column decoder CD, a timing generator TG, a multiplexer MP, a sense amplifier SA, an output data buffer OB, an input data buffer IB, a read/write control circuit RWC, a chip select control circuit CSC, and ATD buffers ATD1-ATD5.
  • Memory cell array MCA includes a plurality of memory cells (not shown) arranged in rows and columns, a plurality of word lines (not shown) arranged in rows, and a plurality of bit line pairs (not shown) arranged in columns.
  • Chip select control circuit CSC generates an internal chip select signal int. /CS in response to an external chip select signal /CS.
  • Row address buffer RAB outputs a row address signal RAD in response to an external address signal EAD.
  • Column address buffer CAB outputs a column address signal CAD in response to external address signal EAD.
  • Row decoder RD selectively activates a word line in response to row address signal RAD.
  • Column decoder CD outputs a multiplexer select signal MPS in response to column address signal CAD.
  • Read/write control circuit RWC generates a read/write enable signal RWE in response to an external read/write enable signal Ext. RWE.
  • ATD buffers ATD1-ATD5 respectively generate one-shot pulse signals LATD1-LATD5 according to change of row address signal RAD, internal chip select signal int. /CS, column address signal CAD, read/write enable signal RWE, and a data input signal Din.
  • Timing generator TG generates a word line activation signal WLE, a multiplexer activation signal MPE, and a sense amplifier activation signal SAE from pulse signals LATD1-LATD5.
  • Multiplexer MP connects or does not connect a bit line pair and a data input/output line pair IO corresponding to each other in response to multiplexer select signal MPS from column decoder CD.
  • Sense amplifier SA amplifies a data signal of a memory cell array read onto data input/output line pair IO when sense amplifier activation signal SAE is active.
  • Output data buffer OB amplifies an output from sense amplifier SA to output it as a data output signal Dout to any external unit of the SRAM when read/write enable signal RWE is active.
  • FIG. 2 is a block diagram illustrating structures of memory cell array MCA and multiplexer MP shown in FIG. 1 in detail.
  • Memory cell array MCA is shown having the structure formed of two rows and two columns for purpose of simplicity.
  • memory cell array MCA includes memory cells MC1-MC4, word lines WL1 and WL2, and bit line pairs BL1 and BL1, and BL2 and /BL2.
  • Memory cells MC1 and MC2 are provided for word line WL1, and memory cells MC3 and MC4 are provided for word line WL2.
  • Memory cells MC1 and MC3 are provided for bit line pair BL1 and /BL1, and memory cells MC2 and MC4 are provided for bit line pair BL2 and /BL2.
  • N channel MOS transistors RN1-RN4 each as the load of the bit line are respectively connected to the ends of bit lines BL1, /BL1, BL2, and /BL2 on one side.
  • N channel MOS transistors RN1-RN4 are diode-connected, and connected between power supply node VDD and corresponding bit lines BL1, /BL1, BL2, and /BL2.
  • Multiplexer MP includes N channel MOS transistors TFG1 and TFG2.
  • N channel MOS transistors TFG1 and TFG2 respectively constitute transfer gates, and are turned on/off in response to multiplexer activation signals MPE1 and MPE2 from the column decoder. According to ON/OFF of the transfer gates, corresponding bit line pairs BL1 and /BL1 as well as BL2 and /BL2 are connected or not connected to input/output line pair IO.
  • FIGS. 3 and 4 are circuit diagrams illustrating examples of the structures of memory cells MC1-MC4 shown in FIG. 2.
  • FIG. 3 illustrates a memory cell of high-resistance load type
  • FIG. 4 illustrates a memory cell of CMOS type.
  • the high-resistance load type memory cell includes N channel driver transistors NT1a and NT1b, N channel access transistors NT2a and NT2b, and load resistors ra and rb.
  • N channel driver transistors NT1a and NT1b respectively have drains connected to storage nodes N5a and N5b, gates connected to drains of the other transistors, and sources connected to ground nodes Vss.
  • N channel access transistors NT2a and NT2b respectively have one of the drain and source connected to storage nodes N5a and N5b, the other thereof connected to bit lines BL and /BL, and gates connected to word line WL.
  • One end of each of load resistors ra and rb is connected to power supply node VDD, and the other thereof is connected to each of storage nodes N5a and N5b.
  • the CMOS type memory cell is provided with P channel MOS transistors PT1a and PT1b in place of load resistors ra and rb shown in FIG. 3.
  • P channel MOS transistors PT1a and PT1b respectively have drains connected to storage nodes N5a and N5b, gates connected to drains of the other transistors, and sources connected to power supply node VDD.
  • Reading of data from memory cell MC1 shown in FIG. 2 is now described.
  • column address signal CAD corresponding to a column in which memory cell MC1 is placed is supplied to column decoder CD
  • multiplexer activation signal MPE1 corresponding to bit line pair BL1 and /BL1 to which memory cell MC1 is connected attains the select level (H level)
  • the other multiplexer activation signal MPE2 goes to the non-select level (L level). Consequently, only the transfer gate TFG1 connected to bit line pair BL1 and /BL1 is rendered conductive to connect only the selected bit line pair BL1 and /BL1 and to disconnect the other bit line pair BL2 and /BL2 to and from input/output line pair IO.
  • storage node N5a of memory cell MC1 is at H level, and storage node N5b is at L level.
  • one driver transistor NT1a of memory cell MC1 is in a non-conducting state, and the other driver transistor NT1b is in a conducting state. Since word line WL1 is at H level, access transistors NT2a and NT2b of memory cell MC1 are both in the conducting state. Accordingly, direct current is generated in a path extending from power supply node VDD through bit line load RN2, bit line /BL1, access transistor NT2b and driver transistor NT1b to ground node Vss.
  • bit line BL1 (power supply voltage VDD)-(threshold voltage Vth).
  • potential on bit line /BL1 where the direct current flows is divided by the resistor due to the conducting resistance of driver transistor NT1b, access transistor NT2b, and bit line load RN2.
  • bit line amplitude ⁇ V is generated on input/output line pair IO via transfer gate TFG1 at time t3, amplified by sense amplifier SA at time t4, and further amplified by output data buffer OB at time t5 to be read as data output signal Dout supplied to any external unit.
  • control by read/write control circuit RWC prevents input data buffer IB from driving input/output line pair 10.
  • input data buffer IB is used to set one of input/output line pair IO to L level, to set the other to H level, to set one bit line BL1 to L level, and to set the other bit line /BL1 to H level to perform the writing operation.
  • FIG. 6 is a block diagram illustrating a structure of timing generator TG shown in FIG. 1.
  • timing generator TG includes an NOR circuit NR1, multiple stages of delay circuits RDLs, inverters IV1-IV3, and NAND circuits ND1 and ND2.
  • NOR circuit NR1 outputs NOR of pulse signals LATD1-LATD5 supplied from ATD buffers ATD1-ATD5.
  • Each of the multiple stages of delay circuits RDLs delays the trailing edge of the input pulse signal to supply the delayed one to delay circuit RDL in the next stage.
  • Delay circuit RDL in the first stage receives an output from NOR circuit NR1.
  • Inverter IV1 inverts an output from delay circuit RDL in the last stage, or the voltage on node Nd.
  • NAND circuit ND1 outputs NAND of an output from inverter IV1 and an output from the first stage delay circuit RDL.
  • Inverter IV2 inverts the output from NAND circuit ND1 to output the inverted one as word line activation signal WLE.
  • NAND circuit ND2 outputs NAND of the read/write enable signal RWE, the output from inverter IV1, and an output from delay circuit RDL in the second stage.
  • Inverter IV3 inverts an output from NAND circuit ND2 to supply the inverted one as sense amplifier activation signal SAE.
  • Word line activation signal WLE output from the timing generator having the structure described above surely falls and maintains its state during the period in which a pulse signal output from the first stage delay circuit RDL falls and maintains its state.
  • sense amplifier activation signal SAE surely falls and maintains its state during the period in which a pulse signal output from the second stage delay circuit RDL falls and maintains its state.
  • FIG. 7 is a block diagram illustrating a structure of row address buffer RAB shown in FIG. 1.
  • row address buffer RAB includes an NOR circuit NR10, a delay circuit BDL, and inverters IV11-IV14.
  • NOR circuit NR10 outputs NOR of external address signal EAD and internal chip select signal int. /CS.
  • Inverter IV10 inverts an output from NOR circuit NR10.
  • Delay circuit BDL delays both of the leading edge and the trailing edge of a signal output from inverter IV10 by a prescribed time to output it.
  • Inverter IV11 inverts the output from delay circuit BDL.
  • Inverter IV12 inverts an output from inverter IV11.
  • Inverter IV13 inverts an output from inverter IV12 to output the inverted one as row address signal /RAD.
  • Inverter IV14 inverts an output from inverter IV11 to output the inverted one as row address signal RAD.
  • Output atd from inverter IV10 is supplied to ATD buffer ATD1.
  • one-shot pulse signal LATD1 is output from ATD buffer ATD1 as shown in FIGS. 8A and 8B.
  • the delay time generated by delay circuit BDL in row address buffer RAB having the structure described above is adjusted such that row address signal RAD changes in the period in which word line activation signal WLE shown in FIG. 6 certainly falls and maintains its state.
  • Column address buffer CAB shown in FIG. 1 has a structure similar to that of row address buffer RAB shown in FIG. 7.
  • outputs from inverters IV13 and IV14 are respectively column address signals /CAD and CAD.
  • Output atd from inverter IV10 is supplied to ATD buffer ATD3.
  • FIG. 9 is a block diagram illustrating a structure of row decoder RD shown in FIG. 1.
  • row decoder RD includes NAND circuits ND21-ND24 and ND31-ND34, and inverters IV21-IV24 and IV31-IV34.
  • NAND circuits ND21-ND24 respectively output NAND of bit signals /A1 and /A2, A1 and /A2, /A1 and A2, and A1 and A2 of row address signals RAD and /RAD.
  • Inverters IV21-IV24 respectively invert outputs from NAND circuits ND21-ND24.
  • NAND circuits ND31-ND34 output NAND of outputs from corresponding inverters IV21-IV24, word line activation signal WLE, and an inverted signal iCS of internal chip select signal int. /CS.
  • Inverters IV31-IV34 respectively invert outputs from NAND circuits ND31-ND34. Outputs from inverters IV31-IV34 are respectively connected to word lines WL1-WL4.
  • FIG. 10 is a block diagram illustrating a structure of column decoder CD shown in FIG. 1.
  • inputs of NAND circuits ND21-ND24 shown in FIG. 9 are replaced respectively with bit signals /A1 and /A2, A1 and /A2, /A1 and A2, and A1 and A2 of column address signals CAD and /CAD, and word line activation signal WLE supplied to NAND circuits ND31-ND34 is replaced with multiplexer select signal MPS.
  • outputs from inverters IV31-IV34 are respectively multiplexer activation signals MPE1-MPE4.
  • the pulse width of an output signal from delay circuit RDL is not so large and the pulse width of word line activation signal WLE is within the range of an address cycle as shown in FIGS. 21A-21R. Therefore, even if skew occurs between row address signals, a word line corresponding to a skew address does not rise since word line activation signal WLE is at L level.
  • FIGS. 11A-11S an operation for reduced supply voltage is described.
  • one-shot pulse signal LATD1 is generated by ATD buffer ATD1.
  • LATD1 In response to pulse signal LATD1, LATD1 is supplied to delay circuit RDL in the first stage in timing generator TG, and the trailing edge of the pulse signal is delayed.
  • the reduced supply voltage increases the width of the pulse signal output from delay circuit RDL in each stage, so that output node Nd from delay circuit RDL in the last stage always has L level.
  • word line activation signal WLE always has L level during a period (the period from time t1 to t2) in which node Nb falls.
  • bit signals A1 and A2 (A1 and A2 are at L level) of row address signal RAD corresponding to a word line to be selected (word line WL1) are supplied from row address buffer RAB to row decoder RD.
  • bit signals A1 and A2 of row address signal RAD as represented by FIGS. 11A-11S, the skew causes node N3 to rise at an instant.
  • word line activation signal WLE is at L level, so that word line WL3 is never activated.
  • Bit signals A1 and A2 of row address signal RAD change during the period in which word line activation signal WLE is at L level. Therefore, even if skew occurs, a non-selected word line is never activated.
  • word line activation signal WLE is surely at L level during a prescribed period, and in this period, bit signals A1 and A2 of row address signal RAD change. Consequently, even if skew is generated between bit signals A1 and A2 of row address signal RAD, a non-selected word line is never activated. In addition, charging and discharging current that is wastefully used can be reduced. This effect can be obtained for the higher supply voltage as well as for the lower supply voltage. Further, word line activation signal WLE determines rising of the word line to eliminate a difference of access time caused depending on an input address.
  • An output from delay circuit RDL in the first stage is shown as an input to NAND circuit ND1 in this embodiment.
  • the output may be any from delay circuit RDL in any stage other than the first stage. This arrangement allows the period in which word line activation signal WLE is at L level to be adjusted to a prescribed time.
  • row address buffer RAB and row decoder RD are herein described, the description is similarly applied to column address buffer CAB and column decoder CD.
  • row address signal RAD output from row address buffer RAB shown in FIG. 7 is fixed at H level when internal chip select signal int. /CS is inactive. In this case, if internal chip select signal int. /CS is rendered active, a word line which should not be selected could be activated to cause erroneous writing.
  • the second embodiment is devised to solve this problem.
  • FIG. 12 is a block diagram illustrating an entire structure of an SRAM according to the second embodiment.
  • the SRAM includes a chip select control circuit CSC1 in place of chip select control circuit CSC, and includes a read/write control circuit RWC1 in place of read/write control circuit RWC.
  • Chip select control circuit CSC1 generates internal chip select signal int. /CS and delay chip select signal DCS in response to chip select signal /CS.
  • Read/write control circuit RWC1 generates delay read/write enable signal DRWE in response to external read/write enable signal Ext. RWE.
  • Row decoder RD and column decoder CD are activated in response to delay chip select signal DCS
  • read/write control circuit RWC1, row address buffer RAB, and column address buffer CAB are activated in response to internal chip select signal int. /CS.
  • FIG. 13 is a block diagram illustrating a structure of chip select control circuit CSC1 shown in FIG. 12.
  • chip select control circuit CSC1 includes inverters IV51-IV57, a delay circuit BDL11, and an NAND circuit ND51.
  • Inverter IV51 inverts chip select signal /CS.
  • Inverter IV52 inverts an output from inverter IV51.
  • Inverter IV53 inverts an output from inverter IV52.
  • Delay circuit BDL11 delays the leading edge and the trailing edge of an output from inverter IV53 by a prescribed time to output the delayed one.
  • NAND circuit ND51 outputs NAND of the output from delay circuit BDL11 and the output from inverter IV53.
  • Inverter IV54 inverts an output from NAND circuit ND51 and outputs the inverted one as delay chip select signal DCS.
  • the delay time in delay circuit BDL11 is adjusted to allow delay chip select signal DCS to change in the period in which word line activation signal WLE is at L level.
  • Inverter IV55 inverts the output from inverter IV53 and outputs the inverted one as internal chip select signal int. /CS.
  • Inverter IV56 inverts an output from inverter IV55.
  • Inverter IV57 inverts an output from inverter IV56 and outputs the inverted one as internal chip select signal iCS. Internal chip select signal iCS is supplied to ATD buffer ATD2.
  • FIG. 14 is a block diagram illustrating a structure of read/write control circuit RWC1 shown in FIG. 12.
  • read/write control circuit RWC1 includes NAND circuits ND61 and ND62, inverters IV61-63, and a delay circuit BDL21.
  • NAND circuit ND61 outputs NAND of external read/write enable signal Ext. RWE and internal chip select signal int. /CS.
  • Inverter IV61 inverts the output from NAND circuit ND61.
  • Inverter IV62 inverts the output from inverter IV61.
  • Delay circuit BDL21 delays the leading edge and the trailing edge of an output from inverter IV62 by a prescribed time to output the delayed one.
  • NAND circuit ND62 outputs NAND of the output from delay circuit BDL21 and an output from inverter IV62.
  • Inverter IV63 inverts the output from NAND circuit ND62 and outputs the inverted one as delay read/write enable signal DRWE.
  • the delay time in delay circuit BDL21 is adjusted such that delay read/write enable signal DRWE changes in the period in which word line activation signal WLE is at L level.
  • row address buffer RAB is activated, and word line activation signal WLE which is at L level for a prescribed period is supplied from timing generator TG to row decoder RD in a manner similar to that of the first embodiment.
  • delay chip select signal DCS changes its level from L to H.
  • delay chip select signal DCS is supplied to row decoder RD and column decoder CD.
  • delay read/write enable signal DRWE changes its state from L level to H level. Accordingly, data output buffer OB and data input buffer IB are activated.
  • word line activation signal WLE changes its state from L level to H level.
  • a word line is selected in a manner similar to that of the first embodiment. In this case, any word line other than the selected word line WL1 is never activated.
  • delay circuits BDL11 and BDL21 are provided in chip select control circuit CSC1 and read/write control circuit RWC1, and accordingly delay chip select signal DCS and delay read/write enable signal DRWE change in the period in which word line activation signal WLE is at L level. Therefore, a word line which should not be selected is never activated and erroneous writing is prevented. Further, charging and discharging current which is wastefully consumed can be reduced since a word line corresponding to a non-selected address is not activated.
  • inverters IV71 and IV72 shown in FIG. 16 may be used.
  • an output signal from inverter IV72 is delay chip select signal DCS1 or delay read/write enable signal DRWE1.

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US20080013385A1 (en) * 2006-06-28 2008-01-17 Hisatada Miyatake Asynchronous semiconductor memory
US9678154B2 (en) 2014-10-30 2017-06-13 Qualcomm Incorporated Circuit techniques for efficient scan hold path design
TWI685853B (zh) * 2018-06-04 2020-02-21 美商美光科技公司 用於集中式命令位址輸入緩衝器之系統及方法

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GB2343278A (en) * 1998-10-28 2000-05-03 Hyundai Electronics Ind Address strobe signal generator for memory device
US6356502B1 (en) 1998-10-28 2002-03-12 Hyundai Electronics Industries Co., Ltd. Address strobe signal generator for memory device
GB2343278B (en) * 1998-10-28 2003-06-18 Hyundai Electronics Ind Apparatus for decoding signals
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US9678154B2 (en) 2014-10-30 2017-06-13 Qualcomm Incorporated Circuit techniques for efficient scan hold path design
TWI685853B (zh) * 2018-06-04 2020-02-21 美商美光科技公司 用於集中式命令位址輸入緩衝器之系統及方法

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