US5309393A - Semiconductor memory device - Google Patents
Semiconductor memory device Download PDFInfo
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- US5309393A US5309393A US07/774,834 US77483491A US5309393A US 5309393 A US5309393 A US 5309393A US 77483491 A US77483491 A US 77483491A US 5309393 A US5309393 A US 5309393A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
Definitions
- the present invention relates to a semiconductor memory device and more particularly to a device having a large capacity and low cost.
- a dynamic random-access memory is a typical semiconductor memory device of a large capacity.
- a typical DRAM has been arranged, in such a way that as shown in FIG. 2, a plurality of word-lines W are disposed in parallel with one another, a plurality of data-lines D are disposed so as to cross the wordlines W, and a memory cell MC is disposed at each of desired positions at intersections of the word-lines W and the data-lines D.
- One memory cell MC is generally made up of one storage capacitor Cs as storage means, and one MOS (metal oxide semiconductor) transistor M as a switch. Information of one binary digit (one bit) is stored in the form of the quantity of electric charge accumulated in the storage capacitor Cs.
- each of the memory cells is connected to the associated dataline by the MOS transistor M, and a signal is transferred between the storage capacitor in each of the memory cells and the data-line, through the MOS transistor M.
- the reading operation is carried out in the following manner.
- the data-line is precharged at a certain potential in a stand-by state, and the data-line is turned to a floating state, then the MOS transistor M is turned ON by the word-line.
- the electric charge accumulated in the storage capacitor Cs is re-allocated between a stray capacitance Cd of the data-line D and the capacitor Cs so that the potential at the data-line D is changed. It is judged whether the level of the signal on the data-line is "1" or "0" by sense means (not shown) connected to the data-line D.
- means for restoring the information destructively read out from the memory cell is provided in the data-line to make the potential level of the data-line go to a high potential corresponding to "1" or a low potential corresponding to "0" in accordance with the judgement result by the sense means.
- the sense means may perform the function of that restore means substitutely in some cases.
- the writing operation can be performed in the same manner as in the restore operation by making the data-line go to the high or low potential by the store means.
- an area required for a silicon substrate to provide a storage capacitor may be substantially equal to an area of a connection hole between a MOS transistor and a storage electrode so that an area of the memory cell becomes small.
- a one-transistor/ one-capacitor type memory cell requires a connection hole between the cell and a data-line, a gate portion of a MOS transistor, a connection hole between the MOS transistor and the storage node and a space for electrically insulating this memory cell from other memory cells. Therefore, the area of the memory cell depends on such elements.
- the feature of the present invention is that a plurality of memory cells each having a switch and storage means for information are connected in a cascade manner. That is, a plurality of storage means are connected in a cascade manner by a plurality of switches controlled by plural word-lines parallel with one another.
- a group of cascade-connected memory cells is referred to as simply "a memory cell block", when applicable.
- One end of the group of cascade-connected memory cells constitutes a terminal for transferring therethrough a signal to or from the external side of the memory cell block and is connected to the data-line.
- the operation of reading or writing information from or to storage means in the memory cell block is performed by controlling a plurality of switches in the memory cell block by a plurality of word-lines, through the connection terminal to externals of the memory cell block.
- connection terminals are provided for transferring therethrough signals to or from the externals corresponding to each memory cell block including therein the plural storage means, the number of connection holes to the data-lines is decreased and the area thereof is reduced.
- the switches are disposed between the storage means so that the electrical isolation between the storage means is effected by the switches. Therefore, an isolation region between the storage means is provided only for every memory cell block and thus the area is reduced compared with the large area required for the prior art memory.
- the present invention it is possible to reduce the chip area of the semi-conductor memory device to realize high integration. Moreover, in order to realize the devices of the present invention, no complicated manufacturing process needs to be introduced. Thus, the invented devices can be realized by using the same manufacturing process as in the prior art semiconductor memory.
- FIG. 1 is a conceptual diagram of the present invention showing the arrangement of the memory cell block of the invention
- FIG. 2 is a conceptual diagram for explaining the prior art
- FIG. 3 is a block diagram showing the arrangement of an embodiment of the present invention employing a data-line
- FIG. 4 is a block diagram showing the arrangement of a further embodiment of the present invention employing a data-line
- FIG. 5 is a block diagram showing the arrangement of an even further embodiment of the present invention in which in addition to the data-line, a global data-line is provided;
- FIG. 6 is a block diagram showing one example of the arrangement of memories according to the present invention employing a register circuit
- FIG. 7 is a block diagram showing a further example of the arrangement of the memories according to the present invention.
- FIG. 8 is a circuit diagram showing one example of the arrangement of logical circuits used in the memory arrangement shown in FIG. 7;
- FIG. 9 is a circuit diagram showing a further example of the arrangement of logical circuits used in the memory arrangement shown in FIG. 7;
- FIG. 10 is a block diagram showing an even further example of the arrangement of the memory associating with other peripheral circuits
- FIG. 11 is a circuit diagram showing a memory cell block of an embodiment employing a one-transistor/ one-capacitor type memory cell;
- FIG. 12A is a cross sectional view illustrating one example of the arrangement of the memory cell block shown in FIG. 11;
- FIG. 12B is a plan view of the same example shown in FIG. 11;
- FIG. 12C is an equivalent circuit diagram showing the same example shown in FIG. 11;
- FIG. 13A is a cross sectional view showing a further example of the arrangement of the memory cell block
- FIG. 13B is a plan view of the same example shown in FIG. 13A;
- FIG. 14A is a cross sectional view showing an even further example of the arrangement of the memory cell block
- FIG. 14B is a plan view of the same example shown in FIG. 14A;
- FIG. 15 is a circuit diagram showing the arrangement of an embodiment in which a dummy data-line is shared among a plurality of sense means;
- FIG. 16A is a waveform diagram showing operation of the circuit shown in FIG. 15 in reading out information
- FIG. 16B is a waveform diagram showing operation of the same circuit of FIG. 15 in transferring data
- FIG. 16C is a waveform diagram showing operation of the same circuit of FIG. 15 in restoring the data
- FIG. 17 is a block diagram showing the arrangement of another embodiment in which sense means is shared among a plurality of data-lines;
- FIG. 18A is a waveform diagram showing operation of the same circuit of FIG. 17 in reading out data
- FIG. 18B is a waveform diagram showing operation of the same circuit of FIG. 17 in restoring the data
- FIG. 19 is a circuit diagram showing the arrangement of still another embodiment employing the folded data-line arrangement
- FIG. 20A is a cross sectional view showing the arrangement of the memory cell block in FIG. 19;
- FIG. 20B is a plan view of the same arrangement of FIG. 19;
- FIG. 21A is a waveform diagram showing operation of the same circuit of FIG. 19 in reading out data
- FIG. 21B is a waveform diagram showing operation of the circuit of FIG. 19 in restoring the data
- FIG. 22 is a circuit diagram showing an example of the arrangement of a dummy cell block of the invention.
- FIG. 23 is a block diagram showing the arrangement of a chip of the invention.
- FIG. 24A is a waveform diagram showing operation of the chip arrangement of FIG. 23 in reading out data
- FIG. 24B is a waveform diagram showing operation of the same chip arrangement of FIG. 23 in refreshing the data
- FIG. 24C is a waveform diagram showing operation of the same chip arrangement of FIG. 23 in storing the data.
- FIG. 25 is a block diagram showing an example in which the present invention is applied to a sound recording-reproducing apparatus.
- MC a memory cell
- MCB a memory cell block
- MCA a memory cell array
- CD a global data-line
- DCB a dummy cell block
- DCA a dummy cell array
- FIG. 1 is a conceptual diagram for illustrating the principle of the present invention through a memory cell block of the invention which is arranged by connecting in a cascade manner a plurality of memory cells made up of switches and storage means. More specifically, there shows an arrangement of a memory cell block MCB for storing information including a plurality of switches SW 1 , SW 2 , . . . , SW n (in this embodiment, the number thereof is n) connected in series and controlled via word-lines W 1 , W 2 , . . . , W n arranged parallel with one another, and a plurality of storage means MM 1 , MM 2 , . . . , MM n connected to the associated connections.
- a memory cell block MCB for storing information including a plurality of switches SW 1 , SW 2 , . . . , SW n (in this embodiment, the number thereof is n) connected in series and controlled via word-lines W 1 , W 2 , .
- the basic operation to read and write of this arrangement is as follows. For example, the operation of reading an information from the k-th storage means MMk connected to the k-th connection (where 1 ⁇ k ⁇ n) counted from the end terminal NB is performed in such a way that all of the switches SW 1 , SW 2 , . . . , and SW k connected between the terminal NB and the storage means MMk are turned on by the control signals via the wordlines W 1 , W 2 , . . . , and W k , respectively, and then the information stored in the means MM k is read out to the terminal NB.
- the operation of writing information to the k-th storage means MM k is performed in such a way that all of the switches SW 1 , SW 2 , . . . , and SW k are turned on and the information received through the terminal NB is written to the means MM k .
- the reading or writing operation with the storage means within the memory cell block MCB will be described in more detail later.
- the terminal NB is a terminal for transferring therethrough the information between the memory cell block MCB and the external side thereof. Therefore, sense means and information write means are connected to the terminal NB.
- the memory cell block may be arranged in such a way that a data-line D perpendicular to each of the word-lines W is provided and the above-mentioned terminal NB is connected to the data-line.
- a plurality of memory cell blocks (MCB 1 , MCB 2 etc.) each being shown in FIG. 1 may be connected to the data-line D.
- a signal which is read out from one of the storage means MM (any one from MM 1 , MM 2 , . . . , and MM n ) in the memory cell block MCB to the terminal NB is transferred to a terminal ND through the data-line D and is then sensed by the sense means.
- a signal which is inputted to the terminal ND by the write means is transferred to the terminal NB through the data-line D to be stored in the storage means MM in the memory cell block MCB.
- the reading or writing of the information from or to the storage means in the memory cell block is performed through at least one switch connected between the storage means and the terminal NB. Therefore, in the term of operating speed or the like, there is a limitation in the number of memory cells which are connected in the memory cell block in a cascade manner.
- FIG. 3 by connecting the plurality of memory cell blocks to the data-line instead of increasing the number of memory cells in a memory cell block, it is possible to increase the number of memory cells per sense means or write means. Therefore, it is correspondingly possible to reduce an occupation area factor of the sense means and write means.
- FIG. 4 is a block diagram showing the arrangement of a further embodiment employing the data-line.
- the present embodiment is arranged in such a way that two memory cell blocks MCB 1 and MCB 2 are disposed so as to confront with each other thereby to share a connection of the data-line D.
- the number of connections between the memory cell blocks and the data-line is reduced to one half of that of the embodiment shown in FIG. 3, and therefore, a required area for the connections can be further reduced.
- the memory cell block MCB is constructed by the n memory cells which are connected in a cascade manner, and only one terminal NB for transferring therethrough a signal between the memory cell block MCB and the externals is provided in the memory cell block.
- the electrical isolation between the storage means MM can be performed by the cascade-connected switches SW.
- FIG. 5 is a block diagram showing the arrangement of an even further embodiment of the present invention.
- the present embodiment is an example wherein the data-line in the embodiment shown in FIG. 4 is provided in two hierarchies. More specifically, the present embodiment is arranged in such a way that the data-line D shown in FIG. 4 to which a plurality of memory cell blocks MCB are connected is divided into plural lines, e.g., D 1 and D 2 , a global data-line CD is provided in parallel with those data-lines D 1 and D 2 , and a signal is transferred between the data-lines and the global data-line through the signal transfer means DS which is capable of being operated selectively.
- the problems of layout and area increase may be solved by making the global data-line CD in another conductive layer from the layer of forming the word-lines W and the data-lines D 1 and D 2 .
- a signal which is read out from the memory cell block MCB to the data-line D 1 or D 2 is transferred to a terminal NCD through signal transfer means DS and the global data-line CD and is then sensed by the sense means. Moreover, the operation of writing an information to the memory cell block MCB is performed in such a way that a signal which is inputted to the terminal NCD by the write means is transferred to the data-line D 1 or D 2 through the global data-line CD and the signal transfer means DS.
- the stray capacitance thereof is small. Moreover, since only small number of signal transfer means corresponding to the division number of datalines are connected to the global data-line CD, the stray capacitance thereof is also small. Therefore, since the stray capacitance existing in the signal transferring path from the memory cell block MCB to the terminal NCD is correspondingly small, the signal is transferred at a high speed. Further, if the signal transfer means DS is operated in the reading operation in a state in which the input impedance viewed the data-line D 1 or D 2 is high, the stray capacitance of the global data-line CD is electrically separated from that of the data-line D 1 or D 2 .
- this signal transfer means is applied to the memory cell in which the storage means is constructed by a capacitor, the memory cell is free from the stray capacitance of the global data-line, and the magnitude of the signal voltage read to the data-line can be increased all the more. Moreover, by providing the signal transfer means DS with the function of amplifying a signal it is possible to operate the memory cell block at a high speed.
- the memory cell block may be arranged in such a way that the signal transfer means DS for separating the stray capacitances of the data-line D from the memory cell block MCB in the reading operation as described above, is inserted between the terminal NB of the memory cell block MCB and the data-line D, and that the signal is transferred through such signal transfer means.
- the number of signal transfer means is increased corresponding to that of memory cell blocks MCB, in this case, it is also possible to increase the magnitude of the signal voltage read out to the terminal NB of the memory cell block MCB.
- FIG.6 is a block diagram showing an arrangement of a memory cell array based on the embodiment shown in FIG. 3. That is, the present embodiment is arranged in such a way that the memory array is provided with a plurality of data-lines D (D 1 , D 2 etc.), and sense means SA (SA 1 , SA 2 etc.) and register circuits DR (DR 1 , DR 2 etc.) are connected to each of the plural data-lines D which is connected with a plurality (e.g., number of p) of memory cell blocks MCB (MCB 11 , MCB 12 etc.) shown in FIG. 1.
- the register circuit DR serves to temporarily save the information of the storage means MM in the memory cell block MCB, in the reading or writing operation.
- an address buffer, a decoder, a driver, an input-output line, a read-write controller and the like are omitted.
- Reading or writing of the storage means MMk in a certain memory cell block MCB, e.g., MCB 11 is performed in the following manner.
- a switch SW 1 in the memory cell block MCB 11 is turned on by a word-line W 1 to read out the information from the storage means MM 1 and the information thus read is sensed by the sense means SA.
- the sensed result is stored in the register circuit DR 1 .
- the switches SW 1 and SW 2 are turned ON to read out the information from the storage means MM 2 and the information thus read is sensed by the sense means SA 1 .
- the sensed result is stored in the register circuit DR 1 .
- the information is shifted from the storage means to the register circuit DR 1 .
- the switches SW 1 , SW 2 , . . . , and SW k are turned on to read out the information from the storage means MM k and the information thus read is sensed by the sense means SA 1 .
- the sensed result is outputted to the externals of the chip thereby to allow the information of the storage means MM k in a certain memory cell block MCB to be read out.
- the sensed result is restored in the storage means MM k through the data-line.
- the writing operation is, when the switches SW 1 , SW 2 , . . .
- SW k are in an on state, performed by writing the information inputted from the external side of the chip to the storage means MM k through the data-line.
- the switch SW k is turned off and the information stored in the register circuit DR 1 is made to return to the memory cell block MCB 11 from which the information was read out.
- the information in the storage means MM k-1 is read out from the register circuit DR 1 to the data-line D 1 to be written to the storage means MM k-1 in the memory cell block MCB 11 through the switches SW 1 , SW 2 , . . . , and SW k-1 .
- the switch SW k-1 is turned off, and when the switches SW 1 , SW 2 , . . . , and SW k-2 are in an on state, the information of the storage means MM k-2 is read out from the register circuit DR 1 to be restored in the storage means MM k-2 in the memory cell block MCB 11 .
- the restoring operation is performed up to the storage means MM 1 .
- the switch SW 1 is turned off, and the reading or writing operation is then completed.
- the memory cell block MCB 11 is selected, the memory cell block MCB 12 and the like connected to the same word-line are also simultaneously selected so that the same operation as in the above description is performed.
- the selection of those memory cell blocks is performed in the same manner as in the prior art DRAM by the Y decoder (not shown). Further, the selection of the memory cell blocks (MCB 11 , MCB 12 etc.) along the data-line can be performed by the selection of the wordline.
- the register circuit DR has only to have the storage capacity smaller than that of the memory cell block MCB by the information content of one storage means MM.
- reading and writing of the k-th storage means in the memory cell block has been described. However, as apparent from the description, reading and writing are also carried out up to the (k-1)-th storage means to perform reading and writing of the k-th storage means. Then, such a method may be taken that all the storage means in the memory cell block, i.e., the storage means from first to n-th are always read out and that only the information of the desired storage means is outputted to the external side of the chip. In this method, the writing operation is performed in such a way that in the restore after the reading operation, instead of the information read out, the write information inputted from the externals of the chip is written in the desired storage means.
- the description was given in such a way that the signal from the storage means is sensed by the sense means and the sensed result is outputted.
- such a method may be taken that after the information in the memory cell block is stored in the register circuit DR, the information is outputted from the register circuit DR to the externals of the chip.
- the writing operation can be performed.
- the storage capacity of the register circuit DR is set to the same storage capacity as that of one memory cell block MCB.
- the register circuit DR is arranged in such a way that the random access can be performed, out of the information stored in the register circuit DR, arbitrary information can be read out or written. Moreover, in the case where certain information or a series of information is intended to be repeatedly read out, the information can be read out from the register circuit DR. Thus, it is possible to perform the reading operation at a high speed and with low power consumption.
- the information data in one memory cell block are considered to be individually independent from one another and thus the description has been given with respect to the method of inputting or outputting arbitrary information.
- a plurality of information data in one memory cell block are read out in a time series manner, it is also possible to output the information of one memory cell block to the externals of the chip in the form of one group of serial information.
- the writing operation it is also possible to write such information in the form of one group of serial information.
- the control of inputting or outputting of the information becomes simply.
- the register circuit DR As described hereinabove, by using the register circuit DR, it is possible to carry out the reading and writing operations, without erasing the information stored in the storage means in the memory cell block.
- the register circuit DR is additionally required.
- the register circuit DR since the register circuit DR is shared among a great number of memory cell blocks MCB, the number thereof may be small. As described above, since by providing the memory cell block MCB, the number of connections between the memory cell blocks and the data-line is decreased and the area is reduced, the chip area of the whole memory is decreased
- FIG. 7 is a block diagram showing the arrangement of another embodiment of the present invention.
- the present embodiment is arranged in such a way that the register circuit DR in the embodiment shown in FIG. 6 is removed and its function is performed by a memory cell block MCB in a memory cell array.
- the memory cell block MCB has the same arrangement as that shown in FIG. 1 and is made up of n switches SW and n storage means MM.
- the memory cell blocks MCB are disposed in a matrix arrangement and are connected to a data-line D to which sense means SA is connected.
- the memory cell blocks MCB are provided every data-line so that the number thereof exceeds needed for the storage capacity by one.
- FIG. 7 shows a specific case where the storage capacity per data-line is (n ⁇ p) bits.
- the number of memory cell blocks MCB per data-line is p.
- the number thereof is (p+1). Therefore, one of the plurality of memory cell blocks MCB connected to one data-line D is in a state in which there is no information (referred to as "the empty state", when applicable).
- Sense means SA is connected to the data-line D. Moreover, there is provided an input-output line IO to which a read-write controller RWC is connected and which is connected to the data-line D by a switch SWY controlled by a Y decoder YDEC.
- the reading operation in the present embodiment is performed in such a way that the information is read out from n storage means MM in a certain memory cell block MCB and the information thus read is restored in the memory cell block MCB in the empty state.
- the information read out from a certain memory cell block MCB is temporarily stored in the register circuit DR and that information is restored in the original memory cell block MCB, whereas in the present embodiment, such information is shifted to the subsequent memory cell blocks one after another. Therefore, the register circuit DR shown in the embodiment of FIG. 6 becomes unnecessary.
- the information is stored in the subsequent memory cell block MCB every reading operation. That is, position of the information is moved in the memory cell array every reading operation.
- the operation of reading the information in the memory cell block MCB is started from the storage means MM near the terminal for transferring therethrough a signal to or from the dataline D, while the writing operation (the operation of restoring the information in the subsequent memory cell block) is started from the storage means MM far the terminal for transferring therethrough a signal to or from the data-line D. That is, by restoring the information, the order of the information data in the memory cell block are reversed. Therefore, it is necessary to remember which memory cell block certain information is stored and which order the information data are stored.
- an X decoder for selecting a memory cell block and a word-line in the memory cell block is made up of sub-X decoders SXD (SXD 1 , SXD 2 etc.) and X address control means XSC (XSC 1 , XSC 2 etc.).
- the sub-X decoder SXD is a decoder for selecting and controlling one of the word-lines W 1 , W 2 , . . . , and W n in the memory cell block MCB.
- the X address control means XSC is used for selecting a memory cell block MCB.
- the X address control means XSC is made up of an X address register XR for storing an X address of the corresponding memory cell block, an X address comparator for judging whether or not an address inputted to an X address buffer XB coincides with an address stored in the X address register XR, and flag registers FR 1 and FR 2 for storing respective flags F 1 and F 2 .
- the flag F 1 is used to indicate whether or not the memory cell block is in the empty state. In the present embodiment, when the memory cell block is in the empty state, "1" is designated thereto.
- the flag F 2 is used to indicate the order of the information data in the memory cell block.
- an X address which is inputted to the X address buffer XB from the external side of the chip is transferred to each of the X address control means XSC. That X address is compared with an address stored in the X address register XR by the X address comparator XC.
- the sub-X decoder SXD corresponding to the X address control means XSC is selected.
- the word-line W is controlled by the sub-X decoder SXD so that the reading operation of the corresponding memory cell block MCB is performed.
- the sub-X decoder SXD is selected and the writing of the information to the corresponding memory cell block MCB is performed.
- the description will be given on the assumption that the memory cell block MCB 11 is in the empty state and the reading of the information from the memory cell block MCB 21 is performed.
- the word-line of the memory cell block MCB 21 is controlled by the sub-X decoder SXD 2 so that the switch SW 1 in the memory cell block MCB 21 is turned on and the information is read out from the storage means MM 1 in the memory cell block MCB 21 to the data-line D.
- the signal corresponding to that information is sensed by the sense means SA 1 so that the information is discriminated.
- the word-line of the memory cell block MCB 11 is controlled by the sub-X decoder SXD 1 so that all the switches SW in the memory cell block MCB 11 are turned on and the discriminated result is stored in the storage means MM n in the memory cell block MCB 11 .
- the switch SW n in the memory cell block MCB 11 is turned off and the switch SW 2 in the memory cell block MCB 21 is turned on, so that the information is read out from the storage means MM 2 in the memory cell block MCB 21 to the data-line D 1 , and the information thus read is sensed by the sense means SA 1 to be stored in the storage means MM n-1 in the memory cell block MCB 11 .
- the information stored in the storage means in MCB 21 is shifted to the storage means in MCB 11 . Since the memory cell block MCB 1 is in the empty state and the memory cell block MCB 11 is not in the empty state through the above operation, the flag F 1 in the X address control means XSC 2 goes to "1" and the flag F 1 in the X address control means XSC 1 goes to "0". Moreover, the address inputted to the X address buffer XB is, as the X address of the memory cell block MCB 11 , stored in the X address register XR in the X address control means XSC 1 .
- the information of the flag F 2 in the X address control means XSC 2 is inverted to be stored in the flag register FR 2 in the X address control means XSC 1 .
- Outputting of the information to the externals of the chip is performed in such a way that when the information read out from the desired storage means in the memory cell block MCB 21 is discriminated by the sense means SA, the switch SWY is selected by the Y decoder YDEC and the information is transferred to the input-output line IO to be an output data Dout by the read-write controller RWC.
- Inputting of the input data Din is performed in such a way that when the information is restored in the memory cell block MCB 11 , the switch SWY is selected so that the input data Din is transferred from the input-output line IO to the dataline D 1 through the read-write controller RWC.
- the position of the desired information in the memory cell block MCB i.e., the number of the storage means from the terminal with the data-line where that information stored is selected by the address information inputted to the Y decoder YDEC and the flag F 2 in the X address control means XSC.
- the register circuit DR which was used in the embodiment shown in FIG. 6 becomes unnecessary, and therefore, no writing and reading operation of the register circuit DR are required.
- the cycle time required for reading or writing of the memory cell blocks MCB becomes short.
- the power consumption becomes small.
- the additional number of memory cell blocks MCB is required for a data-line by one and the X address control means XSC for comparing the X addresses with each other is also required.
- the register circuit DR of FIG. 6 since the register circuit DR of FIG. 6 is not required, the arrangement of the present embodiment may be small in area as compared with the arrangement of FIG. 6 in some cases.
- FIG. 8 is a circuit diagram showing an example of the arrangement of the X address comparator XC. It is assumed that p is 2 to the m-th power. Then, in order to select the p memory cell blocks MCB, the address information of m bits is required. It is also assumed that the address outputted from the X address buffer XB is expressed in the form of m bits of B m B m-1 . . . B 1 and the address stored in the X address register XR is expressed in the form of m bits of A m A m-1 . . . A 1 .
- the X address comparator XC used in the embodiment shown in FIG. 7 outputs "1" when A m , A m-1 , . . .
- FIG. 8 there is shown an example which is made up of m exclusive OR circuits (EOR gates) and a multiple input NOR gate.
- the EOR gate is a comparator having two inputs and is a circuit which outputs "0" when two inputs coincide with each other and outputs "1" when the two inputs are different from each other.
- a m and B m , A m-1 and B m-1 , . . . , and A 1 and B 1 are compared with one another by the m EOR gates, respectively. Only when the outputs of the m EOR gates and the flag F 1 are "0", the output of the multiple input NOR gate goes to "0".
- the above logic is realized.
- FIG. 9 is a circuit diagram showing another example of the arrangement of the X address comparator XC.
- the example shown in FIG. 8 is arranged in such a way that by using the m EOR gates, the comparison operations are simultaneously performed with respect to the m bits.
- the present example is, however, arranged in such a way that one EOR gate is multiply used in a time division manner and m digits are compared with one another in a time series manner.
- an RS type flip-flop circuit FF By employing an RS type flip-flop circuit FF, the EOR gate is multiply used in a time division manner.
- the operation thereof is as follows. First, in the stand-by state, the input terminals A and B of the EOR gate are maintained at the same level ("0" or “1"), the reset terminal R of the flip-flop circuit FF is set to "0", and the set terminal S of the flip-flop circuit FF is set to "1", whereby the output terminal Q of the flip-flop circuit FF is set to "1” and Q is set to "0". Subsequently, after the clock terminal T is set to "0" and the set terminal S is set to "0", the X addresses are transferred from the X address buffer XB and the X address register XR to the X address comparator XC in a time series manner by one bit by one bit.
- a m and B m are inputted to the input terminals A and B of the EOR gate, respectively to be judged whether or not the two bits coincide with each other, and the comparison result is inputted to the reset terminal R of the flip-flop circuit FF.
- the clock terminal T is set to "1", so that the information at the reset terminal R is fetched to the flip-flop circuit FF. Since when A m and B m coincide with each other, the reset terminal R goes to "0", the output terminals Q and Q of FF are kept being “1” and "0", respectively. On the other hand, when A m and B m are different from each other, R goes to "1", and Q and Q are inverted to be “0” and "1", respectively.
- the clock terminal T is returned to "0"
- a m-1 and B m-1 are respectively inputted to the input terminals A and B of the EOR gate, and the terminal T is again set to "1", thereby to fetch the information at the reset terminal R to the flip-flop circuit FF.
- the output terminals Q and Q go to "0" and "1", respectively.
- the EOR gate may be only one so that the area can be reduced.
- FIG. 8 shows the arrangement in which the comparisons of m bits are performed in parallel
- FIG. 9 shows the arrangement in which the comparisons of m bits are performed in a time series manner.
- the intermediate arrangement may be taken in some cases.
- such an arrangement may be taken that the parallel comparisons of 2 bits are performed in a time series manner.
- Such an arrangement can be realized in such a way that in the arrangement of FIG. 9, the logical sum of the outputs of two EOR gates is applied to the reset terminal R of the flip-flop circuit FF.
- FIG. 10 is a block diagram showing the arrangement of still another embodiment in which in the same manner as in the embodiment shown in FIG. 7, the operation is performed by shifting the information among the memory cell blocks.
- the X addresses which are inputted from the externals to the respective memory cell blocks MCB are distributed among the X address registers XR in the X address control means XSC to be stored therein.
- the 10 is arranged in such a way that the relationship between the address inputted from the externals (referred to as “the external address”, when applicable) and the address representing the position of the memory cell block in the chip (referred to as “the internal address”, when applicable) is stored and such relationships are assembled in one memory to be stored therein in the form of an address translation table.
- an X decoder XDEC instead of the provision of the plurality of X address control circuits XSC, there is provided an X decoder XDEC, a memory XTM for the address translation table, and a register XSR for storing therein the X address of the memory cell block in the empty state.
- an X address buffer XB To the memory XTM is connected an X address buffer XB.
- the memory cell blocks MCB are disposed in a matrix arrangement, (p+1) memory cell blocks are connected to one data-line D, and correspondingly, (p+1) sub-X decoders SXD are disposed.
- the data-line D is provided with the sense means SA which is connected to the input-output line IO having the read-write controller RWC through the switch SWY controlled by the Y decoder YDEC.
- the operation will be performed in the following manner.
- the external address inputted to the X address buffer XB is transferred to the memory XTM and by using that external address as an address of XTM, the internal address (designated XAR) stored in XTM is read out.
- XAR is transferred to the X decoder XDEC to select the sub-X decoder SXD for controlling the reading operation.
- the internal address (designated XAW) indicating the empty block is transferred from the register XSR to XDEC to select the sub-X decoder SXD for controlling the writing operation.
- the sub-X decoder SXD 2 is selected by XAR and the sub-X decoder SXD 1 is selected by XAW.
- the information is shifted among the memory cell blocks by the sub-X decoders SXD 2 and SXD 1 .
- the flag F 2 in FIG. 7, i.e., the order of the information data in the memory cell blocks are also stored in the memory XTM and such information is read out together with XAR.
- the flag F 2 is transferred to the Y-decoder YDEC and the switch SWY is correspondingly controlled thereby to transfer the signal to or from the input-output line IO.
- the X address XAR indicating the memory cell block to be read out becomes the X address of the subsequent memory cell block in the empty state, it is stored in the register XSR. Moreover, the internal address corresponding to the external address inputted from the address buffer XB is changed from XAR to the X address XAW indicating the memory cell block to which the information is to be shifted. Then, as the internal address corresponding to the external address inputted from the address buffer XB, XAW is stored in the memory XTM. Further, since the order of the information data in the memory cell blocks is reversed, F 2 is inverted to be stored together with XAW in XTM.
- the memory XTM for storing therein the address translation table is read out. Since the operation of a large number of X address comparators XC may be performed by one operation of reading the memory XTM, the power consumption is greatly reduced.
- a switch and storage means are constructed by a MOS transistor and a storage capacitor, respectively.
- FIG. 11 is a circuit diagram showing the arrangement of a concrete example of a memory cell array in which the memory cell blocks MCB (MCB 11 , MCB 21 etc.) are disposed in a matrix arrangement.
- Each memory cell block MCB is arranged in such a way that each of n-channel MOS transistors M (M 1 , M 2 etc.) and each of storage capacitors Cs (Cs 1 , Cs 2 etc.) are used as a switch and storage means, respectively, as shown in FIG. 11. That is, the memory cell blocks are arranged by connecting n cells of the one-transistor/one-capacitor type memory cells to one another in a cascade manner.
- each of the plural data-lines D (D 1 , D 2 etc.) are connected plural memory cell blocks MCB.
- a plurality of word-lines W (W 1 , W 2 etc.) for controlling the memory cell blocks MCB are disposed so as to cross the data lines.
- the reading operation of the memory cell blocks MCB will be performed in the following manner.
- the word-line W 1 is made to be at a high potential to turn the MOS transistor M 1 on.
- the electric charge accumulated in the storage capacitor Cs 1 is redistributed between Cs 1 and the stray capacitance CD of the data-line D so that the potential of the data-line D is charged. It is judged by the sense means (not shown) connected to the data-line D whether the signal on the data-line is "1" or "0".
- the word-line W 2 is also made to be at a high potential to turn both the MOS transistors M 1 and M 2 on. Then, the electric charge accumulated in the storage capacitor Cs 2 is re-distributed among Cs 1 , Cs 2 and the stray capacitance CD of the data-line D so that the potential of the data-line D is charged. The signal on the data-line D is discriminated by the sense means.
- the word-lines are made to be at a high potential in the order of W 1 , W 2 , . . .
- the writing operation of the memory cell block MCB will be performed in the following manner. First, all the word-lines W 1 , W 2 , . . . , and W n are made to be at a high potential to turn on all the MOS transistor M 1 , M 2 , . . . , and M n . Under this condition, the data-line D is made to be at a high or low potential in accordance with the information to be stored. By making the wordline W n to be at a low potential, the MOS transistor M n is turned off so that the electric charge corresponding to the potential of the data-line D is stored in the storage capacitor Cs n .
- the data-line D is made to be at a potential corresponding to desired information, and the word-line W n-1 is made to be at a low potential to turn the MOS transistor M n-1 off so that the electric Charge corresponding to the potential of the data-line D is stored in the storage capacitor Cs n-1 .
- the data-line D is made to be at a high or low potential in accordance with the desired information, and in the reverse manner to the reading operation, the word-lines are made to be at a low potential in the order of W n , W n-1 , . . .
- the reading operation and the writing operation have been individually described, in the practical use, by combining both the operations with each other, the operation is performed so as not to erase any information.
- the read out information is temporarily stored in the register circuit DR provided outside the memory cell array MCA and is then restored in the memory cell block which has been read out.
- the additional number of the memory cell blocks are set for a data-line by one. Then, after the information is read out from a certain memory cell block, the information thus read is stored in the block in the empty state.
- the refresh operation is required and thus the actual operation is performed by combining the reading operation and the writing operation with each other.
- the refresh operation is performed with the memory cell being treated as unit.
- the refresh operation is performed with the memory cell block being treated as unit. Therefore, while the cycle time required for one refresh operation is long, the number of refresh cycles is reduced to a number fractionized by n as compared with the prior art DRAM. Therefore, when the control of the refresh operation is performed from the externals of the chip, the number thereof may be reduced. Moreover, the time which is accessible from the externals can be made to be continuously long.
- the MOS transistors connected to the data-line per memory cell block MCB is M 1 , i.e., the number thereof is one.
- the number of MOS transistors per memory cell is one, whereas in the present embodiment, the number thereof is one for n memory cells and therefore it is reduced to one fractionized by n.
- the number of diffusion regions connected to the data-line is small, so that the data-line capacitance CD can be reduced.
- the signal produced on the data-line is a potential change due to the re-distribution of the electric charge stored in the storage capacitor Cs, and therefore, the smaller the data-line capacitance CD is, the larger the magnitude of the signal is.
- the storage capacitor connected to the MOS transistor forming a signal transfer path in the memory cell block MCB is coupled in parallel to the data-line capacitance C D .
- the soft-error of the data-line mode is a phenomenon wherein the electric charge which is generated in the substrate by the application of the ⁇ -particles is collected in the data-line which is in the floating state in the reading operation so that the information is judged by mistake. Since the number of diffusion layers connected to the data-line is small, the possibility of the electric charge generated in the substrate being collected in the data-line is small and the probability of an error in judgement occurring is small.
- FIGS. 12A, 12B and 12C are respectively a cross sectional view, a plan view and an equivalent circuit diagram showing an example of the arrangement of the memory cell block MCB.
- two memory cell blocks MCB in the plan view, four MCB) each being made up of three transistors M and three storage capacitors Cs.
- the cross sectional view is taken on the line A--A' of the plan View.
- the reference symbol W designates the word-line
- the reference symbol SN designates the storage electrode
- the reference symbol PL designates the plate electrode
- the reference symbol D designates the data-line.
- These elements are, for example, made up of a first polysilicon layer, a second polysilicon layer, a third polysilicon layer and aluminium, respectively.
- the reference symbol CI designates an insulating film for a capacitor which is, for example, made of silicon oxide (SiO 2 ) or a multiple layer film consisting of silicon oxide and silicon nitride (Si 3 N 4 ).
- An n-channel MOS transistor M is arranged in such a way as to have the intersecting portion between the word-line W and an active area as its gate.
- the storage capacitor Cs is made up of the insulating film CI for a capacitor, the storage node SN and the plate electrode PL between which CI is sandwiched.
- the n + region as the drain of the MOS transistor M and the data-line D are connected to each other through the connection hole DCNT.
- the n + region as the source of the MOS transistor M and the storage node SN are connected to each other through the connection hole MCNT.
- This memory cell block can be manufactured by the same process as that of the prior art STC cell.
- connection hole DCNT is shared between two memory cell blocks.
- the number of the connection holes DCNT may be reduced to one n-th as compared with the prior art DRAM cell.
- the separation between the adjacent memory cells is performed by the MOS transistor acting as the switch. From those reasons, with the memory cell block in which n memory cells are connected to one another in a cascade manner, the length along the data-line is short and the area is small as compared with the case where the n memory cells of the prior art DRAM are arranged. Moreover, the length of the data-line is short and the stray capacitance of the data-line is decreased.
- FIGS. 13A and 13B are respectively a cross sectional view and a plan view showing a further example of the arrangement of the memory cell block MCB.
- the memory cell in which the data-line is shielded by the plate electrode is proposed in an article of IEEE Trans. Electron Devices, Vol. 37, pp. 737-743, 1990.
- such memory cells are connected to one another in a cascade manner to construct the memory cell block MCB.
- the cross sectional view shown in FIG. 13A is taken on the line A--A' of the plan view shown in FIG. 13B.
- the equivalent circuit is the same as that shown in FIG. 12C.
- the word-line W and the data-line D are made of polysilicon, silicide or the like.
- the storage electrode SN is made of silicide or the like.
- the insulating film CI for a capacitor is made of high melting point metal oxide such as SiO 2 , Si 3 N 4 or Ta 2 O 5 , or a multiple layer film thereof
- the plate electrode PL is made of metal such as polysilicon or tungsten.
- the vertical relationship between the plate electrode PL and the storage node SN, and the data-line D is reversed to that of FIG. 12.
- the data-line D is shielded by the plate electrode PL and the capacitance between the data-lines is small. Therefore, when the signal is read out from the storage capacitor to the data-line, the signal voltage read to the data-line is free from the influence of the potential change of the adjacent data-line. That is, the influence of the data-line interference noise becomes small. As a result, it is possible to perform the reading operation at a high signal to noise ratio.
- FIGS. 14A and 14B are respectively a cross sectional view and a plan view showing an even further example of the arrangement of the memory cell block MCB.
- the memory cell employing a crown-shaped stacked capacitor is proposed in an article of IEEE Trans. Electron Devices, Vol. 38, pp. 255-261, 1991. In the present example, such memory cells are connected to one another in a cascade manner to construct the memory cell block MCB.
- the cross sectional view shown in FIG. 14A is taken on the line A--A' of the plan view shown in FIG. 14B.
- the equivalent circuit is the same as that shown in FIG. 12C.
- the word-line W and the data-line D are made of polysilicon, silicide or the like.
- the storage node SN is made of polysilicon or the like.
- the insulating film CI for a capacitor can be made of high melting point metal oxide such as SiO 2 , Si 3 N 4 , Ta 2 O 5 , or a multiple layer film thereof.
- the plate electrode PL is made of metal such as polysilicon or tungsten.
- the area of the memory cell becomes small.
- the plane area of the storage capacitor also becomes small.
- the crown-shaped stacked capacitor is employed, the side area of the storage node is large and it is possible to keep a sufficient capacitance value.
- FIG. 12 through FIG. 14 there are shown examples in each of which the storage capacitor Cs in the memory cell block MCB is constructed by the stacked capacitor which is stacked on the word-line W.
- the arrangement of the memory cell block of the present invention is not limited thereto or thereby.
- the trench capacitor is employed as the storage capacitor Cs which is discussed as the storage capacitor of DRAM in an article of 1982 IEDM Digest of Technical Papers, pp. 806-808, it is possible to construct the memory cell block MCB of the present invention.
- FIG. 15 is a block diagram showing the arrangement of a concrete embodiment which is arranged on the basis of the embodiment shown in FIG. 6.
- the operation for the memory cell block MCB in the memory cell array MCA is performed.
- a dummy data-line DD is provided so that the signal provided on the data-lines D is sensed using a difference between that signal and the reference signal provided on the dummy data-line DD.
- the dummy data-line DD producing the reference signal is shared among a plurality of data-lines thereby to reduce the area.
- a plurality of memory cell blocks MCB are connected to each of the q data-lines D 1 , D 2 , . . . , and D q , and one dummy data-line DD to construct the memory cell block MCB shown in FIG. 11.
- the memory cell array MCA connected to the dummy data-line DD is referred to as "the dummy cell block DCB".
- the dummy cell block DCB has the same arrangement as that of the memory cell block MCB, and the storage capacitor DCs has the same capacitance value as that of the storage capacitor Cs in MCB.
- the dummy cell blocks DCB are made to correspond to the memory cell blocks MCB of each of the data-lines and are controlled by the same word-line.
- the dummy data-line requires a substantially intermediate potential between the potential provided on the data-line when the electric charge corresponding to the information of "1" stored in the storage capacitor Cs in the memory cell block MCB is read out, and the potential provided on the data-line in the case of the presence of such information of "0". This is realized in such a way that the intermediate potential (Vcc/2) between the potential Vcc of "1” and the potential 0V of "0" is stored in advance in the storage capacitor DCs.
- the data-lines D are connected to the input terminals NDS (NDS 1 etc.) of the sense means SA (SA 1 etc.) by the signal transfer means DS (DS 1 etc.).
- the load circuit LD (LD 1 etc.) are connected to the terminal NDS.
- the output terminal of the sense means SA is connected to the terminal NDS by the switch SWW.
- the dummy data-line DD is connected to the input terminal DNDS of the reference signal which is common to a plurality of sense means SA by the signal transfer means DDS.
- the load circuit DLD In the same manner as in the terminal NDS, to the terminal DNDS is connected the load circuit DLD.
- the terminals NSA and NSA of the sense means SA are connected to the register circuits DR (DR 1 etc.) by the switch SWR and are connected to a pair of input-output lines IO and IO by the switch SWY.
- the register circuits DR have the same storage capacity of n bits as that of the memory cell block MCB, constructed by four-transistor memory cells RC (RC 1 through RC n ) and are controlled by the selection lines WR (WR 1 through WR n ).
- the data-lines D and the dummy data-line DD have the precharge circuits PD (PD 1 etc.) and DPD connected thereto, respectively and are precharged to the precharge voltage Vp.
- FIGS. 16A, 16B and 16C By using the operation waveforms shown in FIGS. 16A, 16B and 16C, the operation of the circuit shown in FIG. 15 will be described in the following manner. First, the description will be given with respect to the operation of reading out the information from the memory cell block MCB on referring to FIG. 16A.
- the electric charge accumulated in the storage capacitor Cs in the memory cell block MCB is read out to the data-line D in a time series manner.
- FIG. 16A there is shown the case where "1" and “0” are alternately stored in the storage capacitors in such a way that "1", "0", . . . , and "0" are respectively stored in Cs 1 , Cs 2 , . . . , and Cs n .
- the precharge voltage Vp is set to Vcc/2.
- each of the control pulses ⁇ R and ⁇ W is made to be at a low potential, the signal transfer means DS and DDS are turned OFF, the capacitor of the sense means SA is electrically separated from the data-line D, and the data-line D and the dummy data-line DD are precharged to the precharge voltage Vp by the precharge circuits DD and DPD.
- the control pulse ⁇ L is set to Vcc and the load circuits LD and DLD are made to be in the conduction state.
- control pulse ⁇ SAP is set to the low potential, and each of the terminals NSA and NSA in the sense means SA is precharged to Vcc, and also the control pulse ⁇ DR is set to the high potential (Vcc+ ⁇ ) to turn the switch SWR on and the register circuit DR is precharged.
- control pulse ⁇ DR is set to the low potential to turn the switch SWR OFF thereby to electrically separate the stray capacitance of the register circuit DR from the sense means SA.
- control pulse ⁇ SAP is set to Vcc, and the control terminals NSA and NSA in the sense means SA, and the data-line and the dummy data-line are made to be in the floating state.
- the word-line W 1 of one row of the memory cell blocks in the plurality rows of memory cell blocks MCB is raised to the high potential (Vcc+ ⁇ ) to turn the MOS transistor M 11 on so that the electric charge accumulated in the storage capacitor Cs 1 is read out to each of the data-lines D (D 1 , D 2 , . . . , and D q ).
- the potential change of the data-line D due to the electric charge makes the control pulse ⁇ R be Vcc and is then sensed by the signal transfer means DS to be converted into a current
- the resultant current is caused to flow from the power source voltage Vc through the load circuit LD.
- the signal transfer means DS acts as a common source amplifier having the load circuit LD as the load and at the terminal ND, the output corresponding to the potential change of the data-line D is produced.
- the output produced at the terminal NDS every data line is inputted to the sense means SA.
- the stray capacitance of the data-line D and that of the sense means SA are electrically separated from each other by the signal transfer means SD.
- the same operation as in the above case is performed, so that the electric charge is read out from the storage capacitor DCS to the dummy data-line DD.
- the voltage corresponding to the potential of the dummy data-line DD is outputted to the terminal DNDS to be inputted to each of the plurality of sense means SA in the form of a reference voltage.
- the reference voltage produced at DNDS is an intermediate voltage between the signal voltage produced at the terminal NDS when the information read out from the storage capacitor Cs in the memory cell block MCB is on the level of "1", and the signal voltage produced at the terminal NDS when such information is on the level of "0".
- control pulse ⁇ SA 1 is raised to Vcc to make the sense means SA act as a differential amplifier having the latch circuit of the PMOS transistor as the load.
- control pulse ⁇ SA 1 is reduced and the control pulse ⁇ SA 2 is raised to make the sense means SA operate as a flip-flop type differential amplifier thereby to amplify the difference between the terminals NSA and NSA up to Vcc.
- the amplified signal is not fedback to the terminals NDS and DNDS, it is possible to apply the reference signal to the plurality of sense means SA. Since the data-line D is kept being in the floating state and the potential thereof is not changed, there is no problem of the data-line interference noise due to the amplification of the signal.
- the control pulse ⁇ SA 2 is reduced, the control pulse ⁇ P is raised to Vcc and the control pulse ⁇ SAP is reduced to the low potential so that the data-line D, the dummy data-line, the sense means SA and the register circuit DR are precharged.
- the control pulse ⁇ R is reduced to the low potential and the signal transfer means DS and DDS are turned off.
- the control pulse ⁇ P is reduced to the low potential and the control pulse ⁇ SAP is raised to Vcc, in addition to the word-line W 1 , the word-line W 2 is raised to the high potential so that the electric charge accumulated in the storage capacitor Cs 2 in each of the memory cell blocks MCB is read out to each of the datalines D.
- that electric charge thus read is inputted to the sense means SA through the signal transfer means DS and the load circuit LD and the amplified information is stored in the 4 transistor memory cell RC 2 in the register circuit DR.
- the word-line is raised to the high potential one by one so that the electric charge accumulated in the storage capacitor Cs is read out to the data-line D in sequence to be inputted to the sense means SA through the signal transfer means DS and the load circuit LD and the amplified information is stored in the register circuit DR.
- the electric charge is finally read out from the storage capacitor Csn to complete the reading operation with respect to one memory cell block MCB.
- the inputting or outputting operation is performed. It is possible to randomly access to the register circuit DR.
- the description will hereinbelow be given with respect to the operation of outputting the information stored in the storage capacitor Cs 1 in the memory cell block MCB to the external side. Since that information is stored in the four-transistor memory cell RC 1 in the register circuit DR, it will be read out.
- the control pulse ⁇ SAP is raised from the low potential to Vcc, and the terminals NSA and NSA are made to be in the floating state.
- the potential of the selection-line WR 1 is raised to (Vcc+ ⁇ ) to read out the information from the four-transistor memory cell RC 1 . That is, the current is caused to flow from the terminals NSA and NSA to the four transistor memory cell RC 1 to produce a potential difference between the terminals NSA and NSA.
- the control pulse ⁇ SA 2 is raised to Vcc to make the sense means SA act as a flip-flop type differential amplifier thereby to amplify the signal corresponding to the potential difference.
- the control pulse ⁇ Y is raised to turn the switch SWY on thereby to output the information to the pair of input-output lines IO and IO in the form of a differential signal.
- the selection-line WR 1 is reduced to 0V to restore the information in the four-transistor memory cell RC 1 .
- the control pulse ⁇ Y and ⁇ SA 2 are reduced to 0V to turn the switch SWY and the sense means SA off and the control pulse ⁇ SAP is reduced to 0V to precharge both the terminals NSA and NSA.
- the information amplified by the sense means SA is rewritten as the information transferred through the pair of input-output lines IO and IO from the externals of the chip to perform the writing operation.
- FIG. 16C is a time chart showing the restore operation after "1" and "0" are alternately read out in such a way that "1", "0", . . . , and "0" are respectively read out from Cs 1 , Cs 2 , . . . , and Cs n .
- control pulse ⁇ L is reduced from Vcc to 0V to make the load circuits LD and DLD be in the non-conduction state
- control pulse ⁇ W is raised to the high potential (Vcc+ ⁇ ) to make each of the signal transfer means DS and DDS act as a switch in the on state thereby to connect the data-line D and the dummy data-line DD to the terminals NDS and DNDS, respectively.
- the control pulse ⁇ DR is kept being at the high potential (Vcc+ ⁇ ) and the switch is also kept being in the on state.
- control pulse ⁇ SAP is reduced to the low potential to precharge the terminals NSA and NSA, and the register circuit DR
- control pulse ⁇ P is reduced to the low potential
- control pulse ⁇ SAP is raised to Vcc, and the data-line D and the terminals NSA and NSA are made to be in the floating state.
- the selection-line WRn is raised to (Vcc + ⁇ ) to read out the signal from the four-transistor memory cell RCn in the register circuit DR, and the control pulse ⁇ SA 2 is raised to Vcc to amplify the signal thus read out with the sense means SA. After deciding the information, the selection-line WR n is reduced to 0V.
- the control pulse ⁇ SAW is raised to (Vcc+ ⁇ ) to turn the switch SWW on so that the output of the sense means SA which is inverting-amplified by the inverter is transferred to the memory cell block MCB through the signal transfer means DS and the data-line D, and the word-line Wn is reduced to 0V to restore 0V corresponding to the information of "0" in the storage capacitor Cs n .
- the stray capacitance of the data-line D is electrically separated from the terminal NSA by the inverter, and thus, there is no possibility that the information decided by the sense means SA is inverted
- the inverter in which its input terminal is connected to the terminal NSA and its output is open is used for balancing the stray capacitances with each other by NSA and NSA.
- control pulse ⁇ SAW is reduced to 0V to make both the terminal NDS and the data-line D be in the floating state
- control pulse ⁇ SA2 is reduced to 0V and further the control pulse SAP is reduced to 0V to precharge both the terminals NSA and NSA.
- the above writing operation is, when reading out the information from the register circuit DR, performed by electrically separating the data-line capacitance from the sense means SA. Therefore, since the potential of the data-line D does not take part in the reading of the information from the register circuit DR, there is no necessity of precharging the data-line D. Therefore, when storing "1" or "0" successively, the voltage of the data-line D may not be changed. As a result, the power consumption can be greatly reduced.
- the information is read out from the desired storage capacitor Cs to be amplified by the sense means SA and under this condition, the switch SWY is turned on to output the information to the pair of input-output lines IO and IO in the form of a differential signal, whereby the reading operation can be performed.
- the writing operation is performed in such a way that the information written from the external side of the chip to the pair of input-output lines IO and IO is replaced with the information amplified by the sense means SA by turning the switch SWY on.
- the restore operation it is possible to transfer the information between the memory cell block and the external side. In such an operation, the storage capacity of the register circuit DR may be smaller than that of the memory cell block MCB by one memory cell.
- the dummy data-line DD needs to be arranged in such a way that the noise component which is the same as on the data-line D is generated on the dummy data-line DD.
- the matching with the data-line must be maintained with respect to the electrical characteristics such as the value of the stray capacitance in such a way that when the selection-line such as the word-line is pulse-driven, the coupling noise thereof to that line is the same.
- the signal of the data-line D is applied to one sense means SA, whereas the reference signal of the dummy data-line DD is applied to the plurality of sense means SA.
- the balance may become a problem.
- the stray capacitance of the input terminal of the sense means SA is electrically separated from both the data-line D and the dummy data-line DD by the signal transfer means DS and DDS, the matching of the capacitance may be maintained between the data-line D and the dummy data-line DD.
- To the data-line D and the dummy data-line DD are respectively connected the memory cell block MCB and the dummy cell block DCB which are the same in arrangement.
- the data-line D and the dummy data-line DD are also equal in wiring length to each other. Thus, the matching can be maintained therebetween.
- the storage capacitor DCs in the dummy cell block DCB has the same capacitance value as that of the storage capacitor Cs of the memory cell block MCB and the same operation is performed in both the capacitors. Therefore, the matching can be maintained.
- the time required for the information on the high potential side to be decreased to be mistaken in judgement as the information on the low potential side, i.e., the data-holding time can be made to be long. This means that it is possible to make the time interval necessary for refreshing the memory cell block MCB long.
- FIG. 17 is a block diagram showing the arrangement of a further concrete embodiment of the present invention
- the present embodiment is an example wherein the signal transfer means DS, the load circuit LD, the sense means SA, the switches SWY and SWR, the register circuit DR and the like are shared among the plurality of data-lines D (in the figure, the number thereof is q) thereby to reduce the chip area and to relieve the layout pitch of those circuits.
- the signals which are simultaneously read out to the plurality of data-lines are switched over by the switches SWD (SWD 11 etc.) to be inputted to the respective sense means SA in a time series manner to perform the discrimination, thereby to share the sense means SA and the like.
- SWD SWD 11 etc.
- the global data-lines CD (CD 1 , CD 2 etc.) are provided in parallel to the data-lines D, the signals are transferred to or from the data-lines through the signal transfer means DS (DS 11 , DS 21 etc.), and the sense means SA and the like are shared among the plurality of memory cell arrays MCA (MCA 11 , MCA 21 etc.).
- the sense means SA and the like are shared among the plurality of data-lines D disposed in a matrix arrangement. Thus, it is possible to decrease the occupation area ratio of the sense means SA and the like.
- the q data-lines D 1 , D 2 , . . . , and D q of the memory cell array MCA are connected to the signal transfer means DS through the switch SWD.
- the precharge circuits PD (PD 11 etc.) are connected to the connection terminals between the switches SWD and the signal transfer means DS.
- the dummy cell arrays DCA (DCA 1 etc.) have the same arrangement as that of the memory cell arrays MCA and are connected to the signal transfer means DDS (DDS 1 etc.) through the switches DSWD (DSWD 1 etc.).
- the global dummy data-line DCD is provided with a plurality of dummy cell arrays DCA.
- the memory cell array MCA, the precharge circuit PD, the signal transfer means DS, the load circuit LD, the sense means SA, the switches SWW, SWY and SWR, and the register circuit DR are the same in arrangement as those in FIG. 11.
- the register circuit DR has the storage capacity of (q ⁇ n) bits and is made up of (q ⁇ n) cells of four-transistor memory cells RC.
- the control pulse ⁇ P is raised to Vcc to operate the precharge circuit PD, and all the control pulses ⁇ D 1 , ⁇ D 2 , . . .
- the data line W 1 of the each of the selected memory cell blocks is raised to the high potential (Vcc+ ⁇ ) so that the electric charge is read out from the storage capacitor Cs 1 of each memory cell block MCB to each data-line of each memory cell block.
- the control pulse ⁇ D 1 is kept being in the high potential thereby to transfer the signal produced on the data-line D 1 of each memory cell block to the signal transfer means DS.
- This signal is converted into a current by raising the control pulse ⁇ R to Vcc, so that the current is caused to flow from the load circuit LD through the global data-line CD to input the voltage of the global data-line CD to the sense means SA.
- the common reference signal is applied from the dummy data-line DCA 1 to a plurality of sense means SA.
- the sense means SA performs the differential amplification and the resultant output is transferred to the register circuit DR to be stored therein.
- control pulse ⁇ D 1 is reduced to 0V and the connection terminal between the switch SWD and the signal transfer means DS is precharged by the precharge circuit PD
- the control pulse ⁇ D 2 is raised to (Vcc+ ⁇ ) to switch over the switch SWD, so that the same operation is performed.
- such an operation is repeatedly performed up to the control pulse ⁇ D q , and the signals read out to the respective data-lines D 1 , D 2 , . . . , and D q of each memory cell block are amplified all to be stored in the register circuit DR.
- to operate the precharge circuit PD thereby to precharge the individual data-lines D 1 , D 2 , . . . , and D q .
- the word-line W 2 is also raised to (Vcc+ ⁇ ) to read out the information to the associated data-lines, and the control pulses ⁇ D 1 , ⁇ D 2 , . . . , and ⁇ D q are raised to (Vcc+ ⁇ ) in this order so that the signals are sensed by the sense means SA to be stored in the register circuits DR. Such an operation is repeatedly performed up to the word-line Wn.
- the information which was read out from the memory cell blocks MCB in a manner as described above is accessed to the register circuit DR thereby to perform the reading or writing operation.
- the restore operation is performed in the reverse order of the reading operation as shown in the waveforms of FIG. 18B. That is, the control pulses ⁇ P and ⁇ D 1 , ⁇ D 2 , . . . , and ⁇ D q-1 are reduced to 0V and the control pulse ⁇ W is raised to (Vcc+ ⁇ ). With all the word-lines W 1 , W 2 , . . . , and W n being raised, the control pulses ⁇ D q , ⁇ D q-1 , . . .
- the above-mentioned operation is an operation wherein the information is read out from the q memory cell blocks MCB per global data-line to the register circuit DR to transfer the signal to or from the external side thereby to restore the information in the q memory cell blocks MCB.
- another operation as described in the embodiment shown in FIG. 6, such an operation may be available that the information which was finally read out from the storage capacitor Csn in each memory cell block is not stored in the register circuit DR but is restored in the original memory cell block MCB.
- the storage capacity of the register circuit DR may be ⁇ q ⁇ (n-1) ⁇ , so that it is possible to miniaturize the resister circuit DR.
- FIG. 19 is a circuit diagram showing the arrangement of an even further concrete embodiment of the present invention.
- the present embodiment is arranged in such a way that the signal read out from the memory cell block MCB is amplified by the differential amplifier.
- the data-line is constructed in the folded data-line arrangement with respect to one pair of data-lines in the memory cell array.
- the MOS transistors M (MR 11 , M L11 etc.) and the Storage capacitors Cs (Cs R11 , Cs L11 etc.) are used as the switches and the storage means, respectively to construct the memory cell blocks MCB (MCB R and MCB L ) which are connected to the pair of data-lines D and D.
- connection hole to D is provided opposite to a connection hole to D so as not to read out the electric charge from two storage capacitors Cs to D and D simultaneously.
- the connection holes to the data-lines are shared between two memory cell blocks to reduce the area, and therefore, MCB R having the connection hole to the data-line line D provided on the side of the differential amplifier SA, and MCB L having the connection hole to the data-line D provided opposite thereto are alternately disposed.
- two transistors M 12 and M 02 MR 12 , MR 02 , or M L12 , M L02
- W 2 WR 2 and W L2
- the register circuit DR is storage means which is capable of storing therein 3 bits per pair of data-lines and is made up of four-transistor memory cells RC (RC 1 etc.).
- FIGS. 20A and 20B are respectively a cross sectional view and a plan view showing an example of the arrangement of the memory cell block MCB.
- the cross sectional view is taken on the line A--A' of the plan view.
- the reference symbol W designates the word-line
- the reference symbol SN designates the storage electrode
- the reference symbol PL designates the plate electrode
- the reference symbol D designates the data-line.
- the description will hereinbelow be given with respect to the reading operation on referring to the operation waveforms of FIG. 21A.
- the description will be given with a specific case where the information is read out from a certain memory cell block MCB R .
- the description will be given with the case where the precharge voltage Vp of the data-line is set to Vcc/2 and the reading operation is performed by using that voltage as a reference voltage.
- the information is read out from the storage capacitor C SR11 .
- the signal ⁇ P is reduced to 0V by making the pair of data-lines D and D across which the precharge voltage Vp are developed by the precharge circuit DC be in a floating state.
- the switch SWR is turned off to electrically separate the stray capacitance of the register circuit DR from the differential amplifier SA.
- the word-line WR1 is raised to the high potential (Vcc+ ⁇ ) to turn the MOS transistor M R11 on so that the electric charge accumulated in the storage capacitor CSR 11 is read out to the data-line D.
- the waveforms of the pair of data-lines D and D in FIG. 21A show the case where the information stored in the storage capacitor CSR 11 in the form of electric charge is at the high potential.
- the signal ⁇ SA is raised to Vcc and the signal ⁇ SA is reduced to 0V to operate the differential amplifier SA so that the signal voltage on the data-line D is sensed to be amplified.
- the switch SWR is turned ON to raise the Selection-line W R1 of the four-transistor memory cell RC 1 to (Vcc+ ⁇ ) to store the information in the four-transistor memory cell RC 1 and then the selection-line W R1 is reduced to 0V.
- the word-line W R1 is reduced to the low potential 0V to turn the MOS transistor M R11 off.
- the information is read out from the storage capacitor C SR01 in similar manner.
- the word-line W R3 is raised to the high potential (Vcc+ ⁇ ) to read out the electric charge accumulated in the storage capacitor C SR01 to the data-line D.
- the differential amplifier SA is operated to amplify the signal voltage on the data-line D and the resultant information is stored in the four-transistor memory cell RC 2 in the register circuit DR.
- the signals ⁇ SA and ⁇ SA are made to return to Vp and the signal ⁇ P is raised to Vcc to precharge the pair of data-lines D and D of the storage capacitor C SR01 to the precharge voltage Vp.
- the word-line W R3 being at the high potential (Vcc+ ⁇ )
- the word-line W R2 is also raised to the high potential (V cc + ⁇ ) to read out the electric charge accumulated in the storage capacitor C sR02 to the data-line D.
- the electric charge accumulated in the storage capacitor C SR12 is re-distributed between the storage capacitors C SR11 and C SR12 to be held as it is.
- the signal read out from the storage capacitors C SR02 to the data line D is sensed by the differential amplifier SA to be stored in the 4 transistor memory cell RC 3 , the pair of data-lines D and D, and the storage capacitors C SR01 and C SR02 are precharged by the precharge circuit PC.
- the word-line W R1 is also raised with the word line W R3 being at the high potential (Vcc+ ⁇ ) to read out the electric charge accumulated in the storage capacitors C SR11 and C SR12 to the data-line D.
- the resultant signal is sensed to be amplified by the differential amplifier SA.
- the differential amplifier SA all the information which is stored in the four storage capacitors C SR in the memory cell block M CBk is read out.
- the switch SWY is turned on thereby to output the information to the pair of input-output lines and IO in the form of a differential signal.
- the information which was read out from the memory cell block MCB R in a manner as described above is restored in the reverse order of the reading operation.
- the word-line W R1 is reduced, so that the information read out from the storage capacitor Cs R12 is stored in both the storage capacitors Cs R12 and Cs R11 .
- the switch SWM is turned OFF to electrically separate the capacitances of the pair of data-lines D and D from the differential amplifier SA.
- the selection-line W R3 is raised to (Vcc+ ⁇ ) to read out the information stored in the four-transistor memory cell RC 3 .
- the information thus read out is amplified by the differential amplifier SA.
- the switch SWM is turned on to store the amplified information in both the storage capacitors Cs R02 and Cs R01 and the wordline W R2 is then reduced to 0V.
- the pair of data-lines D and D and the storage capacitor Cs R01 are again precharged
- the switch SWM is turned off to read out the information which was read out from the storage capacitor Cs R01 from the four-transistor memory cell RC 2 in the register circuit DR to be restored, and the wordline W R3 is then reduced to 0V.
- the word-line W R1 is selected so that the information stored in the four-transistor memory cell RC 1 in the register circuit DR is rewritten to the storage capacitor Cs R11 .
- the restore operation is completed.
- the writing operation is performed in such a way that in the reading or restore operation, after the information of the desired storage capacitor is amplified by the differential amplifier SA, that information is restored. That is, the switch SWY is turned on to write the information from the externals of the chip which was written to the pair of input-output lines IO and IO to the differential amplifier SA, thus completing the writing operation.
- the memory cell block MCB has the arrangement in which two of the one-transistor/one-capacitor type memory cells used in the prior art DRAM are connected in series to each other and the two memory cells are further combined therewith. As a result, the number of connection holes to the data-line is reduced one half. Thus, it is possible to decrease the area of the memory cell. Since with the one-transistor/one-capacitor type memory cell, the destructive reading is performed, the operations for the memory cell block MCB are performed in a time series manner, and the information is prevented from being erased by means of the register circuit. In addition, the folded data-line arrangement in which a high signal-to-noise ratio is obtained is applied to the present embodiment.
- FIG. 22 is a circuit diagram showing the arrangement of an example in which for the purpose of balancing the coupling noise to the pair of data-lines D and D or the word-line in the embodiment shown in FIG. 19, the dummy cell block DCB is connected to the pair of data-lines D and D.
- the dummy cell block DCB has the same arrangement as that of the memory cell block MCBL, and the storage capacitors DCs (DCs 01 , DCs 02 , DCs 11 , and DCs 12 ) have the same Capacitance value as that of the storage capacitor Cs L in the memory cell block MCB L and they are controlled by the dummy word-line DW (DW 1 , DW 2 , and DW 3 ).
- the present example has the same arrangement as that of FIG. 19 except that the dummy cell block DCB is connected.
- the sense means SA, the register circuit DR and the line are omitted for brevity.
- the precharge voltage Vp applied to the precharge circuit PC is Vcc/2.
- the dummy word-lines DW (DW 1 , DW 2 , and DW 3 ) are raised to the high potential to turn the precharge circuit PC on to precharge the pair of data-lines D and D, and the storage capacitor DCs of the dummy cell block DCB to Vcc/2.
- the reading operation after the dummy data-line DW is reduced to store Vcc/2 in the storage capacitor DCs, the pair of data-lines D and D are made to be in the floating state.
- the dummy word-line DW is driven in the reading operation in such a way that the dummy word-line DW 3 and the wordline W R1 or W L1 , D W2 and W R2 or W L2 , and D W1 and W R3 or W L3 are driven with the same signals, respectively.
- the MOS transistor M R11 is turned on by the word-line W R1 and at the same time the MOS transistor DM 01 in the dummy cell block DCB is turned on.
- the storage capacitor Cs in the memory cell block is connected in parallel with the stray capacitance of the data-line D by connecting the dummy cell block DCB, since the storage capacitor DCs of the dummy cell block having the same capacitance value as that of Cs is connected to the data-line D, the capacitance balance between the pair of data lines D and D is maintained. Moreover, by driving the word-line and the dummy data-line with the same signal, the noise generated from the word-line to the dummy data-line can be equalized between the pair of data-lines D and D. As a result, it is possible to eliminate the possibility of the error of judgement with respect to the information in the differential amplifier SA.
- FIG. 23 is a block diagram showing the arrangement of main portions of the chip of the semiconductor memory device according to the present invention.
- the reference symbol MA designates a memory array in which memory cell blocks for storing therein n bits are disposed in a matrix arrangement
- the reference symbol SA designates sense means
- the reference symbol DR designates a register circuit.
- the reference symbol WD designates a word-driver for driving the word-lines connected to the associated memory cell blocks, WDCG a word series clock generator for controlling the drive timing for the word-line and the like, WDEC a decoder for decoding a word series address, WAB an address buffer for holding the word series address, SAD a driver for generating a control pulse for the sense means, DRD a driver for generating a control pulse for the register circuit, RDEC a decoder for decoding an address of the register circuit, RAB an address buffer for holding an address of the register circuit, DIB an input buffer for deciding information Din inputted from the external side, DOB an output buffer for deciding information outputted to the externals, CSCG a chip select series clock generator for controlling a timing for each portion, MRCG a reading series clock generator for controlling a timing for the reading from the memory cell block, MWCG a writing series clock generator for controlling a timing of the writing to the memory cell block, DTCG a data transfer clock generator
- FIGS. 24A, 24B and 24C are views showing the operation of reading out the data to the externals of the chip, the operation of writing the data from the externals of the chip, and the refresh operation, respectively.
- the reference symbol PMR designates the reading period
- the reference symbol PDT designates the data transfer period
- the reference symbol PMW designates the period of the writing to the memory cell block.
- the chip select series clock generator is operated to start the reading period PMR.
- the address A of plural bits which have been inputted at this time are written to the address buffer WAB and are then decoded by the decoder WDEC to be transferred to the word-line WD.
- the reading series clock generator MRCG the word series clock generator WDCG, and the drivers SAD and DRD are operated.
- the information is shifted from the memory array MA to the register circuit DR by means of the sense means SA.
- the operation during this period is such an operation as shown in FIG. 16A for example.
- the data transfer clock generator DTCG is operated to start the data transfer period PDT.
- the address A of plural bits which have been inputted at this time are written to the address buffer RAB and are then decoded by the decoder RDEC.
- the write enable signal WE which is on the high level "H" is fetched to the write clock generator WCG to select the reading.
- the drivers SAD and DRD are operated.
- the information is shifted from the register circuit DR to the output buffer DOB by means of the sense means SA.
- the output buffer DOB is controlled by the data transfer clock generator DTCG so that the output data Dout are continuously outputted to the external side every fall of the data transfer signal DT.
- the operation during this period is such an operation as shown in FIG. 16B for example.
- the chip select series clock generator is operated to start the writing period PMW.
- the writing series clock generator MWCG the word series clock generator WDCG, and the drivers SAD and DRD are operated.
- the information is shifted from the register circuit DR to the memory array MA by means of the sense means.
- the operation during this period is such an operation as shown in FIG. 16C for example.
- the writing operation is performed in the similar manner to that of the reading operation. That is, the writing operation is performed in the same manner as in the reading operation, with respect to the period PMR of the reading from the memory cell block and the period PMW of the writing thereto, except for the data transfer period PDT.
- the write enable signal WE which is on the low level "L” is fetched to the write clock generator WCG to select the writing.
- the address A of plural bits which have been inputted at this time are fetched to the address buffer RAB and are then decoded by the decoder RDEC.
- the input data Din are continuously fetched to the input buffer DIB every fall of the data transfer signal DT by the data transfer clock generator DTCG.
- the drivers SAD and DRD are operated so that the information is written from the input buffer DIB to the register circuit DR by mean of the sense means SA.
- the address of the register circuit DR is inputted only when the data transfer signal DT is first fallen, so that the data of plural bits are transferred to or from the externals of the chip in sequence.
- Such an arrangement may be taken that whenever the data transfer signal DT is fallen, the address in the register circuit DR is fetched, and the information of that address is transferred to or from the external side.
- the address is fetched only when the data transfer signal DT is first fallen, the data transfer can be performed at a higher speed.
- the period PMR of the reading from the memory cell block and the period PMW of the writing thereto are continuously executed thereby to perform the refresh operation.
- the chip select signal CS is made to fall to start the period PMR of the reading from the memory cell block.
- the chip select signal CS is made to rise to execute the period PMW of the writing to the memory cell block.
- the address of the memory cell block to be refreshed is fetched when making the chip select signal CS fall.
- the address for the refresh operation may not be inputted from the external side but be generated inside the chip. Moreover, the refresh may not be controlled from the externals but be automatically controlled in the internal side of the chip. With such an operation, while the control from the externals is easy, the access time becomes long since the reading or writing operation and the refresh operation compete with each other. In such a case, if the signal for representing the completion of the period PMR of the reading from the memory cell block is outputted to the external side of the chip and in response to that signal, the data transfer signal DT is made to fall, it is possible to shorten the mean access time.
- the data transfer signal DT by using the data transfer signal DT, the signal of plural bits is continuously transferred to or from the externals of the chip.
- the data transfer is performed by accessing to the register circuit DR without accessing to the memory array MA. Therefore, it is possible to realize a high transfer rate.
- an external memory there has been used a magnetic memory such as a hard disc.
- the semiconductor memory device of the present embodiment it is possible to realize the miniaturization and the high speed operation.
- the controller for the semiconductor memory device it is possible to use a semiconductor memory controller disclosed in Japanese Patent Application (un-examined publication number) JP-A 63-127486 or JP-A 63-113653.
- FIG. 25 is a block diagram showing the arrangement of an applied example of the semiconductor memory device according to the present invention in which a sound recording-reproducing apparatus is arranged.
- the reference symbol MIC designates a microphone as voice input means
- the reference symbol SP designates a speaker as voice output means.
- the reference symbols PAMP and MAMP designate amplifiers, ADC an analog-to-digital converter, DAC a digital-to-analog converter, M a semiconductor memory device according to the present invention, and MCT a control circuit for controlling the semiconductor memory device M.
- a low-pass filter for the pass band limitation, a low-pass filter for the waveform shaping and the like are omitted for brevity.
- the sound recording operation is performed in such a way that the voice applied to the microphone MIC is amplified by the amplifier PAMP, and the resultant analog signal is converted into a digital signal by the analog-to-digital converter ADC and is then controlled to be written to the semiconductor memory device M by the controller MCT.
- the address, the clock signal and the like of the semiconductor memory device M are generated by the controller MCT.
- the reproducing operation is performed in such a way that the semiconductor memory device is controlled to read out the information stored therein b
- the controller MCT y the controller MCT, and the information thus read is converted into an analog signal by the digital-to-analog converter DAC, amplified by the amplifier MAMP and is outputted from the speaker SP.
- the input-output operation is performed one bit by one bit.
- the analog-to-digital converter ADC when the information of plural bits is outputted in parallel from the analog-to-digital converter ADC, such a procedure may be taken that by providing a parallel-to-serial converter, that information is converted into information of time series type to be transferred to the semiconductor memory device M.
- the digital-to-analog converter ADC is arranged in such a way that the information of plural bits is inputted thereto in parallel, such a procedure may be taken that by providing a serial-to-parallel converter, the output of the semiconductor memory device M is converted into information of parallel type.
- the data rate of the voice information may be 64 kbit/sec, so that the provision of the semiconductor memory device having a cycle time of 15 ⁇ s can cope therewith. Moreover, the information is data which are continuous in a time series manner. Therefore, with the semiconductor memory device used for the voice recording apparatus, the operation speed does not become a problem, but an inexpensive and large capacity one is required.
- the semiconductor memory device according to the present invention is suitable for a high signal-to-noise ratio and high integration. Thus, it is possible to decrease the chip area to reduce a bit unit price. Therefore, for such an application, the semiconductor memory device is more suitable than the prior art DRAM.
- a plurality of memory cells each of which is made up of a switch and storage means are connected in a cascade manner to construct the memory cell blocks, and the memory cell blocks are used to construct the memory cell array, whereby it is possible to reduce the number of contacts between the data-lines and the memory cells. As a result, it is possible to reduce the occupation area of the connection hole and to reduce the chip area. Moreover, the stray capacitance of the data-line becomes small. Thus, it is possible to realize the reading operation at a high signal-to-noise ratio.
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JP27039890A JP3350045B2 (ja) | 1990-10-11 | 1990-10-11 | 半導体記憶装置 |
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JP6298657B2 (ja) * | 2013-03-07 | 2018-03-20 | 株式会社半導体エネルギー研究所 | 半導体装置 |
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US5539612A (en) * | 1992-09-08 | 1996-07-23 | Texas Instruments Incorporated | Intermediate structure for forming a storage capacitor |
US5604659A (en) * | 1992-09-08 | 1997-02-18 | Texas Instruments Incorporated | Microelectronic device with centered storage capacitor cavity sized less than feature size |
US5712182A (en) * | 1992-09-08 | 1998-01-27 | Texas Instruments Incorporated | Method of forming a microelectronic device having a cavity smaller than lithographic tolerances |
US5715192A (en) * | 1992-11-26 | 1998-02-03 | Kabushiki Kaisha Toshiba | Semiconductor memory device |
US5463577A (en) * | 1993-12-28 | 1995-10-31 | Kabushiki Kaisha Toshiba | Semiconductor memory |
US5546204A (en) * | 1994-05-26 | 1996-08-13 | Honeywell Inc. | TFT matrix liquid crystal device having data source lines and drain means of etched and doped single crystal silicon |
US5541870A (en) * | 1994-10-28 | 1996-07-30 | Symetrix Corporation | Ferroelectric memory and non-volatile memory cell for same |
US5661678A (en) * | 1994-12-12 | 1997-08-26 | Kabushiki Kaisha Toshiba | Semiconductor memory device using dynamic type memory cells |
EP0866427A2 (de) | 1997-03-13 | 1998-09-23 | Francotyp-Postalia Aktiengesellschaft & Co. | Postverarbeitungssystem mit einer über Personalcomputer gesteuerten druckenden Maschinen-Basisstation |
US6456987B1 (en) | 1997-03-13 | 2002-09-24 | Francotyp-Postalia Ag & Co. | Personal computer-based mail processing system with security arrangement contained in the personal computer |
US6172918B1 (en) * | 1998-12-08 | 2001-01-09 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor memory device allowing high-speed operation of internal data buses |
US20060082478A1 (en) * | 2001-03-21 | 2006-04-20 | Brent Keeth | Memory device and method having data path with multiple prefetch I/O configurations |
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US7151707B2 (en) * | 2001-03-21 | 2006-12-19 | Micron Technology, Inc. | Memory device and method having data path with multiple prefetch I/O configurations |
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US7065546B2 (en) * | 2002-04-09 | 2006-06-20 | Sony Electronics Inc. | Method of performing quantization within a multimedia bitstream utilizing division-free instructions |
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US6982911B2 (en) * | 2004-03-18 | 2006-01-03 | Infineon Technologies Ag | Memory device with common row interface |
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US20080165559A1 (en) * | 2007-01-04 | 2008-07-10 | Samsung Electronics Co., Ltd. | Data line layout and line driving method in semiconductor memory device |
US7697314B2 (en) * | 2007-01-04 | 2010-04-13 | Samsung Electronics Co., Ltd. | Data line layout and line driving method in semiconductor memory device |
US20090327572A1 (en) * | 2008-06-30 | 2009-12-31 | In Sung Cho | Exchanging information between components coupled with an a i2c bus via separate banks |
US20090327239A1 (en) * | 2008-06-30 | 2009-12-31 | Sibeam, Inc. | Bitmap device identification in a wireless communication system |
US20090327547A1 (en) * | 2008-06-30 | 2009-12-31 | In Sung Cho | I2c bus compatible with hdmi |
US20090327544A1 (en) * | 2008-06-30 | 2009-12-31 | In Sung Cho | Dispatch capability using a single physical interface |
US20090323562A1 (en) * | 2008-06-30 | 2009-12-31 | In Sung Cho | Connection control in a wireless communication system |
US20090327467A1 (en) * | 2008-06-30 | 2009-12-31 | In Sung Cho | Device discovery in a wireless communication system |
US8116333B2 (en) * | 2008-06-30 | 2012-02-14 | Sibeam, Inc. | Connection control in a wireless communication system |
US8341271B2 (en) | 2008-06-30 | 2012-12-25 | Sibeam, Inc. | Device discovery in a wireless communication system |
US9264762B2 (en) | 2008-06-30 | 2016-02-16 | Sibeam, Inc. | Dispatch capability using a single physical interface |
US9531986B2 (en) | 2008-06-30 | 2016-12-27 | Sibeam, Inc. | Bitmap device identification in a wireless communication system |
Also Published As
Publication number | Publication date |
---|---|
KR100212096B1 (ko) | 1999-08-02 |
JPH04147490A (ja) | 1992-05-20 |
KR920008753A (ko) | 1992-05-28 |
JP3350045B2 (ja) | 2002-11-25 |
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