US20200235023A1 - Integrated circuit packaging structure and manufacturing method thereof - Google Patents

Integrated circuit packaging structure and manufacturing method thereof Download PDF

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Publication number
US20200235023A1
US20200235023A1 US16/294,951 US201916294951A US2020235023A1 US 20200235023 A1 US20200235023 A1 US 20200235023A1 US 201916294951 A US201916294951 A US 201916294951A US 2020235023 A1 US2020235023 A1 US 2020235023A1
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Prior art keywords
heat dissipation
slurry
packaging
encapsulation material
dissipation structure
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US16/294,951
Inventor
Peng Chen
Houde Zhou
Baohua Zhang
Chao Gu
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Yangtze Memory Technologies Co Ltd
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Yangtze Memory Technologies Co Ltd
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Application filed by Yangtze Memory Technologies Co Ltd filed Critical Yangtze Memory Technologies Co Ltd
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD. reassignment YANGTZE MEMORY TECHNOLOGIES CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: CHEN, PENG, GU, Chao, ZHANG, BAOHUA, ZHOU, HOUDE
Priority to US16/923,075 priority Critical patent/US11476173B2/en
Publication of US20200235023A1 publication Critical patent/US20200235023A1/en
Abandoned legal-status Critical Current

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    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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    • H01L2924/1815—Shape

Definitions

  • the present disclosure relates to an integrated circuit (IC) packaging structure and a manufacturing method thereof, and more particularly, to an IC packaging structure including a heat dissipation structure and a manufacturing method thereof.
  • IC integrated circuit
  • an integrated circuit (IC) package is a step configured to encapsulate one or more semiconductor dies of integrated circuits with a molding compound for keeping the semiconductor dies from being damaged by external factors.
  • a heat sink is disposed above the molding compound for heat dissipation.
  • the heat dissipation performance is limited because the heat transfer coefficient of the molding compound is too low, and the total size of the IC package will be increased significantly by the heat sink especially when a higher cooling capability is demanded.
  • An integrated circuit (IC) packaging structure and a manufacturing method thereof are provided in the present disclosure.
  • a trench is formed in an encapsulation material, and a heat dissipation structure is at least partially disposed in the trench for reducing the distance between the heat dissipation structure and a die encapsulated by the encapsulation material.
  • the cooling capability of the IC packaging structure may be improved accordingly without increasing the size of the IC packaging structure significantly.
  • an integrated circuit (IC) packaging structure includes a packaging substrate, one or a plurality of dies disposed on the packaging substrate, an encapsulation material, at least one trench, and a heat dissipation structure.
  • the encapsulation material is disposed on the packaging substrate and configured to encapsulate the one or the plurality of the dies on the packaging substrate.
  • the at least one trench is disposed in the encapsulation material. At least a part of the heat dissipation structure is disposed in the at least one trench.
  • a heat transfer coefficient of the heat dissipation structure is higher than a heat transfer coefficient of the encapsulation material.
  • the heat dissipation structure is isolated from the one or the plurality of the dies by the encapsulation material.
  • the heat dissipation structure includes a first portion disposed in the at least one trench and a second portion disposed on a surface of the encapsulation material.
  • the first portion is directly connected with the second portion.
  • a material composition of the second portion is identical to a material composition of the first portion.
  • a material composition of the second portion is different from a material composition of the first portion.
  • the first portion includes first metal particles
  • the second portion includes second metal particles
  • a dimension of each of the second metal particles is larger than a dimension of each of the first metal particles
  • the encapsulation material comprises an epoxy molding compound (EMC).
  • EMC epoxy molding compound
  • a manufacturing method of an IC packaging structure includes the following steps.
  • One or a plurality of dies is disposed on a packaging substrate.
  • An encapsulation material is formed on the packaging substrate.
  • the encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate.
  • At least one trench is formed in the encapsulation material.
  • a heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench.
  • the step of forming the heat dissipation structure includes the following steps.
  • a first slurry is formed in the at least one trench.
  • a first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.
  • the step of forming the heat dissipation structure further includes forming a second slurry on a surface of the encapsulation material after forming the first slurry in the at least one trench.
  • the step of forming the heat dissipation structure further includes performing a second curing process to the second slurry for forming a second portion of the heat dissipation structure on the surface of the encapsulation material, wherein the second slurry is formed after the first curing process.
  • the second slurry is formed before the first curing process, and the second slurry is cured by the first curing process to be a second portion of the heat dissipation structure on the surface of the encapsulation material.
  • a material composition of the second slurry is identical to a material composition of the first slurry.
  • a material composition of the second slurry is different from a material composition of the first slurry.
  • the first slurry comprises first metal particles
  • the second slurry comprises second metal particles
  • a dimension of each of the second metal particles is larger than a dimension of each of the first metal particles
  • the manufacturing method further includes performing a cutting process after the step of forming the heat dissipation structure.
  • the manufacturing method further includes performing a cutting process after the step of forming the encapsulation material and before the step of forming the at least one trench.
  • a heat transfer coefficient of the heat dissipation structure is higher than a heat transfer coefficient of the encapsulation material.
  • FIG. 1 is a schematic drawing illustrating an integrated circuit (IC) packaging structure according to a first embodiment of the present disclosure.
  • FIG. 2 is a flowchart of a manufacturing method of the IC packaging structure shown in FIG. 1 according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic drawing illustrating an IC packaging structure according to a second embodiment of the present disclosure.
  • FIG. 4 is a schematic drawing illustrating a second portion of a heat dissipation structure in the IC packaging structure according to the second embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a manufacturing method of the IC packaging structure shown in FIG. 3 according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a manufacturing method of the IC packaging structure shown in FIG. 3 according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic drawing illustrating a manufacturing method of the IC packaging structure shown in FIG. 3 according to further another embodiment of the present disclosure.
  • FIG. 8 is a schematic drawing illustrating an IC packaging structure according to a third embodiment of the present disclosure.
  • FIG. 9 is a schematic drawing illustrating a manufacturing method of the IC packaging structure shown in FIG. 8 according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a manufacturing method of an IC packaging structure according to a fourth embodiment of the present disclosure.
  • FIG. 11 is a schematic drawing illustrating the manufacturing method of the IC packaging structure according to the fourth embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a manufacturing method of an IC packaging structure according to a fifth embodiment of the present disclosure.
  • FIG. 13 is a schematic drawing illustrating the manufacturing method of the IC packaging structure according to the fifth embodiment of the present disclosure.
  • references in the specification to “one embodiment,” “an embodiment,” “some embodiments,” etc. indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
  • terminology may be understood at least in part from usage in context.
  • the term “one or more” as used herein, depending at least in part upon context may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense.
  • terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.
  • the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
  • spatially relative terms such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures.
  • the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.
  • the apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • FIG. 1 is a schematic drawing illustrating an integrated circuit (IC) packaging structure according to a first embodiment of the present disclosure.
  • an IC packaging structure 101 includes a packaging substrate 10 , one or a plurality of dies 22 disposed on the packaging substrate 10 , an encapsulation material 40 , at least one trench TR, and a heat dissipation structure 50 .
  • the encapsulation material 40 is disposed on the packaging substrate 10 and configured to encapsulate the one or the plurality of the dies 22 on the packaging substrate 10 .
  • the figures in the present disclosure are simplified schematic drawings for illustrative purposes, and the dies 22 are fully covered and encapsulated by the encapsulation material actually.
  • the at least one trench TR is disposed in the encapsulation material 40 . At least a part of the heat dissipation structure 50 is disposed in the at least one trench TR.
  • the cooling capability of the IC packaging structure 101 may be improved by the heat dissipation structure 50 because the heat dissipation structure 50 becomes closer to the dies 22 by being disposed in the trench TR within the encapsulation material 40 , and the size of the IC packaging structure will not be increased by the heat dissipation structure 50 .
  • the heat dissipation structure 50 in the present disclosure may be applied in different types of IC packaging technology, such as a ball grid array (BGA) package, a quad flat package (QFP), a quad flat no-leads (QFN) package, a land grid array (LGA) package, a pin grid array (PGA) package, or other suitable IC packaging technology.
  • the packaging substrate 10 may be formed by suitable insulating materials and/or dielectric materials.
  • the packaging substrate 10 may include a plastic substrate, such as an epoxy substrate, a bismaleimide triazine (BT) resin substrate, or a substrate made of other suitable materials capable of providing physical support to the dies 22 .
  • the packaging substrate 10 may include multiple layers of conductive wires (not shown) disposed in the insulating material, and different layers of the conductive wires may be connected with one another by a connection via in the packaging substrate 10 .
  • the dies 22 may be disposed on a first surface of the packaging substrate 10
  • a plurality of connection structures 60 (such as solder balls in BGA package) may be disposed on a second surface of the packaging substrate 10
  • the second surface may be opposite to the first surface in a vertical direction Z.
  • the vertical direction Z may be regarded as a thickness direction of the packaging substrate 10 , but not limited thereto.
  • each of the dies 22 may be electrically connected to the packaging substrate 10 by a bonding wire 30 (such as an aluminum wire, a copper wire, a silver wire, or a gold wire), and the dies 22 may be electrically connected to the connection structures 60 via the bonding wires 30 and the packaging substrate 10 , but not limited thereto.
  • a bonding wire 30 such as an aluminum wire, a copper wire, a silver wire, or a gold wire
  • Each of the dies 22 may be a die for any suitable purposes.
  • each of the dies 22 may be an IC die including circuits for date storage, compute, and/or processing. Some of the dies 22 may be stacked in the vertical direction Z.
  • a second die 22 B may be disposed on a first die 22 A in the vertical direction Z.
  • the second die 22 B may be smaller than the first die 22 A for providing a required bonding area on the first die 22 A, but not limited thereto.
  • the dimensions of the dies 22 stacked in the vertical direction Z may be substantially equal to one another, and the dies 22 may be shifted respectively in a horizontal direction perpendicular to the vertical direction Z for providing a required bonding area on each die 22 .
  • medium layers 20 may be disposed between the die 22 and the packaging substrate 10 and/or between the dies 22 , and each of the medium layers 20 may be an adhesive film, a polymer film, and/or a spacer film.
  • the encapsulation material 40 may include a plastic material, such as an epoxy molding compound (EMC), or other suitable insulation materials.
  • EMC epoxy molding compound
  • a heat transfer coefficient of the heat dissipation structure 50 may be higher than a heat transfer coefficient of the encapsulation material 40 .
  • the heat dissipation structure 50 may include metal, such as silver, or other suitable materials having respectively higher heat transfer coefficient.
  • the thermal conductivity of silver is about 429 W/(m ⁇ K)
  • the thermal conductivity of EMC is about 0.8 W/(m ⁇ K).
  • the heat dissipation structure 50 in this embodiment may be regarded as a heat dissipation structure embedded in the encapsulation material 40 for providing a better heat transfer path from the dies 22 to the surface of the IC packaging structure 101 .
  • Apart of the encapsulation material 40 is still located between the heat dissipation structure 50 and the dies 22 in the vertical direction Z.
  • the trench TR does not penetrate the encapsulation material 40 above the dies 22 , and the heat dissipation structure 50 may be isolated from the one or the plurality of the dies 22 by the encapsulation material 40 .
  • the heat dissipation structure 50 may be disposed corresponding to at least one of the dies 22 in the vertical direction Z, but not limited thereto.
  • the location of the heat dissipation structure 50 and/or the depth of the trench TR may be further modified according to the heat distribution on the stacked dies 22 and/or the circuits in the packaging substrate 10 .
  • a manufacturing method of the IC packaging structure 101 may include the following steps.
  • One or a plurality of dies 22 is disposed on the packaging substrate 10 .
  • the encapsulation material 40 is formed on the packaging substrate 10 .
  • the encapsulation material 40 is configured to encapsulate the one or the plurality of the dies 22 on the packaging substrate 10 .
  • At least one trench TR is formed in the encapsulation material 40 .
  • a heat dissipation structure 50 is formed on the encapsulation material 40 , and at least a part of the heat dissipation structure 50 is formed in the at least one trench TR.
  • FIG. 2 is a flowchart of a manufacturing method of the IC packaging structure 101 in FIG. 1 according to an embodiment of the present disclosure.
  • the method of forming the heat dissipation structure 50 may include but is not limited to the following steps.
  • step S 11 the at least one trench TR is formed in the encapsulation material 40 .
  • the trench TR may be formed by a laser engraving process, an etching process, or other suitable approaches.
  • step S 12 a first slurry P 1 may be formed in the at least one trench TR.
  • the first slurry P 1 may include metal, metallic compounds, adhesives, dispersing agents, solvents, or other suitable components.
  • the first slurry P 1 may be a sliver slurry including silver particles, but not limited thereto.
  • a first curing process is performed to the first slurry P 1 for forming the heat dissipation structure 50 in the trench TR.
  • the first curing process may include a thermal curing process, an irradiation curing process, or other suitable curing approaches according to the curing requirements of the first slurry P 1 .
  • the first slurry P 1 may be cured and solidified to be the heat dissipation structure 50 located in the trench TR. It is worth noting that the method of forming the heat dissipation structure 50 is not limited to the steps described above.
  • the heat dissipation structure 50 may be formed by other suitable approaches performed outside the trench TR (e.g. metal injection molding) and be placed in the trench TR subsequently.
  • the cooling capability of the IC packaging structure 101 may be improved without increasing the size of the IC packaging structure 101 because the heat dissipation structure 50 is disposed in the trench TR within the encapsulation material 40 and the heat dissipation structure 50 with a higher heat transfer coefficient becomes closer to the dies 22 on the packaging substrate 10 .
  • FIG. 3 is a schematic drawing illustrating an IC packaging structure 102 according to a second embodiment of the present disclosure.
  • FIG. 4 is a schematic drawing illustrating a second portion 50 B of the heat dissipation structure 50 in the IC packaging structure 103 .
  • the difference between the IC packaging structure 102 and the IC packaging structure in the first embodiment described above is that the heat dissipation structure 50 in the IC packaging structure 102 may include a first portion 50 A disposed in the at least one trench TR and a second portion 50 B disposed on a surface of the encapsulation material 40 .
  • the first portion 50 A may be directly connected with the second portion 50 B.
  • the material composition of the second portion 50 B may be identical to the material composition of the first portion 50 A, such as the materials of the heat dissipation structure 50 described in the first embodiment, but not limited thereto. In some embodiments, the material composition of the second portion 50 B may be different from the material composition of the first portion 50 A. For example, as shown in FIG. 4 , the second portion 50 B of the heat dissipation structure 50 disposed on the top surface of the encapsulation material 40 may have an uneven surface for increasing the surface area of the second portion 50 B and enhancing the cooling capacity of the heat dissipation structure 50 . In some embodiments, a plurality of metal particles (not shown) may be used to form the uneven surface of the second portion 50 B.
  • the first portion 50 A of the heat dissipation structure 50 may include first metal particles (such as silver powders, not shown), the second portion 50 B of the heat dissipation structure 50 may include second metal particles (not shown), and a dimension of each of the second metal particles may be larger than a dimension of each of the first metal particles because larger metal particles are required for forming the uneven surface of the second portion 50 B, but not limited thereto.
  • the roughness of the uneven surface of the second portion 50 B may be controlled by adjusting the dimension of the metal particles used in the second portion 50 B.
  • the uneven surface of the second portion 50 B may also be formed by other suitable approaches.
  • the thickness of the second portion 50 B in the vertical direction Z may be about 0.01 millimeter or less than 0.01 millimeter, and the cooling capability of the IC packaging structure 102 may be further improved by the second portion 50 B without increasing the size of the IC packaging structure 102 significantly.
  • FIG. 5 is a flowchart of a manufacturing method of the IC packaging structure 102 according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a manufacturing method of the IC packaging structure 102 according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic drawing illustrating a manufacturing method of the IC packaging structure 102 according to further another embodiment of the present disclosure.
  • a method of forming the heat dissipation structure 50 may include but is not limited to the following steps.
  • step S 21 the at least one trench TR is formed in the encapsulation material 40 .
  • step S 22 the first slurry P 1 may be formed in the at least one trench TR. Subsequently, in step S 23 , the first curing process is performed to the first slurry P 1 .
  • the first slurry P 1 may be cured and solidified by the first curing process to be the first portion 50 A of the heat dissipation structure 50 in the trench TR.
  • step S 24 may be carried on to form a second slurry P 2 on the surface of the encapsulation material 40 .
  • the second slurry P 2 may be formed after the step of forming the first slurry P 1 in the at least one trench TR and may be formed after the first curing process, but not limited thereto. Subsequently, in step S 25 , a second curing process may be performed to the second slurry P 2 for forming the second portion 50 B of the heat dissipation structure 50 on the surface of the encapsulation material 40 .
  • the second curing process may include a thermal curing process, an irradiation curing process, or other suitable curing approaches according to the curing requirements of the second slurry P 2 .
  • the second slurry P 2 may be cured and solidified to be the second portion 50 B of the heat dissipation structure 50 on the surface of the encapsulation material 40 .
  • the second slurry P 2 may be formed on the surface of the encapsulation material 40 by a spray coating process or other suitable approaches.
  • the material composition of the second slurry P 2 may be identical to the material composition of the first slurry P 1 described in the first embodiment.
  • the material composition of the second slurry P 2 may be different from the material composition of the first slurry P 1 .
  • the first slurry P 1 may include the first metal particles
  • the second slurry P 2 may include the second metal particles
  • the dimension of each of the second metal particles may be larger than the dimension of each of the first metal particles.
  • the first slurry P 1 and the second slurry P 2 may be cured and solidified by the first curing process and the second curing process respectively, and the first curing process may be different from the second curing process especially when the material composition of the second slurry P 2 may be different from the material composition of the first slurry P 1 , but not limited thereto.
  • the process condition of the second curing process may also be substantially identical to the process condition of the first curing process.
  • the second slurry P 2 may be further formed on side surfaces of the encapsulation material 40 , and the second slurry P 2 on the side surfaces of the encapsulation material 40 may be cured and solidified to be the second portion 50 B of the heat dissipation structure 50 on the side surfaces of the encapsulation material 40 .
  • a method of forming the heat dissipation structure 50 may include but is not limited to the following steps.
  • step S 31 the at least one trench TR is formed in the encapsulation material 40 .
  • step S 32 the first slurry P 1 may be formed in the at least one trench TR.
  • step S 33 the second slurry P 2 may be on the surface of the encapsulation material 40 and the first slurry P 1 .
  • step S 34 the first curing process is performed to the first slurry P 1 and the second slurry P 2 for forming the first portion 50 A and the second portion 50 B of the heat dissipation structure 50 respectively.
  • the second slurry P 2 may be formed before the first curing process, and the second slurry P 2 is cured and solidified by the first curing process to be the second portion 50 B of the heat dissipation structure 50 on the surface of the encapsulation material 40 .
  • the heat dissipation structure 50 including the first portion 50 A and the second portion 50 B connected to the first portion 50 A may be formed by other suitable approaches (e.g. metal injection molding) independently and be combined with the encapsulation material 40 having the trench TR formed therein subsequently.
  • FIG. 8 is a schematic drawing illustrating an IC packaging structure 103 according to a third embodiment of the present disclosure
  • FIG. 9 is a schematic drawing illustrating a manufacturing method of the IC packaging structure 103 according to an embodiment of the present disclosure.
  • the difference between the IC packaging structure 103 and the IC packaging structure in the second embodiment described above is that more than one trench TR may be formed in the encapsulation material 40 , and the heat dissipation structure 50 in the IC packaging structure 103 may include a plurality of first portions 50 A disposed in the trenches TR respectively.
  • the amount of the trenches TR, the shapes of the trenches TR, and/or the depth of each of the trenches TR may be further modified according to the heat distribution on the stacked dies 22 and/or the circuits in the packaging substrate 10 .
  • the heat dissipation structure 50 in the IC packaging structure 103 may be formed by a method similar to the method shown in FIG. 5 or the method shown in FIG. 6 described above.
  • the heat dissipation structure 50 including the first portions 50 A and the second portion 50 B connected to the first portions 50 A may be formed by other suitable approaches independently and be combined with the encapsulation material 40 having the trenches TR formed therein subsequently.
  • FIG. 10 is a flowchart of a manufacturing method of an IC packaging structure according to a fourth embodiment of the present disclosure
  • FIG. 11 is a schematic drawing illustrating the manufacturing method of the IC packaging structure in this embodiment.
  • the manufacturing method of the IC packaging structure may include the following steps.
  • a plurality of dies 22 may be disposed on the packaging substrate 10 .
  • At least some of the dies 22 may be disposed separated from one another in a horizontal direction orthogonal to the vertical direction Z, and the horizontal direction (such as a first direction D 1 shown in FIG. 11 ) may be parallel to the top surface of the packaging substrate 10 , but not limited thereto.
  • the encapsulation material 40 is formed on the packaging substrate 10 and encapsulates the dies 22 on the packaging substrate 10 .
  • step S 41 at least one trench TR is formed in the encapsulation material 40 .
  • step S 42 the first slurry is formed in the trench TR.
  • step S 43 the first curing process is performed to the first slurry.
  • step S 44 the second slurry is formed on the encapsulation material 40 .
  • step S 45 the second curing process is performed.
  • the steps S 41 -S 45 may be similar to the manufacturing method described in FIG. 5 and details of the steps S 41 -S 45 will not be redundantly described.
  • the manufacturing method of the steps S 41 -S 45 may be replaced by the manufacturing method described in FIG. 6 .
  • a cutting process may be performed.
  • the cutting process may be performed along cutting lines CL for separating some of the dies on the packaging substrate 10 , and the cutting process may be regarded as a singulation process, but not limited thereto.
  • the cutting process may be performed after the step of forming the heat dissipation structure 50 , but not limited thereto.
  • the trench TR may be a straight line pattern elongated in the first direction D 1 , and the dies 22 arranged in the first direction D 1 may be separated from one another by the cutting process.
  • three IC packaging structure 102 shown in FIG. 3 may be formed after performing the cutting process to the structure shown in FIG. 11 , but not limited thereto.
  • the projection shape of the trench TR in the vertical direction Z may be further modified according to the heat distribution on the dies 22 and/or the circuits in the packaging substrate 10 .
  • FIG. 12 is a flowchart of a manufacturing method of an IC packaging structure according to a fifth embodiment of the present disclosure
  • FIG. 13 is a schematic drawing illustrating the manufacturing method of the IC packaging structure in this embodiment.
  • FIG. 3 may be regarded as a schematic drawing in a step subsequent to FIG. 13 .
  • the manufacturing method of the IC packaging structure may include the following steps.
  • a plurality of dies 22 may be disposed on the packaging substrate 10 .
  • the encapsulation material 40 is formed on the packaging substrate 10 and encapsulates the dies 22 on the packaging substrate 10 .
  • step S 51 the cutting process is performed.
  • the cutting process may be performed along cutting lines CL for separating some of the dies on the packaging substrate 10 , and the cutting process may be regarded as a singulation process, but not limited thereto.
  • step S 52 at least one trench TR is formed in the encapsulation material 40 after the cutting process.
  • step S 53 the first slurry is formed in the trench TR.
  • step S 54 the first curing process is performed to the first slurry.
  • step S 55 the second slurry is formed on the encapsulation material 40 .
  • the second curing process is performed.
  • the steps S 52 -S 56 may be similar to the manufacturing method described in FIG.
  • the manufacturing method of the steps S 52 -S 56 may be replaced by the manufacturing method described in FIG. 6 .
  • the cutting process may be performed after the step of forming the encapsulation material 40 and before the step of forming the at least one trench TR.
  • the heat dissipation structure is at least partially disposed in the trench formed in the encapsulation material for reducing the distance between the heat dissipation structure and the dies encapsulated by the encapsulation material.
  • the cooling capability of the IC packaging structure may be improved accordingly without increasing the size of the IC packaging structure significantly.

Abstract

An integrated circuit (IC) packaging structure includes a packaging substrate, one or a plurality of dies, an encapsulation material, at least one trench, and a heat dissipation structure. The one or the plurality of the dies is disposed on the packaging substrate. The encapsulation material is disposed on the packaging substrate and is configured to encapsulate the one or the plurality of the dies on the packaging substrate. The at least one trench is disposed in the encapsulation material. At least a part of the heat dissipation structure is disposed in the at least one trench. The cooling capability of the IC packaging structure may be improved by the heat dissipation structure without increasing the size of the IC packaging structure significantly.

Description

    CROSS REFERENCE TO RELATED APPLICATIONS
  • This application is a continuation of International Application No. PCT/CN2019/072669 filed on Jan. 22, 2019, which is incorporated herein by reference in its entirety.
    • BACKGROUND OF THE INVENTION 1. Field of the Invention
  • The present disclosure relates to an integrated circuit (IC) packaging structure and a manufacturing method thereof, and more particularly, to an IC packaging structure including a heat dissipation structure and a manufacturing method thereof.
    • 2. Description of the Prior Art
  • In semiconductor manufacturing processes, an integrated circuit (IC) package is a step configured to encapsulate one or more semiconductor dies of integrated circuits with a molding compound for keeping the semiconductor dies from being damaged by external factors. Generally, a heat sink is disposed above the molding compound for heat dissipation. However, the heat dissipation performance is limited because the heat transfer coefficient of the molding compound is too low, and the total size of the IC package will be increased significantly by the heat sink especially when a higher cooling capability is demanded.
    • SUMMARY OF THE INVENTION
  • An integrated circuit (IC) packaging structure and a manufacturing method thereof are provided in the present disclosure. A trench is formed in an encapsulation material, and a heat dissipation structure is at least partially disposed in the trench for reducing the distance between the heat dissipation structure and a die encapsulated by the encapsulation material. The cooling capability of the IC packaging structure may be improved accordingly without increasing the size of the IC packaging structure significantly.
  • According to an embodiment of the present disclosure, an integrated circuit (IC) packaging structure is provided. The IC packaging structure includes a packaging substrate, one or a plurality of dies disposed on the packaging substrate, an encapsulation material, at least one trench, and a heat dissipation structure. The encapsulation material is disposed on the packaging substrate and configured to encapsulate the one or the plurality of the dies on the packaging substrate. The at least one trench is disposed in the encapsulation material. At least a part of the heat dissipation structure is disposed in the at least one trench.
  • In some embodiments, a heat transfer coefficient of the heat dissipation structure is higher than a heat transfer coefficient of the encapsulation material.
  • In some embodiments, the heat dissipation structure is isolated from the one or the plurality of the dies by the encapsulation material.
  • In some embodiments, the heat dissipation structure includes a first portion disposed in the at least one trench and a second portion disposed on a surface of the encapsulation material.
  • In some embodiments, the first portion is directly connected with the second portion.
  • In some embodiments, a material composition of the second portion is identical to a material composition of the first portion.
  • In some embodiments, a material composition of the second portion is different from a material composition of the first portion.
  • In some embodiments, the first portion includes first metal particles, the second portion includes second metal particles, and a dimension of each of the second metal particles is larger than a dimension of each of the first metal particles.
  • In some embodiments, the encapsulation material comprises an epoxy molding compound (EMC).
  • According to an embodiment of the present disclosure, a manufacturing method of an IC packaging structure is provided. The manufacturing method includes the following steps. One or a plurality of dies is disposed on a packaging substrate. An encapsulation material is formed on the packaging substrate. The encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate. At least one trench is formed in the encapsulation material. A heat dissipation structure is formed on the encapsulation material, and at least a part of the heat dissipation structure is formed in the at least one trench.
  • In some embodiments, the step of forming the heat dissipation structure includes the following steps. A first slurry is formed in the at least one trench. A first curing process is performed to the first slurry for forming a first portion of the heat dissipation structure.
  • In some embodiments, the step of forming the heat dissipation structure further includes forming a second slurry on a surface of the encapsulation material after forming the first slurry in the at least one trench.
  • In some embodiments, the step of forming the heat dissipation structure further includes performing a second curing process to the second slurry for forming a second portion of the heat dissipation structure on the surface of the encapsulation material, wherein the second slurry is formed after the first curing process.
  • In some embodiments, the second slurry is formed before the first curing process, and the second slurry is cured by the first curing process to be a second portion of the heat dissipation structure on the surface of the encapsulation material.
  • In some embodiments, a material composition of the second slurry is identical to a material composition of the first slurry.
  • In some embodiments, a material composition of the second slurry is different from a material composition of the first slurry.
  • In some embodiments, the first slurry comprises first metal particles, the second slurry comprises second metal particles, and a dimension of each of the second metal particles is larger than a dimension of each of the first metal particles.
  • In some embodiments, the manufacturing method further includes performing a cutting process after the step of forming the heat dissipation structure.
  • In some embodiments, the manufacturing method further includes performing a cutting process after the step of forming the encapsulation material and before the step of forming the at least one trench.
  • In some embodiments, a heat transfer coefficient of the heat dissipation structure is higher than a heat transfer coefficient of the encapsulation material.
  • Other aspects of the present disclosure can be understood by those skilled in the art in light of the description, the claims, and the drawings of the present disclosure.
  • These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.
  • FIG. 1 is a schematic drawing illustrating an integrated circuit (IC) packaging structure according to a first embodiment of the present disclosure.
  • FIG. 2 is a flowchart of a manufacturing method of the IC packaging structure shown in FIG. 1 according to an embodiment of the present disclosure.
  • FIG. 3 is a schematic drawing illustrating an IC packaging structure according to a second embodiment of the present disclosure.
  • FIG. 4 is a schematic drawing illustrating a second portion of a heat dissipation structure in the IC packaging structure according to the second embodiment of the present disclosure.
  • FIG. 5 is a flowchart of a manufacturing method of the IC packaging structure shown in FIG. 3 according to an embodiment of the present disclosure.
  • FIG. 6 is a flowchart of a manufacturing method of the IC packaging structure shown in FIG. 3 according to another embodiment of the present disclosure.
  • FIG. 7 is a schematic drawing illustrating a manufacturing method of the IC packaging structure shown in FIG. 3 according to further another embodiment of the present disclosure.
  • FIG. 8 is a schematic drawing illustrating an IC packaging structure according to a third embodiment of the present disclosure.
  • FIG. 9 is a schematic drawing illustrating a manufacturing method of the IC packaging structure shown in FIG. 8 according to an embodiment of the present disclosure.
  • FIG. 10 is a flowchart of a manufacturing method of an IC packaging structure according to a fourth embodiment of the present disclosure.
  • FIG. 11 is a schematic drawing illustrating the manufacturing method of the IC packaging structure according to the fourth embodiment of the present disclosure.
  • FIG. 12 is a flowchart of a manufacturing method of an IC packaging structure according to a fifth embodiment of the present disclosure.
  • FIG. 13 is a schematic drawing illustrating the manufacturing method of the IC packaging structure according to the fifth embodiment of the present disclosure.
    •  DETAILED DESCRIPTION
  • Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.
  • It is noted that references in the specification to “one embodiment,” “an embodiment,” “some embodiments,” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.
  • In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a,” “an,” or “the,” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.
  • It should be readily understood that the meaning of “on,” “above,” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something).
  • Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
  • Please refer to FIG. 1. FIG. 1 is a schematic drawing illustrating an integrated circuit (IC) packaging structure according to a first embodiment of the present disclosure. As shown in FIG. 1, an IC packaging structure 101 includes a packaging substrate 10, one or a plurality of dies 22 disposed on the packaging substrate 10, an encapsulation material 40, at least one trench TR, and a heat dissipation structure 50. The encapsulation material 40 is disposed on the packaging substrate 10 and configured to encapsulate the one or the plurality of the dies 22 on the packaging substrate 10. It should be noted that the figures in the present disclosure are simplified schematic drawings for illustrative purposes, and the dies 22 are fully covered and encapsulated by the encapsulation material actually. The at least one trench TR is disposed in the encapsulation material 40. At least a part of the heat dissipation structure 50 is disposed in the at least one trench TR. The cooling capability of the IC packaging structure 101 may be improved by the heat dissipation structure 50 because the heat dissipation structure 50 becomes closer to the dies 22 by being disposed in the trench TR within the encapsulation material 40, and the size of the IC packaging structure will not be increased by the heat dissipation structure 50.
  • The heat dissipation structure 50 in the present disclosure may be applied in different types of IC packaging technology, such as a ball grid array (BGA) package, a quad flat package (QFP), a quad flat no-leads (QFN) package, a land grid array (LGA) package, a pin grid array (PGA) package, or other suitable IC packaging technology. In some embodiments, the packaging substrate 10 may be formed by suitable insulating materials and/or dielectric materials. For example, the packaging substrate 10 may include a plastic substrate, such as an epoxy substrate, a bismaleimide triazine (BT) resin substrate, or a substrate made of other suitable materials capable of providing physical support to the dies 22. In some embodiments, the packaging substrate 10 may include multiple layers of conductive wires (not shown) disposed in the insulating material, and different layers of the conductive wires may be connected with one another by a connection via in the packaging substrate 10. In some embodiments, the dies 22 may be disposed on a first surface of the packaging substrate 10, a plurality of connection structures 60 (such as solder balls in BGA package) may be disposed on a second surface of the packaging substrate 10, and the second surface may be opposite to the first surface in a vertical direction Z. The vertical direction Z may be regarded as a thickness direction of the packaging substrate 10, but not limited thereto. In some embodiments, each of the dies 22 may be electrically connected to the packaging substrate 10 by a bonding wire 30 (such as an aluminum wire, a copper wire, a silver wire, or a gold wire), and the dies 22 may be electrically connected to the connection structures 60 via the bonding wires 30 and the packaging substrate 10, but not limited thereto.
  • Each of the dies 22 may be a die for any suitable purposes. In some embodiments, each of the dies 22 may be an IC die including circuits for date storage, compute, and/or processing. Some of the dies 22 may be stacked in the vertical direction Z. For example, a second die 22B may be disposed on a first die 22A in the vertical direction Z. In some embodiments, the second die 22B may be smaller than the first die 22A for providing a required bonding area on the first die 22A, but not limited thereto. In some embodiments, the dimensions of the dies 22 stacked in the vertical direction Z may be substantially equal to one another, and the dies 22 may be shifted respectively in a horizontal direction perpendicular to the vertical direction Z for providing a required bonding area on each die 22. In some embodiments, medium layers 20 may be disposed between the die 22 and the packaging substrate 10 and/or between the dies 22, and each of the medium layers 20 may be an adhesive film, a polymer film, and/or a spacer film.
  • The encapsulation material 40 may include a plastic material, such as an epoxy molding compound (EMC), or other suitable insulation materials. In some embodiments, a heat transfer coefficient of the heat dissipation structure 50 may be higher than a heat transfer coefficient of the encapsulation material 40. For example, the heat dissipation structure 50 may include metal, such as silver, or other suitable materials having respectively higher heat transfer coefficient. The thermal conductivity of silver is about 429 W/(m·K), and the thermal conductivity of EMC is about 0.8 W/(m·K). The heat dissipation structure 50 in this embodiment may be regarded as a heat dissipation structure embedded in the encapsulation material 40 for providing a better heat transfer path from the dies 22 to the surface of the IC packaging structure 101. Apart of the encapsulation material 40 is still located between the heat dissipation structure 50 and the dies 22 in the vertical direction Z. In other words, the trench TR does not penetrate the encapsulation material 40 above the dies 22, and the heat dissipation structure 50 may be isolated from the one or the plurality of the dies 22 by the encapsulation material 40. In some embodiments, the heat dissipation structure 50 may be disposed corresponding to at least one of the dies 22 in the vertical direction Z, but not limited thereto. The location of the heat dissipation structure 50 and/or the depth of the trench TR may be further modified according to the heat distribution on the stacked dies 22 and/or the circuits in the packaging substrate 10.
  • As shown in FIG. 1, a manufacturing method of the IC packaging structure 101 may include the following steps. One or a plurality of dies 22 is disposed on the packaging substrate 10. The encapsulation material 40 is formed on the packaging substrate 10. The encapsulation material 40 is configured to encapsulate the one or the plurality of the dies 22 on the packaging substrate 10. At least one trench TR is formed in the encapsulation material 40. A heat dissipation structure 50 is formed on the encapsulation material 40, and at least a part of the heat dissipation structure 50 is formed in the at least one trench TR.
  • Please refer to FIG. 2 and FIG. 1. FIG. 2 is a flowchart of a manufacturing method of the IC packaging structure 101 in FIG. 1 according to an embodiment of the present disclosure. As shown in FIG. 2 and FIG. 1, the method of forming the heat dissipation structure 50 may include but is not limited to the following steps. In step S11, the at least one trench TR is formed in the encapsulation material 40. The trench TR may be formed by a laser engraving process, an etching process, or other suitable approaches. In step S12, a first slurry P1 may be formed in the at least one trench TR. The first slurry P1 may include metal, metallic compounds, adhesives, dispersing agents, solvents, or other suitable components. In some embodiments, the first slurry P1 may be a sliver slurry including silver particles, but not limited thereto. Subsequently, in step S13, a first curing process is performed to the first slurry P1 for forming the heat dissipation structure 50 in the trench TR. In some embodiments, the first curing process may include a thermal curing process, an irradiation curing process, or other suitable curing approaches according to the curing requirements of the first slurry P1. The first slurry P1 may be cured and solidified to be the heat dissipation structure 50 located in the trench TR. It is worth noting that the method of forming the heat dissipation structure 50 is not limited to the steps described above. In some embodiments, the heat dissipation structure 50 may be formed by other suitable approaches performed outside the trench TR (e.g. metal injection molding) and be placed in the trench TR subsequently.
  • The cooling capability of the IC packaging structure 101 may be improved without increasing the size of the IC packaging structure 101 because the heat dissipation structure 50 is disposed in the trench TR within the encapsulation material 40 and the heat dissipation structure 50 with a higher heat transfer coefficient becomes closer to the dies 22 on the packaging substrate 10.
  • The following description will detail the different embodiments of the present disclosure. To simplify the description, identical components in each of the following embodiments are marked with identical symbols. For making it easier to understand the differences between the embodiments, the following description will detail the dissimilarities among different embodiments and the identical features will not be redundantly described.
  • Please refer to FIG. 3 and FIG. 4. FIG. 3 is a schematic drawing illustrating an IC packaging structure 102 according to a second embodiment of the present disclosure. FIG. 4 is a schematic drawing illustrating a second portion 50B of the heat dissipation structure 50 in the IC packaging structure 103. As shown in FIG. 3 and FIG. 4, the difference between the IC packaging structure 102 and the IC packaging structure in the first embodiment described above is that the heat dissipation structure 50 in the IC packaging structure 102 may include a first portion 50A disposed in the at least one trench TR and a second portion 50B disposed on a surface of the encapsulation material 40. In some embodiments, the first portion 50A may be directly connected with the second portion 50B. In some embodiments, the material composition of the second portion 50B may be identical to the material composition of the first portion 50A, such as the materials of the heat dissipation structure 50 described in the first embodiment, but not limited thereto. In some embodiments, the material composition of the second portion 50B may be different from the material composition of the first portion 50A. For example, as shown in FIG. 4, the second portion 50B of the heat dissipation structure 50 disposed on the top surface of the encapsulation material 40 may have an uneven surface for increasing the surface area of the second portion 50B and enhancing the cooling capacity of the heat dissipation structure 50. In some embodiments, a plurality of metal particles (not shown) may be used to form the uneven surface of the second portion 50B. In some embodiments, the first portion 50A of the heat dissipation structure 50 may include first metal particles (such as silver powders, not shown), the second portion 50B of the heat dissipation structure 50 may include second metal particles (not shown), and a dimension of each of the second metal particles may be larger than a dimension of each of the first metal particles because larger metal particles are required for forming the uneven surface of the second portion 50B, but not limited thereto. The roughness of the uneven surface of the second portion 50B may be controlled by adjusting the dimension of the metal particles used in the second portion 50B. In some embodiments, the uneven surface of the second portion 50B may also be formed by other suitable approaches. The thickness of the second portion 50B in the vertical direction Z may be about 0.01 millimeter or less than 0.01 millimeter, and the cooling capability of the IC packaging structure 102 may be further improved by the second portion 50B without increasing the size of the IC packaging structure 102 significantly.
  • Please refer to FIGS. 5-7 and FIG. 3. FIG. 5 is a flowchart of a manufacturing method of the IC packaging structure 102 according to an embodiment of the present disclosure. FIG. 6 is a flowchart of a manufacturing method of the IC packaging structure 102 according to another embodiment of the present disclosure. FIG. 7 is a schematic drawing illustrating a manufacturing method of the IC packaging structure 102 according to further another embodiment of the present disclosure. As shown in FIG. 5 and FIG. 3, in some embodiments, a method of forming the heat dissipation structure 50 may include but is not limited to the following steps. In step S21, the at least one trench TR is formed in the encapsulation material 40. In step S22, the first slurry P1 may be formed in the at least one trench TR. Subsequently, in step S23, the first curing process is performed to the first slurry P1. The first slurry P1 may be cured and solidified by the first curing process to be the first portion 50A of the heat dissipation structure 50 in the trench TR. After the step of forming the first portion 50A of the heat dissipation structure 50, step S24 may be carried on to form a second slurry P2 on the surface of the encapsulation material 40. In other words, the second slurry P2 may be formed after the step of forming the first slurry P1 in the at least one trench TR and may be formed after the first curing process, but not limited thereto. Subsequently, in step S25, a second curing process may be performed to the second slurry P2 for forming the second portion 50B of the heat dissipation structure 50 on the surface of the encapsulation material 40.
  • In some embodiments, the second curing process may include a thermal curing process, an irradiation curing process, or other suitable curing approaches according to the curing requirements of the second slurry P2. The second slurry P2 may be cured and solidified to be the second portion 50B of the heat dissipation structure 50 on the surface of the encapsulation material 40. The second slurry P2 may be formed on the surface of the encapsulation material 40 by a spray coating process or other suitable approaches. In some embodiments, the material composition of the second slurry P2 may be identical to the material composition of the first slurry P1 described in the first embodiment. In some embodiments, the material composition of the second slurry P2 may be different from the material composition of the first slurry P1. For example, the first slurry P1 may include the first metal particles, the second slurry P2 may include the second metal particles, and the dimension of each of the second metal particles may be larger than the dimension of each of the first metal particles. In addition, the first slurry P1 and the second slurry P2 may be cured and solidified by the first curing process and the second curing process respectively, and the first curing process may be different from the second curing process especially when the material composition of the second slurry P2 may be different from the material composition of the first slurry P1, but not limited thereto. In some embodiments, the process condition of the second curing process may also be substantially identical to the process condition of the first curing process. Additionally, in some embodiments, the second slurry P2 may be further formed on side surfaces of the encapsulation material 40, and the second slurry P2 on the side surfaces of the encapsulation material 40 may be cured and solidified to be the second portion 50B of the heat dissipation structure 50 on the side surfaces of the encapsulation material 40.
  • As shown in FIG. 6 and FIG. 3, in some embodiments, a method of forming the heat dissipation structure 50 may include but is not limited to the following steps. In step S31, the at least one trench TR is formed in the encapsulation material 40. In step S32, the first slurry P1 may be formed in the at least one trench TR. Subsequently, in step S33, the second slurry P2 may be on the surface of the encapsulation material 40 and the first slurry P1. In step S34, the first curing process is performed to the first slurry P1 and the second slurry P2 for forming the first portion 50A and the second portion 50B of the heat dissipation structure 50 respectively. In other words, the second slurry P2 may be formed before the first curing process, and the second slurry P2 is cured and solidified by the first curing process to be the second portion 50B of the heat dissipation structure 50 on the surface of the encapsulation material 40.
  • As shown in FIG. 7 and FIG. 3, in some embodiments, the heat dissipation structure 50 including the first portion 50A and the second portion 50B connected to the first portion 50A may be formed by other suitable approaches (e.g. metal injection molding) independently and be combined with the encapsulation material 40 having the trench TR formed therein subsequently.
  • Please refer to FIG. 8 and FIG. 9. FIG. 8 is a schematic drawing illustrating an IC packaging structure 103 according to a third embodiment of the present disclosure, and FIG. 9 is a schematic drawing illustrating a manufacturing method of the IC packaging structure 103 according to an embodiment of the present disclosure. As shown in FIG. 8, the difference between the IC packaging structure 103 and the IC packaging structure in the second embodiment described above is that more than one trench TR may be formed in the encapsulation material 40, and the heat dissipation structure 50 in the IC packaging structure 103 may include a plurality of first portions 50A disposed in the trenches TR respectively. The amount of the trenches TR, the shapes of the trenches TR, and/or the depth of each of the trenches TR may be further modified according to the heat distribution on the stacked dies 22 and/or the circuits in the packaging substrate 10. In some embodiments, the heat dissipation structure 50 in the IC packaging structure 103 may be formed by a method similar to the method shown in FIG. 5 or the method shown in FIG. 6 described above. In some embodiments, the heat dissipation structure 50 including the first portions 50A and the second portion 50B connected to the first portions 50A may be formed by other suitable approaches independently and be combined with the encapsulation material 40 having the trenches TR formed therein subsequently.
  • Please refer to FIG. 10, FIG. 11 and FIG. 3. FIG. 10 is a flowchart of a manufacturing method of an IC packaging structure according to a fourth embodiment of the present disclosure, and FIG. 11 is a schematic drawing illustrating the manufacturing method of the IC packaging structure in this embodiment. As shown in FIG. 10 and FIG. 11, the manufacturing method of the IC packaging structure may include the following steps. A plurality of dies 22 may be disposed on the packaging substrate 10. At least some of the dies 22 may be disposed separated from one another in a horizontal direction orthogonal to the vertical direction Z, and the horizontal direction (such as a first direction D1 shown in FIG. 11) may be parallel to the top surface of the packaging substrate 10, but not limited thereto. The encapsulation material 40 is formed on the packaging substrate 10 and encapsulates the dies 22 on the packaging substrate 10. Subsequently, in step S41, at least one trench TR is formed in the encapsulation material 40. In step S42, the first slurry is formed in the trench TR. In step S43, the first curing process is performed to the first slurry. In step S44, the second slurry is formed on the encapsulation material 40. In step S45, the second curing process is performed. The steps S41-S45 may be similar to the manufacturing method described in FIG. 5 and details of the steps S41-S45 will not be redundantly described. In some embodiments, the manufacturing method of the steps S41-S45 may be replaced by the manufacturing method described in FIG. 6. Subsequently, in step S46, a cutting process may be performed. In some embodiments, the cutting process may be performed along cutting lines CL for separating some of the dies on the packaging substrate 10, and the cutting process may be regarded as a singulation process, but not limited thereto. In some embodiments, the cutting process may be performed after the step of forming the heat dissipation structure 50, but not limited thereto. In some embodiment, the trench TR may be a straight line pattern elongated in the first direction D1, and the dies 22 arranged in the first direction D1 may be separated from one another by the cutting process. For example, three IC packaging structure 102 shown in FIG. 3 may be formed after performing the cutting process to the structure shown in FIG. 11, but not limited thereto. The projection shape of the trench TR in the vertical direction Z may be further modified according to the heat distribution on the dies 22 and/or the circuits in the packaging substrate 10.
  • Please refer to FIG. 12, FIG. 13, and FIG. 3. FIG. 12 is a flowchart of a manufacturing method of an IC packaging structure according to a fifth embodiment of the present disclosure, and FIG. 13 is a schematic drawing illustrating the manufacturing method of the IC packaging structure in this embodiment. FIG. 3 may be regarded as a schematic drawing in a step subsequent to FIG. 13. As shown in FIG. 12 and FIG. 13, the manufacturing method of the IC packaging structure may include the following steps. A plurality of dies 22 may be disposed on the packaging substrate 10. The encapsulation material 40 is formed on the packaging substrate 10 and encapsulates the dies 22 on the packaging substrate 10. Subsequently, in step S51, the cutting process is performed. In some embodiments, the cutting process may be performed along cutting lines CL for separating some of the dies on the packaging substrate 10, and the cutting process may be regarded as a singulation process, but not limited thereto. As shown in FIG. 12, FIG. 13, and FIG. 3, in step S52, at least one trench TR is formed in the encapsulation material 40 after the cutting process. In step S53, the first slurry is formed in the trench TR. In step S54, the first curing process is performed to the first slurry. In step S55, the second slurry is formed on the encapsulation material 40. In step S56, the second curing process is performed. The steps S52-S56 may be similar to the manufacturing method described in FIG. 5 and details of the steps S52-S56 will not be redundantly described. In some embodiments, the manufacturing method of the steps S52-S56 may be replaced by the manufacturing method described in FIG. 6. In some embodiments, the cutting process may be performed after the step of forming the encapsulation material 40 and before the step of forming the at least one trench TR.
  • To summarize the above descriptions, in the IC packaging structure and the manufacturing method thereof according to the present disclosure, the heat dissipation structure is at least partially disposed in the trench formed in the encapsulation material for reducing the distance between the heat dissipation structure and the dies encapsulated by the encapsulation material. The cooling capability of the IC packaging structure may be improved accordingly without increasing the size of the IC packaging structure significantly.
  • Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.

Claims (20)

1: An integrated circuit (IC) packaging structure, comprising:
a packaging substrate;
one or a plurality of dies disposed on the packaging substrate;
an encapsulation material disposed on the packaging substrate and configured to encapsulate the one or the plurality of the dies on the packaging substrate;
at least one trench disposed in the encapsulation material; and
a heat dissipation structure, wherein at least a part of the heat dissipation structure is disposed in the at least one trench.
2: The IC packaging structure according to claim 1, wherein a heat transfer coefficient of the heat dissipation structure is higher than a heat transfer coefficient of the encapsulation material.
3: The IC packaging structure according to claim 1, wherein the heat dissipation structure is isolated from the one or the plurality of the dies by the encapsulation material.
4: The IC packaging structure according to claim 1, wherein the heat dissipation structure comprises:
a first portion disposed in the at least one trench; and
a second portion disposed on a surface of the encapsulation material.
5: The IC packaging structure according to claim 4, wherein the first portion is directly connected with the second portion.
6: The IC packaging structure according to claim 4, wherein a material composition of the second portion is identical to a material composition of the first portion.
7: The IC packaging structure according to claim 4, wherein a material composition of the second portion is different from a material composition of the first portion.
8: The IC packaging structure according to claim 7, wherein the first portion comprises first metal particles, the second portion comprises second metal particles, and a dimension of each of the second metal particles is larger than a dimension of each of the first metal particles.
9: The IC packaging structure according to claim 1, wherein the encapsulation material comprises an epoxy molding compound (EMC).
10: A manufacturing method of an integrated circuit (IC) packaging structure, comprising:
disposing one or a plurality of dies on a packaging substrate;
forming an encapsulation material on the packaging substrate, wherein the encapsulation material is configured to encapsulate the one or the plurality of the dies on the packaging substrate;
forming at least one trench in the encapsulation material; and
forming a heat dissipation structure on the encapsulation material, wherein at least a part of the heat dissipation structure is formed in the at least one trench.
11: The manufacturing method of the IC packaging structure according to claim 10, wherein the step of forming the heat dissipation structure comprises:
forming a first slurry in the at least one trench; and
performing a first curing process to the first slurry for forming a first portion of the heat dissipation structure.
12: The manufacturing method of the IC packaging structure according to claim 11, wherein the step of forming the heat dissipation structure further comprises:
forming a second slurry on a surface of the encapsulation material after forming the first slurry in the at least one trench.
13: The manufacturing method of the IC packaging structure according to claim 12, wherein the step of forming the heat dissipation structure further comprises:
performing a second curing process to the second slurry for forming a second portion of the heat dissipation structure on the surface of the encapsulation material, wherein the second slurry is formed after the first curing process.
14: The manufacturing method of the IC packaging structure according to claim 12, wherein the second slurry is formed before the first curing process, and the second slurry is cured by the first curing process to be a second portion of the heat dissipation structure on the surface of the encapsulation material.
15: The manufacturing method of the IC packaging structure according to claim 12, wherein a material composition of the second slurry is identical to a material composition of the first slurry.
16: The manufacturing method of the IC packaging structure according to claim 12, wherein a material composition of the second slurry is different from a material composition of the first slurry.
17: The manufacturing method of the IC packaging structure according to claim 16, wherein the first slurry comprises first metal particles, the second slurry comprises second metal particles, and a dimension of each of the second metal particles is larger than a dimension of each of the first metal particles.
18: The manufacturing method of the IC packaging structure according to claim 10, further comprising:
performing a cutting process after the step of forming the heat dissipation structure.
19: The manufacturing method of the IC packaging structure according to claim 10, further comprising:
performing a cutting process after the step of forming the encapsulation material and before the step of forming the at least one trench.
20: The manufacturing method of the IC packaging structure according to claim 10, wherein a heat transfer coefficient of the heat dissipation structure is higher than a heat transfer coefficient of the encapsulation material.
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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2023031660A (en) * 2021-08-25 2023-03-09 キオクシア株式会社 Semiconductor device and electronic equipment

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5883430A (en) * 1996-06-19 1999-03-16 International Business Machines Corporation Thermally enhanced flip chip package
US6369455B1 (en) * 2000-01-04 2002-04-09 Siliconware Precision Industries Co., Ltd. Externally-embedded heat-dissipating device for ball grid array integrated circuit package
US6469380B2 (en) * 2000-11-08 2002-10-22 Citizen Watch Co., Ltd. Resin sealed semiconductor device utilizing a clad material heat sink
US8058736B2 (en) * 2006-06-09 2011-11-15 Renesas Electronics Corporation Semiconductor device having heat spreader with center opening
US8581374B1 (en) * 2010-10-04 2013-11-12 Marvell International Ltd. Placing heat sink into packaging by strip formation assembly
US9059143B2 (en) * 2010-07-28 2015-06-16 J-Devices Corporation Semiconductor device

Family Cites Families (44)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0697326A (en) * 1992-09-14 1994-04-08 Apic Yamada Kk Semiconductor device and heat radiating member thereof
JPH0837256A (en) * 1994-07-26 1996-02-06 Hitachi Ltd Semiconductor device
TW388976B (en) * 1998-10-21 2000-05-01 Siliconware Precision Industries Co Ltd Semiconductor package with fully exposed heat sink
US6265771B1 (en) * 1999-01-27 2001-07-24 International Business Machines Corporation Dual chip with heat sink
FR2811476B1 (en) * 2000-07-07 2002-12-06 Thomson Csf ELECTRONIC DEVICE WITH THERMALLY CONDUCTIVE ENCAPSULANT
US6541310B1 (en) * 2000-07-24 2003-04-01 Siliconware Precision Industries Co., Ltd. Method of fabricating a thin and fine ball-grid array package with embedded heat spreader
JP3888439B2 (en) * 2002-02-25 2007-03-07 セイコーエプソン株式会社 Manufacturing method of semiconductor device
TW556469B (en) * 2002-08-20 2003-10-01 Via Tech Inc IC package with an implanted heat-dissipation fin
CN1494136A (en) * 2002-11-01 2004-05-05 威宇科技测试封装（上海）有限公司 Chip packaging structure having internal set heat radiation fin
CN2596547Y (en) * 2002-12-25 2003-12-31 立卫科技股份有限公司 Semiconductor packaging structure with radiating fin
US7550097B2 (en) * 2003-09-03 2009-06-23 Momentive Performance Materials, Inc. Thermal conductive material utilizing electrically conductive nanoparticles
EP1524690B1 (en) * 2003-10-13 2009-03-11 Infineon Technologies AG Semiconductor package with heat spreader
TWI253731B (en) * 2004-11-04 2006-04-21 Advanced Semiconductor Eng Semiconductor package
US7361986B2 (en) * 2004-12-01 2008-04-22 Taiwan Semiconductor Manufacturing Company, Ltd. Heat stud for stacked chip package
JP2007066960A (en) * 2005-08-29 2007-03-15 Seiko Instruments Inc Semiconductor package, circuit board, and process for manufacturing semiconductor package
US7378300B2 (en) * 2005-09-22 2008-05-27 Stats Chippac Ltd. Integrated circuit package system
US7723759B2 (en) * 2005-10-24 2010-05-25 Intel Corporation Stacked wafer or die packaging with enhanced thermal and device performance
US7468548B2 (en) * 2005-12-09 2008-12-23 Fairchild Semiconductor Corporation Thermal enhanced upper and dual heat sink exposed molded leadless package
DE102006000724A1 (en) * 2006-01-03 2007-07-12 Infineon Technologies Ag Electronic semiconductor unit, has semiconductor chip, cooling body, and passage contacts that are partly embedded into filling layer, where passage contacts are separated from cooling body through recesses
JP4351239B2 (en) * 2006-09-13 2009-10-28 タツタ システム・エレクトロニクス株式会社 Thermal conductive paste
JP2008153430A (en) * 2006-12-18 2008-07-03 Mitsubishi Electric Corp Heatsink substrate and heat conductive sheet, and power module using these
JP5178117B2 (en) * 2007-09-28 2013-04-10 ユニチカ株式会社 Heat dissipation slurry and electronic parts using the same
KR101046378B1 (en) * 2008-01-10 2011-07-05 주식회사 하이닉스반도체 Semiconductor package
JPWO2009142036A1 (en) * 2008-05-21 2011-09-29 ニホンハンダ株式会社 Heat-dissipating cured coating film, coating composition, method for producing heat-dissipating cured coating film, and electronic device having heat-dissipating cured coating film
US7964951B2 (en) * 2009-03-16 2011-06-21 Ati Technologies Ulc Multi-die semiconductor package with heat spreader
US7875970B2 (en) * 2009-06-10 2011-01-25 Green Arrow Asia Limited Integrated circuit package having a castellated heatspreader
JP5401292B2 (en) * 2009-12-15 2014-01-29 ルネサスエレクトロニクス株式会社 Semiconductor device and communication method
JP2013089718A (en) * 2011-10-17 2013-05-13 Kaneka Corp Heat sink with highly heat-conducting resin, and led light source
US8704341B2 (en) * 2012-05-15 2014-04-22 Advanced Semiconductor Engineering, Inc. Semiconductor packages with thermal dissipation structures and EMI shielding
TWI497781B (en) * 2012-07-19 2015-08-21 Univ Nat Cheng Kung Light emitting diode device with enhancement of heat dissipation, and the method of preparing the same
US8836110B2 (en) * 2012-08-31 2014-09-16 Freescale Semiconductor, Inc. Heat spreader for use within a packaged semiconductor device
CN104576565A (en) * 2013-10-18 2015-04-29 飞思卡尔半导体公司 Semiconductor device provided with radiator and assembly method of semiconductor device
JP6349543B2 (en) * 2013-12-25 2018-07-04 パナソニックＩｐマネジメント株式会社 COOLING STRUCTURE AND METHOD FOR MANUFACTURING COOLING STRUCTURE
US9269647B2 (en) 2014-05-29 2016-02-23 Samsung Electronics Co., Ltd. Semiconductor package having heat dissipating member
JP6331879B2 (en) * 2014-08-26 2018-05-30 株式会社デンソー Electronic device and manufacturing method thereof
US10002857B2 (en) * 2016-04-12 2018-06-19 Qualcomm Incorporated Package on package (PoP) device comprising thermal interface material (TIM) in cavity of an encapsulation layer
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
CN106384730A (en) * 2016-12-06 2017-02-08 江苏悦达新材料科技有限公司 High heat conduction metal foil layer/graphene metal mixed layer composite heat radiation film
CN106601691A (en) * 2016-12-30 2017-04-26 广东美的制冷设备有限公司 Intelligent power module, intelligent power module preparation method, and power electronic equipment
FR3061600B1 (en) 2017-01-03 2020-06-26 Stmicroelectronics (Grenoble 2) Sas ELECTRONIC DEVICE COMPRISING A GROOVED CHIP
TWI615930B (en) * 2017-03-17 2018-02-21 力成科技股份有限公司 Heat sink and chip package having the same
CN108615819B (en) * 2018-04-25 2020-02-14 云谷（固安）科技有限公司 Display panel, display panel manufacturing method and display terminal
US10879225B2 (en) * 2018-10-24 2020-12-29 Samsung Electronics Co., Ltd. Semiconductor package and method of manufacturing semiconductor package
KR102480014B1 (en) * 2018-11-23 2022-12-21 삼성전자 주식회사 Semiconductor package and method of manufacturing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5883430A (en) * 1996-06-19 1999-03-16 International Business Machines Corporation Thermally enhanced flip chip package
US6369455B1 (en) * 2000-01-04 2002-04-09 Siliconware Precision Industries Co., Ltd. Externally-embedded heat-dissipating device for ball grid array integrated circuit package
US6469380B2 (en) * 2000-11-08 2002-10-22 Citizen Watch Co., Ltd. Resin sealed semiconductor device utilizing a clad material heat sink
US8058736B2 (en) * 2006-06-09 2011-11-15 Renesas Electronics Corporation Semiconductor device having heat spreader with center opening
US9059143B2 (en) * 2010-07-28 2015-06-16 J-Devices Corporation Semiconductor device
US8581374B1 (en) * 2010-10-04 2013-11-12 Marvell International Ltd. Placing heat sink into packaging by strip formation assembly

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