CN2596547Y - Semiconductor packaging structure with radiating fin - Google Patents
Semiconductor packaging structure with radiating fin Download PDFInfo
- Publication number
- CN2596547Y CN2596547Y CN 02295126 CN02295126U CN2596547Y CN 2596547 Y CN2596547 Y CN 2596547Y CN 02295126 CN02295126 CN 02295126 CN 02295126 U CN02295126 U CN 02295126U CN 2596547 Y CN2596547 Y CN 2596547Y
- Authority
- CN
- China
- Prior art keywords
- fin
- packaging structure
- semiconductor packaging
- chip
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
The utility model relates to a semiconductor packaging structure with a heat radiating fin. A base board is provided with at least one chip and one heat radiating fin. The outer periphery of the surface of the exposing part of the heat radiating fin is additionally provided with a groove which blocks packaging colloid wrapping the outer part of the chip in the groove to prevent the packaging colloid form overflowing into the surface of the heat radiating fin. The periphery of the exposing part of the heat radiating fin can maintain uniform appearance and maintain effective heat radiating area and radiating effect.
Description
Technical field
The utility model relates to a kind of semiconductor packaging structure, particularly a kind of BGA Package (Ball Grid Array, semiconductor packaging structure BGA) with fin.
Background technology
Progress along with integrated circuit technique, the trend of electronic product level and functional promotion can reduce multifunction, high speed, high capacity, densification, lightweight, in order to reach these demands, except the promotion of integrated circuit manufacture process technological progress, the structure packing technique and the material of many novelties are developed.
Because the pin of semi-conductor packaging assembly is more and more many, the assembly integration is more and more high, and the requirement to speed is also more and more fast, make that the making volume is little, speed reaches highdensity structure arrangement soon and has been trend, add the more and more big result of consumed power of structure arrangement, cause the heat dissipation problem of structure arrangement increasingly important.In order to shorten the heat radiation approach, promote radiating effect and effective area of dissipation, conventional art is that a fin 12 is set on the substrate 10 of BGA structure arrangement, as shown in Figure 1, make the chip 14 on fin 12 covered substrates 10 surfaces, to strengthen radiating effect by this, utilize a packing colloid 16 to coat each assembly at last again and only expose this fin 12 and expose disc.
Yet, in general manufacture process, can not cover fin 12 fully for making packing colloid 16, so utilize the upper surface and the pressing mold die cavity plane engagement of fin 12, prevent that packing colloid 16 from overflowing into fin 12 surfaces.But mobile high and wayward because of packing colloid 16, make its fin 12 expose disc around still have the glue that overflows phenomenon produce, as shown in phantom in Figure 1, make it can't keep exposing around the disc outward appearance uniformly; And because of packing colloid 16 overflows into fin 12 surfaces, the area of dissipation of fin 12 is dwindled, and then influence the radiating effect of structure arrangement.
Summary of the invention
The purpose of this utility model provides a kind of semiconductor packaging structure with fin, is to set up a groove at the exposed surface of fin, and by this packing colloid is barred from the groove, overflows into fin surface effectively to prevent packing colloid.
Another purpose of the present utility model provides a kind of semiconductor packaging structure with fin, makes the exposing surface of fin can keep uniform outward appearance on every side, and the area of dissipation that is maintained fixed, to guarantee its radiating effect.
For reaching above-mentioned purpose, the utility model is to be provided with a plurality of soldered balls below a substrate, and at least one chip is then carried in the substrate top, chip and substrate is formed be electrically connected; And a fin is arranged, and it is that upwards projection formation one exposes portion, and is equipped with a groove in the portion outside of exposing, this fin is installed on upper surface of base plate and covers chip; Utilize a packing colloid to coat this chip and fin again, and packing colloid stopped by this groove, the portion of exposing of fin is exposed outside this packing colloid.
Below by the detailed description of specific embodiment and conjunction with figs., the effect of further understanding the purpose of this utility model, technology contents, characteristics and being reached.
Description of drawings
Fig. 1 has the structure cutaway view of the BGA structure arrangement of fin for tradition;
Fig. 2 is a structure cutaway view of the present utility model;
Fig. 3 is the structure cutaway view of the employed fin of the utility model;
Fig. 4 is the structure vertical view of the employed fin of the utility model.
Description of reference numerals: 10 substrates; 12 fin; 14 chips; 16 packing colloids; 20 substrates; 22 solids; 24 chips; 26 lead-in wires; 28 soldered balls; 30 fin; 302 expose portion; 304 grooves; 32 packing colloids.
Embodiment
The utility model is that the fin exposed surface at semiconductor packaging structure designs a ring-like groove, therefore makes its packing colloid can stop in this groove, avoids packing colloid to produce the glue phenomenon of overflowing, and exposes portion's area and improves its radiating effect to guarantee fin.The semiconductor packaging structure that encapsulates below by the ball bar array by a tool wire bond structure illustrates effect of the present utility model.
Fig. 2 is a structure cutaway view of the present utility model, as shown in the figure, in the semiconductor packaging structure, one substrate 20 has first surface and second surface, first surface in substrate 20 is installed semiconductor chip 24 with solid glutinous 22, this chip 24 contains electronic circuit, utilizing wire bonder to go between again 26 connects output on the chips 24 and goes into pad on contact and the substrate 20, second surface at substrate 20 also is equiped with a plurality of metal soldered balls 28, with as external contact, provide to be soldered on motherboard or other electronic installation; And a fin 30 arranged, be that upwards projection forms a disc and exposes portion 302, please also refer to Fig. 3 and shown in Figure 4, the surface of exposing portion 302 at disc is to be equipped with a circular groove 304 on every side, and the portion of exposing 302 and this groove 304 at fin 30 and top thereof are formed in one, this fin 30 is installed on the first surface of substrate 20 and covers this chip 24 by an adhesive agent, makes the portion of exposing 302 at fin 30 tops be positioned at chip 24 tops just; Outermost packing colloid 32; be to use molding compounds (molding compound); the dust head is epoxy resin (epoxy resin); coat aforesaid chip 24 and fin 30 and only expose this through casting and expose portion 302; so that mechanical protective effect to be provided, avoid chip 24 to be subjected to the external force infringement.
Wherein, in pressing mold (Transfer Molding) processing procedure, the groove 304 that outermost packing colloid 32 is exposed portion 302 outsides by fin 30 stops and only stops in the groove 304, the disc that makes packing colloid 32 can not overflow into fin 30 exposes portion 302, so the disc that fin 30 is exposed can keep circular outward appearance uniformly around exposing portion 302, influences its area of dissipation and radiating effect effectively to prevent packing colloid 32 from overflowing into fin 30 surfaces.
In addition, the fin that the utility model uses, it exposes portion except presenting the circular face shape, also can be one square face shaping.
Therefore, the utility model is set up a groove in the outside, the portion of exposing surface of fin, and by this packing colloid is barred from the groove, to prevent that effectively packing colloid from overflowing into fin surface, make the exposing surface of fin can keep uniform outward appearance on every side, and the area of dissipation that is maintained fixed, it can not covered, to guarantee the radiating effect of semiconductor packaging structure by excessive glue.
Above-described embodiment only is for technological thought of the present utility model and characteristics are described; its purpose is to make those skilled in the art can understand content of the present utility model and implements according to this; rather than be used for limiting scope of the present utility model; therefore all equalizations of doing according to the spirit that the utility model disclosed change or modify, and must be encompassed in the protection range of the present utility model.
Claims (5)
1, a kind of semiconductor packaging structure with fin is characterized in that comprising:
One substrate has first surface and second surface;
At least one chip is arranged at this substrate first surface and is electrically connected with its formation;
One fin is that upwards projection formation one exposes portion, and is equipped with a groove that around this exposes the portion surface this fin is arranged at this substrate first surface and covers this chip; And
One packing colloid coats this chip and part fin, this packing colloid is stopped by this groove, and then the portion of exposing of this fin is exposed outside this packing colloid.
2, the semiconductor packaging structure with fin as claimed in claim 1, wherein the second surface at this substrate is that a plurality of soldered balls are installed, with as external contact.
3, the semiconductor packaging structure with fin as claimed in claim 1, wherein the portion of exposing of this fin presents a circular face or one square shape.
4, the semiconductor packaging structure with fin as claimed in claim 1, wherein this fin is made of metal material.
5, the semiconductor packaging structure with fin as claimed in claim 1, wherein this fin and expose portion and this groove is formed in one.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02295126 CN2596547Y (en) | 2002-12-25 | 2002-12-25 | Semiconductor packaging structure with radiating fin |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02295126 CN2596547Y (en) | 2002-12-25 | 2002-12-25 | Semiconductor packaging structure with radiating fin |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN2596547Y true CN2596547Y (en) | 2003-12-31 |
Family
ID=33752298
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02295126 Expired - Lifetime CN2596547Y (en) | 2002-12-25 | 2002-12-25 | Semiconductor packaging structure with radiating fin |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN2596547Y (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416782C (en) * | 2004-08-20 | 2008-09-03 | 威宇科技测试封装有限公司 | Chip radiator fin-fitting method |
| CN101800208B (en) * | 2009-02-11 | 2012-02-29 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and heat radiating fin thereof |
| CN105470220A (en) * | 2015-12-09 | 2016-04-06 | 华天科技（西安）有限公司 | Cooling fin surface mount package part capable of preventing material overflow |
| CN108630637A (en) * | 2017-03-17 | 2018-10-09 | 力成科技股份有限公司 | Heat dissipation member and chip package with same |
| CN109863596A (en) * | 2019-01-22 | 2019-06-07 | 长江存储科技有限责任公司 | Integrated circuit package structure and its manufacturing method |
-
2002
- 2002-12-25 CN CN 02295126 patent/CN2596547Y/en not_active Expired - Lifetime
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100416782C (en) * | 2004-08-20 | 2008-09-03 | 威宇科技测试封装有限公司 | Chip radiator fin-fitting method |
| CN101800208B (en) * | 2009-02-11 | 2012-02-29 | 日月光半导体制造股份有限公司 | Semiconductor packaging structure and heat radiating fin thereof |
| CN105470220A (en) * | 2015-12-09 | 2016-04-06 | 华天科技（西安）有限公司 | Cooling fin surface mount package part capable of preventing material overflow |
| CN108630637A (en) * | 2017-03-17 | 2018-10-09 | 力成科技股份有限公司 | Heat dissipation member and chip package with same |
| CN109863596A (en) * | 2019-01-22 | 2019-06-07 | 长江存储科技有限责任公司 | Integrated circuit package structure and its manufacturing method |
| CN109863596B (en) * | 2019-01-22 | 2020-05-26 | 长江存储科技有限责任公司 | Integrated circuit package structure and manufacturing method thereof |
| TWI746939B (en) * | 2019-01-22 | 2021-11-21 | 大陸商長江存儲科技有限責任公司 | Integrated circuit packaging structure and manufacturing method thereof |
| US11476173B2 (en) | 2019-01-22 | 2022-10-18 | Yangtze Memory Technologies Co., Ltd. | Manufacturing method of integrated circuit packaging structure |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| ASS | Succession or assignment of patent right |
Owner name: WEIYU SEMICONDUCTOR (HONG KONG) LTD. Free format text: FORMER OWNER: LIWEI SCIENCE AND TECHNOLOGY CO., LTD. Effective date: 20041210 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20041210 Address after: Hongkong Special Administrative Region of China Patentee after: WEIYU SEMICONDUCTOR (HONGKONG) Co.,Ltd. Address before: Taiwan, China Patentee before: VATE TECHNOLOGY CO.,LTD. |
|
| ASS | Succession or assignment of patent right |
Owner name: ASE (WEIHAI) INC. Free format text: FORMER OWNER: ADVANCED SEMICONDUCTOR ENGINEERING (HONG KONG) CO., LTD. Effective date: 20111201 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| C56 | Change in the name or address of the patentee |
Owner name: ADVANCED SEMICONDUCTOR ENGINEERING (HONG KONG) CO. Free format text: FORMER NAME: WEIYU SEMICONDUCTOR (HONG KONG) CO., LTD. |
|
| COR | Change of bibliographic data |
Free format text: CORRECT: ADDRESS; FROM: HONG KONG, CHINA TO: 264205 WEIHAI, SHANDONG PROVINCE |
|
| CP01 | Change in the name or title of a patent holder |
Address after: Hongkong Special Administrative Region of China Patentee after: Advanced packaging and testing (Hongkong) Co.,Ltd. Address before: Hongkong Special Administrative Region of China Patentee before: WEIYU SEMICONDUCTOR (HONGKONG) Co.,Ltd. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20111201 Address after: 264205 No. 16-1, Hainan Road, export processing zone, Weihai economic and Technological Development Zone, Shandong, China Patentee after: RIYUEGUANG SEMICONDUCTOR(WEIHAI) Co.,Ltd. Address before: Hongkong Special Administrative Region of China Patentee before: Advanced packaging and testing (Hongkong) Co.,Ltd. |
|
| C17 | Cessation of patent right | ||
| CX01 | Expiry of patent term |
Expiration termination date: 20121225 Granted publication date: 20031231 |