US20100207224A1 - Solid-state imaging device having penetration electrode formed in semiconductor substrate - Google Patents

Solid-state imaging device having penetration electrode formed in semiconductor substrate Download PDF

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Publication number
US20100207224A1
US20100207224A1 US12/629,322 US62932209A US2010207224A1 US 20100207224 A1 US20100207224 A1 US 20100207224A1 US 62932209 A US62932209 A US 62932209A US 2010207224 A1 US2010207224 A1 US 2010207224A1
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electrode
solid
imaging device
state imaging
semiconductor substrate
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US12/629,322
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Mariko Saito
Ikuko Inoue
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Toshiba Corp
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Assigned to KABUSHIKI KAISHA TOSHIBA reassignment KABUSHIKI KAISHA TOSHIBA ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INOUE, IKUKO, SAITO, MARIKO
Publication of US20100207224A1 publication Critical patent/US20100207224A1/en
Priority to US13/490,768 priority Critical patent/US9136291B2/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14618—Containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H01L2224/0237—Disposition of the redistribution layers
    • H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/1462—Coatings
    • H01L27/14621—Colour filter arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14625—Optical elements or arrangements associated with the device
    • H01L27/14627—Microlenses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H01L27/14636—Interconnect structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/02002—Arrangements for conducting electric current to or from the device in operations

Definitions

  • the present invention relates to a solid-state imaging device having a penetration electrode formed in a semiconductor substrate, for example, a camera module.
  • a solid-state imaging device having a semiconductor image sensor is also required to be miniaturized.
  • a penetration electrode in which a through-hole is formed to extend from a rear surface side of a semiconductor chip on which a semiconductor image sensor is formed to an internal electrode on a front surface side so as to electrically connect an electrode on the rear surface side to the internal electrode on the front surface side through a conductor layer buried in the through-hole.
  • a conventional method of forming a penetration electrode has the following structure, for example.
  • a through-hole is formed to extend from a rear surface side of a silicon substrate to a front surface side. Thereafter, an insulating film is formed in the through-hole. After the through-hole is extended to the insulating film and an insulating interlayer which are present between a bottom surface of the through-hole and an internal electrode, a conductor layer (penetration electrode) is buried in the through-hole (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2007-53149).
  • the through-hole is formed in the insulating interlayer, a small-size through-hole having a diameter ranging from about 20 to 30 ⁇ m is formed. For this reason, a resist film thickness must be made large, and the manufacturing cost increases because a long developing time is required to pattern the resist.
  • the insulating film formed on the silicon substrate in the through-hole is damaged by plasma asher used in removal of the resist, and a short circuit occurs between the silicon substrate and the conductor layer.
  • a solid-state imaging device comprising: an imaging element formed on a first main surface of a semiconductor substrate; an external terminal formed on a second main surface facing the first main surface of the semiconductor substrate; an insulating film formed in a through-hole formed in the semiconductor substrate; a penetration electrode formed on the insulating film in the through-hole and electrically connected to the external terminal; a first insulating interlayer formed on the first main surface of the semiconductor substrate and the penetration electrode; a first electrode formed on the first insulating interlayer; and a first contact plug formed in the first insulating interlayer between the penetration electrode and the first electrode to electrically connect the penetration electrode and the first electrode to each other.
  • FIG. 1 is a sectional view showing a configuration of a camera module according to an embodiment of the present invention
  • FIG. 2 is an enlarged sectional view of portions of a silicon semiconductor substrate and a glass substrate in the camera module according to the embodiment
  • FIG. 3 is an enlarged sectional view of a penetration electrode and an electrode pad portion in the camera module according to the embodiment
  • FIG. 4 is a plan view of the penetration electrode and the electrode pad portion when being viewed from a pad opening side in the camera module according to the embodiment;
  • FIG. 5 is a sectional view of a first step showing a method of manufacturing the penetration electrode in the camera module according to the embodiment
  • FIG. 6 is a sectional view of a second step showing the method of manufacturing the penetration electrode in the camera module according to the embodiment
  • FIG. 7 is a sectional view of a third step showing the method of manufacturing the penetration electrode in the camera module according to the embodiment.
  • FIG. 8 is a sectional view of a fourth step showing the method of manufacturing the penetration electrode in the camera module according to the embodiment.
  • FIG. 9 is a sectional view of a fifth step showing the method of manufacturing the penetration electrode in the camera module according to the embodiment.
  • FIG. 10 is a sectional view of a sixth step showing the method of manufacturing the penetration electrode in the camera module according to the embodiment.
  • a camera module is exemplified as a solid-state imaging device.
  • the same reference numerals as in all the drawings denote the same parts in the drawings.
  • FIG. 1 is a sectional view showing a configuration of a camera module according to an embodiment of the present invention.
  • an optically transparent substrate for example, a glass substrate 12 is formed through-an adhesive agent 11 .
  • An infrared (IR) cut filter 14 is arranged on the glass substrate 12 through an adhesive agent 13 , and a lens holder 17 including an imaging lens 16 is arranged on the IR cut filter 14 through an adhesive agent 15 .
  • an external terminal for example, a solder ball 18 is formed on a solder ball 18 .
  • a light-shielding and electromagnetic shield 19 is arranged around the silicon semiconductor substrate 10 and the glass substrate 12 , and the light-shielding and electromagnetic shield 19 is caused to adhere to the lens holder 17 by an adhesive agent 20 . With this structure, a camera module 100 is formed.
  • the camera module 100 is directly mounted (chip-on-board [COB]) on a mounting substrate 200 consisting of, for example, a resin or ceramics through the solder ball 18 .
  • FIG. 2 is an enlarged sectional view of portions of a silicon substrate and a glass substrate in the camera module according to the embodiment.
  • the camera module has an imaging pixel unit in which an imaging element 21 is formed and a peripheral circuit unit which processes a signal output from the imaging pixel unit.
  • the imaging pixel unit of the camera module has the following configuration.
  • element isolation insulating layers for example, shallow trench isolation [STI]
  • element regions isolated by the element isolation insulating layers 22 are formed on the first main surface of the silicon semiconductor substrate 10 .
  • the imaging element 21 including a photodiode and a transistor is formed.
  • An insulating interlayer 23 is formed on the first main surface on which the imaging element 21 is formed, and an insulating interlayer 24 is formed on the insulating interlayer 23 .
  • an interconnection 25 is formed in the insulating interlayer 24 .
  • a passivation film 26 is formed, and a base layer 27 is formed on the passivation film 26 .
  • color filters 28 are formed to correspond the imaging elements 21 .
  • an overcoat 29 is formed on the color filter 28 .
  • microlenses 30 are formed to correspond to the imaging elements 21 (or color filters 28 ).
  • a cavity 31 is formed above the microlenses 30 , and an optically transparent support substrate (transparent substrate), for example, the glass substrate 12 is arranged above the cavity 31 .
  • the insulating interlayer 23 is formed on the first main surface of the silicon semiconductor substrate 10 , and an internal electrode 32 is formed on the insulating interlayer 23 .
  • a contact plug 34 which electrically connects these electrodes to each other is formed.
  • the contact plug 34 is formed in a region which does not overlap the through-hole when being viewed from a direction perpendicular to the first main surface.
  • the element surface electrode 33 is used to apply a voltage and read a signal through, for example, the contact plug 34 and the internal electrode 32 . For example, in a die sort test, a test probe is brought into contact with the element surface electrode 33 .
  • a through-hole extending from a second main surface to the first main surface, i.e., the second main surface to the insulating interlayer 23 is formed.
  • An insulating film 35 is formed on a side surface of the through-hole and the second main surface.
  • a conductor layer (penetration electrode) 36 is formed on an internal surface of the through-hole, i.e., on the insulating film 35 and the insulating interlayer 23 .
  • a conductor layer (penetration electrode) 36 is formed on an internal surface of the through-hole.
  • a contact plug 37 which electrically connects the conductor layer 36 and the internal electrode 32 to each other is formed.
  • the contact plug 37 is arranged in a region in which the conductor layer 36 and the insulating interlayer 23 are in contact with each other when being viewed from a direction perpendicular to the first main surface.
  • the internal electrode 32 is electrically connected to a peripheral circuit (not shown) formed in the imaging elements 21 or the peripheral circuit unit. In this manner, the penetration electrode formed in the through-hole electrically connects the solder ball 18 and the imaging elements 21 or the peripheral circuit to each other.
  • a protecting film for example, a solder resist 38 is formed on the conductor layer 36 and the insulating film 35 on the second main surface. Furthermore, on the second main surface, the solder resist 38 on the conductor layer 36 is partially bored, and the solder ball 18 is formed on the exposed conductor layer 36 .
  • the conductor layer 36 is formed on the element surface electrode 33 .
  • the base layer 27 is formed on the passivation film 26 , and the overcoat 29 is formed on the base layer 27 .
  • a styrene resin layer 39 is formed on the overcoat 29 .
  • the passivation film 26 , the base layer 27 , the overcoat 29 , and the styrene resin layer 39 which are arranged on the element surface electrode 33 are bored to form a pad opening 40 .
  • the glass substrate 12 is formed through the adhesive agent 11 .
  • the adhesive agent 11 is patterned and is not arranged on the imaging elements 21 (on the microlenses 30 ).
  • the solder resist 38 consists of, for example, a phenolic resin, a polyimide resin, an amine resin, or the like.
  • solder ball 18 for example, Sn—Pb (eutectic) or 95Pb—Sn (high-lead high-melting-point solder) is used.
  • Pb-free solder Sn—Ag, Sn—Cu, Sn—Ag—Cu, or the like is used.
  • FIG. 3 is an enlarged sectional view of the penetration electrode and the electrode pad portion in the camera module.
  • FIG. 4 is a plan view of the penetration electrode and the electrode portion when being viewed from a pad opening side.
  • FIGS. 3 and 4 show the penetration electrode and the electrode portion up to the passivation film 26 formed on the insulating interlayer 24 , and do not show members formed on the passivation film 26 .
  • a penetration electrode 36 extending from the second main surface of the silicon semiconductor substrate 10 to the first main surface thereof is formed.
  • the internal electrode 32 is formed on the first main surface of the silicon semiconductor substrate 10 through the insulating interlayer 23 .
  • the contact plug 37 is formed in the insulating interlayer 23 between the conductor layer 36 and the internal electrode 32 .
  • the contact plug 37 is arranged in a region in which the penetration electrode 36 and the insulating interlayer 23 are in contact with each other when viewed from a direction perpendicular to the first main surface, i.e., when viewed from the pad opening side.
  • reference numeral 41 denotes a region in which the penetration electrode 36 and the insulating interlayer 23 are in contact with each other
  • reference numeral 42 denotes an outer shape of the through-hole on the first main surface.
  • FIGS. 5 to 10 are sectional views of steps showing the method of manufacturing a penetration electrode in the camera module.
  • the insulating interlayer 23 is formed on the first main surface of the silicon semiconductor substrate 10 .
  • the contact plug 37 is formed on the insulating interlayer 23
  • the internal electrode 32 is formed on the contact plug 37 and the insulating interlayer 23 .
  • the silicon semiconductor substrate 10 and the internal electrode 32 are connected to each other through the contact plug 37 .
  • the contact plug 37 is formed as follows. After a hole is formed in the insulating interlayer 23 by a photolithography process, a metal material, for example, tungsten (W) is deposited on the insulating interlayer 23 to bury the hole with tungsten.
  • the internal electrode 32 for example, an aluminum (Al) film or a copper (Cu) film is formed on the insulating interlayer 23 .
  • a through-hole 43 is formed in the silicon semiconductor substrate 10 .
  • the insulating film 35 is formed on the internal surface of the through-hole 43 , i.e., on the side surface and the bottom surface (surface of the insulating interlayer 23 ) of the through-hole 43 .
  • a resist 44 is coated on the insulating film 35 , and, as shown in FIG. 9 , the resist 44 is patterned by a photolithography process.
  • the insulating film 35 which is not protected by the resist 44 is removed. More specifically, the insulating film 35 on the insulating interlayer 23 on which the contact plug 37 is formed is removed. Thereafter, after the resist 44 is peeled, as shown in FIG. 3 , the conductor layer 36 is formed on the insulating film 35 , the contact plug 37 , and the insulating interlayer 23 . With the above operations, a penetration electrode (conductor layer) connected to the internal electrode 32 through the contact plug 37 is manufactured.
  • the penetration electrode (conductor layer) 36 and the internal electrode 32 are connected by the contact plug 37 to make it possible to omit a process of forming a through-hole in the insulating interlayer 23 on the first main surface.
  • the thickness of the resist 44 can be reduced, a patterning time for the resist 44 can be shortened, and a manufacturing cost can be reduced.
  • the resist 44 can be thinned, damage to the insulating film 35 by plasma asher used when the resist 44 is peeled can be reduced. In this manner, short circuits occurring between the penetration electrode 36 and the silicon semiconductor substrate 10 can be reduced.
  • an electrode may be arranged in at least one layer.
  • one electrode pad or a plurality of electrode pads may be arranged in the insulating interlayer 24 between the internal electrode 32 and the element surface electrode 33 .
  • three interconnection layers 25 are formed in the insulating interlayer 24 .
  • an opening end position of the passivation film 26 is different from opening end positions of the base layer 27 , the overcoat 29 , the styrene resin layer 39 to form a step.
  • the pad opening 40 may be formed such that the opening end positions are matched with each other.
  • a step may be formed but need not be formed between the opening end position of the overcoat 29 and the opening end position of the styrene resin layer 39 .
  • openings are formed in the passivation film 26 , the base layer 27 , the overcoat 29 , and the styrene resin layer 39 to obtain the pad opening 40 .
  • a structure in which the openings in the films and the pad opening are not formed may be used.
  • the embodiment of the present invention provides a solid-state imaging device which can reduce defects due to short-circuit occurring between a silicon substrate and a conductor layer in a penetration electrode formed in a through-hole in a silicon substrate.

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  • Engineering & Computer Science (AREA)
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  • Power Engineering (AREA)
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  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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JP2009031430A JP5178569B2 (ja) 2009-02-13 2009-02-13 固体撮像装置

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US20100327383A1 (en) * 2009-06-29 2010-12-30 Hayasaki Yuko Semiconductor device including through-electrode and method of manufacturing the same
US20130141626A1 (en) * 2010-08-23 2013-06-06 Canon Kabushiki Kaisha Image pickup device, image pickup module, and camera
US20140326486A1 (en) * 2013-05-02 2014-11-06 Hong Fu Jin Precision Industry (Shenzhen) Co., Ltd. Printed circuit board
US20220217290A1 (en) * 2018-06-08 2022-07-07 Sony Semiconductor Solutions Corporation Imaging device
US11699653B2 (en) 2019-08-08 2023-07-11 Canon Kabushiki Kaisha Semiconductor apparatus and equipment

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JP5958732B2 (ja) * 2011-03-11 2016-08-02 ソニー株式会社 半導体装置、製造方法、および電子機器
US9219091B2 (en) * 2013-03-12 2015-12-22 Optiz, Inc. Low profile sensor module and method of making same
TWI600125B (zh) * 2015-05-01 2017-09-21 精材科技股份有限公司 晶片封裝體及其製造方法
TWI692859B (zh) * 2015-05-15 2020-05-01 日商新力股份有限公司 固體攝像裝置及其製造方法、以及電子機器
CN106365110A (zh) * 2015-07-24 2017-02-01 上海丽恒光微电子科技有限公司 探测传感器及其制备方法
CN115697879A (zh) 2020-06-09 2023-02-03 三菱电机株式会社 电梯的轿厢门装置

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US9136291B2 (en) 2015-09-15
TW201104847A (en) 2011-02-01

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