US20090242133A1 - Electrode structure and substrate processing apparatus - Google Patents
Electrode structure and substrate processing apparatus Download PDFInfo
- Publication number
- US20090242133A1 US20090242133A1 US12/407,109 US40710909A US2009242133A1 US 20090242133 A1 US20090242133 A1 US 20090242133A1 US 40710909 A US40710909 A US 40710909A US 2009242133 A1 US2009242133 A1 US 2009242133A1
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- substrate
- electrode
- wafer
- processing
- edge portion
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- 238000012545 processing Methods 0.000 title claims abstract description 124
- 239000000758 substrate Substances 0.000 title claims abstract description 70
- 235000012431 wafers Nutrition 0.000 description 68
- 239000007789 gas Substances 0.000 description 27
- 238000001020 plasma etching Methods 0.000 description 15
- 238000005530 etching Methods 0.000 description 14
- 150000001768 cations Chemical class 0.000 description 8
- 230000000052 comparative effect Effects 0.000 description 7
- 239000002826 coolant Substances 0.000 description 5
- 238000010276 construction Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000000470 constituent Substances 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012546 transfer Methods 0.000 description 3
- 239000001307 helium Substances 0.000 description 2
- 229910052734 helium Inorganic materials 0.000 description 2
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 2
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 2
- 239000000498 cooling water Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012530 fluid Substances 0.000 description 1
- -1 for example Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32137—Radio frequency generated discharge controlling of the discharge by modulation of energy
- H01J37/32155—Frequency modulation
- H01J37/32165—Plural frequencies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
- H01J37/32082—Radio frequency generated discharge
- H01J37/32091—Radio frequency generated discharge the radio frequency energy being capacitively coupled to the plasma
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32431—Constructional details of the reactor
- H01J37/32532—Electrodes
- H01J37/32541—Shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Definitions
- the present invention relates to an electrode structure and a substrate processing apparatus, and more particularly, to an electrode structure disposed inside a processing chamber of a substrate processing apparatus and connected to a DC power source.
- a substrate processing apparatus for performing plasma processing on substrates includes a processing chamber in which a wafer is housed, a mounting table which is disposed inside the processing chamber and on which the wafer is mounted, a shower head that supplies a processing gas to a processing space inside the processing chamber.
- the mounting table is connected with a high-frequency power supply and applies high-frequency electric power to the processing space.
- the processing gas supplied to the processing space is excited by the high-frequency electric power, whereby a plasma (cations and electrons) is produced.
- a plasma distribution in the processing space greatly affects on results of plasma processing on wafers, it is preferable to positively control the plasma distribution.
- a DC voltage is applied to the shower head.
- a DC power source is connected to a circular disk-shaped ceiling electrode plate, which is a component part of the shower head and exposed to the processing space.
- the shower head When applied with a negative DC voltage, the shower head only draws cations in the plasma. Since a DC voltage has an electric potential remaining constant with elapse of time unlike a high frequency voltage, cations are continuously drawn into the shower head. The cations drawn into the shower head cause secondary electrons to be emitted from constituent atoms of the shower head. As a result, the electron density in the processing space increases at a part facing the shower head (see, for example, US Patent Application Publication No. 20060066247A1 (corresponding to Japanese Laid-open Patent Publication No. 2006-270019)).
- the electron density distribution sometimes becomes ununiform due to affections of the shape of the processing chamber, etc.
- the ceiling electrode plate comprised of a single electrically conductive plate
- the electron density in the processing space increases at all the parts corresponding to the shower head, making it impossible to eliminate the problem of uneven electron density distribution.
- the electron density in the processing space decreases at a part facing a circumferential edge portion of a wafer, posing a problem that the etching rate in etching processing decreases at the circumferential edge portion of the wafer as compared to that at a central portion thereof.
- the present invention provides an electrode structure and a substrate processing apparatus, which are capable of adequately increasing an electron density in a processing space at a part facing a circumferential edge portion of a substrate.
- an electrode structure disposed inside a processing chamber of a substrate processing apparatus for performing plasma processing on a substrate, so as to face the substrate placed on a mounting table in the processing chamber, which comprises an inner electrode disposed to face a central portion of the substrate, and an outer electrode disposed to face a circumferential edge portion of the substrate, wherein the inner electrode is connected to a first DC power source, the outer electrode is connected to a second DC power source, and the outer electrode has a first surface thereof extending parallel to the substrate and a second surface thereof obliquely extending relative to the first surface of the outer electrode.
- the outer electrode facing a circumferential edge portion of a substrate is connected with the second DC power source and applied with a DC voltage.
- the outer electrode draws cations in a plasma and emits secondary electrons.
- the outer electrode has its first surface extending parallel to the substrate and its second surface obliquely extending relative to the first surface, and secondary electrons are emitted from the first and second surfaces.
- the first and second surfaces of the outer electrode can be directed toward the circumferential edge portion of the substrate.
- the first and second surfaces are directed to the circumferential edge portion of the substrate, and therefore, secondary electrons emitted from the first surface and those emitted from the second surface are superimposed on one another at a part right above the circumferential edge portion of the substrate. As a result, it is possible to reliably and adequately increase the electron density right above the circumferential edge portion of the substrate.
- a substrate processing apparatus including a processing chamber for housing a substrate, a mounting table disposed inside the processing chamber and adapted to place the substrate thereon, and an electrode structure disposed inside the processing chamber so as to face the substrate placed on the mounting table, the substrate processing being adapted to perform plasma processing on the substrate, wherein the electrode structure includes an inner electrode thereof disposed to face a central portion of the substrate and an outer electrode thereof disposed to face a circumferential edge portion of the substrate, the inner electrode is connected to a first DC power source and the outer electrode is connected to a second DC power source, and the outer electrode has a first surface thereof extending parallel to the substrate and a second surface thereof obliquely extending relative to the first surface of the outer electrode.
- secondary electrons emitted from the second surface of the outer electrode are superimposed on the secondary electrons emitted from the first surface of the outer electrode at a part in the processing space facing a circumferential edge portion of a substrate, making it possible to adequately increase the electron density in the processing space at the part facing the circumferential edge portion of the substrate.
- FIG. 1 is a section view schematically showing the construction of a substrate processing apparatus according to one embodiment of this invention
- FIG. 2 is a fragmentary enlarged section view schematically showing the construction of and around an outer electrode of an upper electrode shown in FIG. 1 ;
- FIG. 3 is a graph showing a relation between outer electrode surface area and etching rate at a circumferential edge portion of a wafer
- FIG. 4 is a graph showing the rate of increase in etching rate observed when a value of DC voltage applied to the outer electrode is increased.
- FIG. 5 is a graph showing relation between outer electrode surface area and etching rate at a circumferential edge portion of a wafer in example 1 of this invention and comparative examples 1 and 2.
- FIG. 1 schematically shows in cross section the construction of a substrate processing apparatus according to one embodiment of this invention
- FIG. 2 schematically shows in fragmentary enlarged view the construction of and around an outer electrode of an upper electrode in FIG. 1 .
- the substrate processing apparatus is adapted to perform RIE (reactive ion etching) processing on semiconductor wafers as substrates by using a plasma.
- RIE reactive ion etching
- the substrate processing apparatus 10 includes a cylindrical processing chamber 11 and a columnar susceptor 12 disposed therein and serving as a mounting table on which is placed a semiconductor wafer (hereinafter simply referred to as wafer) W having a diameter, e.g., of 300 mm.
- wafer semiconductor wafer
- An exhaust passage 13 is defined by an inner side wall of the processing chamber 11 and a side surface of the susceptor 12 and functions as a flow passage through which a gas in a processing space S, described later, is exhausted to the outside of the processing chamber 11 .
- An exhaust plate (exhaust ring) 14 is disposed in the middle of the exhaust passage 13 .
- the exhaust plate 14 is a plate-like member formed with a number of through holes and functions as a partition plate by which the processing chamber 11 is divided into an upper part and a lower part.
- reaction chamber the upper part
- exhaust chamber the lower part
- exhaust pipes 17 , 18 To the lower part (hereinafter referred to as exhaust chamber (manifold)) 16 of the processing chamber 11 are connected exhaust pipes 17 , 18 through which a gas in the processing chamber 11 is exhausted.
- the exhaust plate 14 catches or reflects the plasma generated in the reaction chamber 15 to prevent leakage of the plasma to the manifold 16 .
- the exhaust pipe 17 is connected to a TMP (turbo molecular pump), not shown, and the exhaust pipe 18 is connected to a DP (dry pump), not shown.
- TMP turbo molecular pump
- DP dry pump
- These pumps vacuum and depressurize the inside of the processing chamber 11 .
- the DP depressurizes the inside of the chamber 11 from atmospheric pressure to a medium vacuum (for example, not higher than 1.3 ⁇ 10 Pa (0.1 Torr)), and the TMP cooperates with the DP to depressurize the inside of the chamber 11 to a high vacuum (for example, not higher than 1.3 ⁇ 10 ⁇ 3 Pa (1.0 ⁇ 10 ⁇ 5 Torr)) which is lower in pressure than the medium vacuum.
- the pressure within the processing chamber 11 is controlled by an APC valve (not shown).
- the susceptor 12 inside the processing chamber 11 is connected via a first matcher 21 to a first high-frequency power supply 19 and also connected via a second matcher 22 to a second high-frequency power supply 20 .
- the first high-frequency power supply 19 applies high-frequency electric power of a relatively high frequency, e.g., 60 MHz, to the susceptor 12
- the second high-frequency power supply 20 applies high-frequency electric power of a relatively low frequency, e.g., 2 MHz, to the susceptor 12 .
- the susceptor 12 functions as a lower electrode that applies high-frequency power to the processing space S defined between the susceptor 12 and a shower head 30 described later.
- An electrostatic chuck 24 made of a disk-shaped insulating member and having an electrostatic electrode plate 23 incorporated therein is disposed on the susceptor 12 .
- a wafer W is mounted on the electrostatic chuck 24 when it is placed on the susceptor 12 .
- a DC power supply 25 is electrically connected to the electrostatic electrode plate 23 in the electrostatic chuck 24 .
- a positive DC voltage is applied to the electrode plate 23
- a negative electrical potential is generated on a surface of the wafer W on the side of the electrostatic chuck 24 (hereinafter referred to as the rear surface)
- a potential difference is produced between the electrode plate 23 and the rear surface of the wafer W. Due to the potential difference, the wafer W is attracted to and held by the electrostatic chuck 24 through a Coulomb force or a Johnsen-Rahbek force.
- An annular focus ring 26 is disposed on the susceptor 12 such as to surround the wafer W held by the susceptor.
- the focus ring 26 is made of a conductive member, e.g., silicon, and converges plasma toward the surface of the wafer W to improve the efficiency of RIE processing.
- An annular coolant unit 27 is provided inside the susceptor 12 and extends circumferentially of the susceptor.
- a low temperature coolant for example, cooling water or a Galden fluid (registered trademark) is supplied from a chiller unit (not shown) via a coolant pipe 28 into the coolant chamber 27 for circulation.
- the susceptor 12 is cooled by the low temperature coolant and cools the wafer W and the focus ring 26 via the electrostatic chuck 24 .
- a plurality of heat-transfer gas feed holes 29 of a gas feed pipe are opened to that part of the upper surface of the electrostatic chuck 24 (hereinafter referred to as the suction surface) by which the wafer W is attracted and held.
- Helium (He) gas as a heat transfer gas, is supplied from the gas feed holes 29 to a gap between the suction surface of the electrostatic chuck 24 and the rear surface of the wafer W.
- the helium gas supplied to the gap efficiently transfers heat of the wafer W to the electrostatic chuck 24 .
- the shower head 30 is disposed at a ceiling portion of the processing chamber 11 .
- the shower head 30 includes an upper electrode 31 (electrode structure) disposed to face the wafer W placed on the susceptor 12 (hereinafter referred to as the placed wafer W) so as to be exposed to the processing space S, an insulating plate 32 made of an insulative member, and an electrode support member 33 that supports via the insulating plate 32 the upper electrode 31 hanging therefrom.
- the upper electrode 31 , the insulating plate 32 , and the electrode support member 33 are stacked one upon another in this order.
- the electrode support member 33 has a buffer chamber 39 formed therein.
- the buffer chamber 39 defines a columnar space, which is divided into inner and outer buffer chambers 39 a , 39 b by an annular sealing member, e.g., an O-ring 40 .
- a processing gas introduction pipe 41 is connected to the inner buffer chamber 39 a , and a processing gas introduction pipe 42 is connected to the outer buffer chamber 39 b .
- a processing gas is introduced into the inner buffer chamber 39 a via the gas introduction pipe 41
- a processing gas is introduced into the outer buffer chamber 39 b via the gas introduction pipe 42 .
- the processing gas introduction pipes 41 , 42 each include a mass flow controller (MFC), not shown. Therefore, amounts of flow of processing gases introduced into the inner and outer buffer chambers 39 a , 39 b are controlled independently of each other.
- the buffer chamber 39 is communicated with the processing space S via gas holes 43 formed in the electrode support member 33 , gas holes 33 formed in the insulating plate 32 , and gas holes 36 formed in the upper electrode 31 .
- the processing gases introduced into the inner and outer buffer chambers 39 a , 39 b are supplied to the processing space S. At that time, the amounts of flow of processing gases introduced into the inner and outer buffer chambers 39 a , 39 b are adjusted, whereby a distribution of processing gases in the processing space S is controlled.
- the shower head 30 supplies processing gases into the processing space S
- the first high-frequency power supply 19 applies high-frequency power of 60 MHz to the processing space S via the susceptor 12
- the second high-frequency power supply 20 applies high-frequency power of 2 MHz to the susceptor 12 .
- the processing gases are excited by the high-frequency power of 60 MHz and converted into plasma.
- the high-frequency power of 2 MHz produces a bias voltage on the susceptor 12 , and therefore cations or electrons in the plasma are drawn into the surface of the placed wafer W, whereby RIE processing is performed on the wafer W.
- an upper electrode is divided into inner and outer electrodes respectively facing a central portion and a circumferential edge portion of a wafer, and DC voltages of negative polarity are independently applied to the inner and outer electrodes.
- a DC voltage of a value different from that applied to the inner electrode is applied to the outer electrode to thereby independently control the electron density in the processing space at parts facing the outer and inner electrodes.
- the present inventors et al. conducted experiments on RIE processing and had knowledge that the electron density in the processing space at a part facing an opposite surface of the outer electrode (hereinafter referred to as the part facing the outer electrode) increased with the increase in surface area of that surface of the outer electrode facing the processing space (hereinafter referred to as the outer electrode surface area), resulting in increase in etching rate at a circumferential edge portion of the wafer (see FIG. 3 ).
- the present inventors et al. also had knowledge that the electron density at the part facing the outer electrode increased with the increase in a value of DC voltage applied to the outer electrode, resulting in increase in etching rate at the circumferential edge portion of the wafer. Specifically, it was confirmed that the etching rate at the circumferential edge portion of the wafer increased by about 7% when an absolute value of DC voltage applied to the outer electrode was increased from 300 volts to 900 volts, with the DC voltage applied to the inner electrode kept at an absolute value of 300 volts (see FIG. 4 ).
- the upper electrode 31 of the substrate processing apparatus 10 has its inner electrode 34 facing a central portion of the placed wafer W and its outer electrode 35 arranged to surround the inner electrode 34 and facing a circumferential edge portion of the placed wafer W, and the outer electrode 35 has a first secondary electron emission surface 35 a (first surface) thereof extending parallel to the place wafer W and a second secondary electron emission surface 35 b (second surface) thereof obliquely extending relative to the first secondary electron emission surface 35 a toward the placed wafer W.
- the first and second secondary electron emission surfaces 35 a , 35 b are directed to the circumferential edge portion of the placed wafer W.
- the inner electrode 34 is made of a circular disk shaped member having a diameter, e.g., of 300 mm, and is formed with a number of gas holes 36 extending in the thickness direction of the inner electrode 34 .
- the outer electrode 35 is an annular member having an outer diameter, e.g., of 380 mm and an inner diameter, e.g., of 300 mm.
- the inner and outer electrodes 34 , 35 are each made of a conductive or semiconductor material, e.g., single crystal silicon.
- First and second DC power sources 37 , 38 are respectively connected to the inner and outer electrode 34 , of the upper electrode 31 , and DC voltages are independently applied to the electrodes 34 , 35 .
- the inner electrode 34 is made of a disk-shaped member as described above, only that surface of the inner electrode 34 extending parallel to the placed wafer W is exposed to the processing space S. Therefore, the secondary electrons emitted from the surface of the inner electrode 34 are uniformly distributed from a central portion to a circumferential edge portion of the wafer W. Thus, RIE processing is promoted on the entire surface of the placed wafer W.
- both the first and second secondary electron emission surfaces 35 a , 35 b of the outer electrode 35 are directed to the circumferential edge portion of the placed wafer W. Therefore, secondary electrons emitted from the first and second secondary electron emission surface 35 a , 35 b are superimposed on one another at locations right above the circumferential edge portion of the place wafer W. As a result, it is possible to adequately increase the electron density right above the circumferential edge portion of the placed wafer W, and RIE processing on the circumferential edge portion of the placed wafer W is promoted.
- Operations of component parts of the substrate processing apparatus 10 are controlled by a CPU of a control unit (not shown) of the substrate processing apparatus 10 .
- the second DC power source 38 is connected to the outer electrode 35 facing the circumferential edge portion of the placed wafer W, and a DC voltage is applied to the outer electrode 35 .
- the outer electrode 35 draws cations in the plasma and emits secondary electrons, whereby the electron density in the processing space S right above the circumferential edge portion of the placed wafer W can be increased.
- the outer electrode 35 has its first secondary electron emission surface 35 a extending parallel to the placed wafer W and its second secondary electron emission surface 35 b extending obliquely relative to the electron emission surface 35 a toward the placed wafer W, and secondary electrons are emitted from the electron emission surfaces 35 a , 35 b .
- both the surfaces 35 a , 35 b are directed to the circumferential edge portion of the placed wafer W, the electron density right above the circumferential edge portion of the placed wafer W can adequately be increased, whereby RIE processing on the circumferential edge portion of the wafer W can be promoted.
- the electron density right above the circumferential edge portion of the placed wafer W can be adequately increased, without the need of increasing the area of the surface of the outer electrode 35 facing the wafer W.
- both the first and second secondary electron emission surfaces 35 a , 35 b are directed to the circumferential edge portion of the placed wafer W.
- the second secondary electron emission surface 35 b may not be directed to the circumferential edge portion of the placed wafer W.
- the electron emission surface 35 b may extend perpendicular to the first secondary electron emission surface 35 a . Even in that case, the electron density at a part facing the circumferential edge portion of the placed wafer W can be adequately increased since secondary electrons emitted from the electron emission surfaces 35 a , 35 are superimposed on one another in the part in the processing space S facing the circumferential edge portion of the placed wafer W.
- the second secondary electron emission surface 35 b may not be a flat surface, but may be a parabolic surface directed to the circumferential edge portion of the placed wafer W. In that case, it is possible to emit secondary electrons from the electron emission surface 35 b concentratedly toward the circumferential edge portion of the placed wafer W, whereby the electron density right above the circumferential edge portion of the wafer W can further be adequately increased.
- the substrate subjected to etching processing is a semiconductor wafer W.
- the substrate subjected to etching processing is not limited thereto, and may be, for example, a glass substrate for a display such as LCD (liquid crystal display) or FPD (flat panel display).
- the present inventors performed RIE processing on a placed wafer W by using the substrate processing apparatus 10 , and measured the etching rate by the RIE processing at a circumferential edge portion of the wafer W. The result is shown by a black-circle mark in a graph of FIG. 5 .
- the present inventors prepared two outer electrodes each only having a surface extending parallel to a placed wafer W and having different surface areas, and then replaced the outer electrode 35 of the substrate processing apparatus 10 with one of the prepared outer electrodes. Subsequently, RIE processing was performed on the placed wafer W, and the etching rate by the RIE processing at a circumferential edge portion of the placed wafer W was measured (Comparative Example 1). Then, the outer electrode was replaced by another outer electrode, and a similar measurement was made (Comparative Example 2). The results are shown by black diamond-shaped marks in the graph of FIG. 5 .
- surface area of outer electrode is taken along abscissa and etching rate is taken along ordinate.
- the surface area of outer electrode in Example 1 corresponds to the total area of the first and second secondary electron emission surfaces 35 a , 35 b of the outer electrode 35 .
- the surface area of outer electrode in each of Comparative Examples 1, 2 corresponds to the area of the surface of the outer electrode extending parallel to the placed wafer W.
- the surface areas of the outer electrodes of and the etching rates in Example 1 and Comparative Examples 1, 2 are each represented by a numerical value which assumes a value of 1 for those of Comparative Example 1. It is understood from the graph of FIG.
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Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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US12/407,109 US20090242133A1 (en) | 2008-03-27 | 2009-03-19 | Electrode structure and substrate processing apparatus |
Applications Claiming Priority (4)
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JP2008-083046 | 2008-03-27 | ||
JP2008083046A JP5348919B2 (ja) | 2008-03-27 | 2008-03-27 | 電極構造及び基板処理装置 |
US10996908P | 2008-10-31 | 2008-10-31 | |
US12/407,109 US20090242133A1 (en) | 2008-03-27 | 2009-03-19 | Electrode structure and substrate processing apparatus |
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US20090242133A1 true US20090242133A1 (en) | 2009-10-01 |
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US12/407,109 Abandoned US20090242133A1 (en) | 2008-03-27 | 2009-03-19 | Electrode structure and substrate processing apparatus |
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US (1) | US20090242133A1 (ja) |
JP (1) | JP5348919B2 (ja) |
KR (1) | KR20110131157A (ja) |
CN (1) | CN101546700B (ja) |
TW (1) | TWI475610B (ja) |
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US20090314432A1 (en) * | 2008-06-23 | 2009-12-24 | Tokyo Electron Limited | Baffle plate and substrate processing apparatus |
US20100116437A1 (en) * | 2008-11-07 | 2010-05-13 | Tokyo Electron Limited | Plasma processing apparatus and constituent part thereof |
US20110206833A1 (en) * | 2010-02-22 | 2011-08-25 | Lam Research Corporation | Extension electrode of plasma bevel etching apparatus and method of manufacture thereof |
US20150069910A1 (en) * | 2013-09-06 | 2015-03-12 | Tokyo Electron Limited | Plasma processing method and plasma processing apparatus |
US9543123B2 (en) | 2011-03-31 | 2017-01-10 | Tokyo Electronics Limited | Plasma processing apparatus and plasma generation antenna |
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US20160289827A1 (en) * | 2015-03-31 | 2016-10-06 | Lam Research Corporation | Plasma processing systems and structures having sloped confinement rings |
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JP3814176B2 (ja) * | 2001-10-02 | 2006-08-23 | キヤノンアネルバ株式会社 | プラズマ処理装置 |
JP4672456B2 (ja) * | 2004-06-21 | 2011-04-20 | 東京エレクトロン株式会社 | プラズマ処理装置 |
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2009
- 2009-03-19 US US12/407,109 patent/US20090242133A1/en not_active Abandoned
- 2009-03-20 CN CN2009101294603A patent/CN101546700B/zh active Active
- 2009-03-26 TW TW098109962A patent/TWI475610B/zh active
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- 2011-10-26 KR KR1020110109965A patent/KR20110131157A/ko not_active Application Discontinuation
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Cited By (10)
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US20090314432A1 (en) * | 2008-06-23 | 2009-12-24 | Tokyo Electron Limited | Baffle plate and substrate processing apparatus |
US8152925B2 (en) * | 2008-06-23 | 2012-04-10 | Tokyo Electron Limited | Baffle plate and substrate processing apparatus |
US20100116437A1 (en) * | 2008-11-07 | 2010-05-13 | Tokyo Electron Limited | Plasma processing apparatus and constituent part thereof |
US9337003B2 (en) | 2008-11-07 | 2016-05-10 | Tokyo Electron Limited | Plasma processing apparatus and constituent part thereof |
US20110206833A1 (en) * | 2010-02-22 | 2011-08-25 | Lam Research Corporation | Extension electrode of plasma bevel etching apparatus and method of manufacture thereof |
US9543123B2 (en) | 2011-03-31 | 2017-01-10 | Tokyo Electronics Limited | Plasma processing apparatus and plasma generation antenna |
US20150069910A1 (en) * | 2013-09-06 | 2015-03-12 | Tokyo Electron Limited | Plasma processing method and plasma processing apparatus |
US9484180B2 (en) * | 2013-09-06 | 2016-11-01 | Tokyo Electron Limited | Plasma processing method and plasma processing apparatus |
US11430636B2 (en) * | 2014-06-05 | 2022-08-30 | Tokyo Electron Limited | Plasma processing apparatus and cleaning method |
CN110462798A (zh) * | 2017-01-17 | 2019-11-15 | 朗姆研究公司 | 在感应耦合等离子体处理室内以低偏压产生近衬底补充等离子体密度 |
Also Published As
Publication number | Publication date |
---|---|
TWI475610B (zh) | 2015-03-01 |
TW201001530A (en) | 2010-01-01 |
CN101546700B (zh) | 2011-04-13 |
CN101546700A (zh) | 2009-09-30 |
KR20110131157A (ko) | 2011-12-06 |
JP2009239014A (ja) | 2009-10-15 |
JP5348919B2 (ja) | 2013-11-20 |
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