US20040129674A1 - Method and system to enhance the removal of high-k dielectric materials - Google Patents

Method and system to enhance the removal of high-k dielectric materials Download PDF

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Publication number
US20040129674A1
US20040129674A1 US10/644,957 US64495703A US2004129674A1 US 20040129674 A1 US20040129674 A1 US 20040129674A1 US 64495703 A US64495703 A US 64495703A US 2004129674 A1 US2004129674 A1 US 2004129674A1
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plasma
layer
permittivity material
substrate
modifying
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Gordon Bease
Lee Chen
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means

Definitions

  • the present invention is related to removal of materials from a substrate, particularly to removal of high-k dielectric layers from a semiconductor substrate.
  • CMOS complementary metal-oxide semiconductor
  • High-k materials Dielectric materials featuring a dielectric constant greater than that of SiO 2 (k ⁇ 3.9) are commonly referred to as high-k materials.
  • high-k materials may refer to dielectric materials that are deposited onto substrates (e.g., HfO 2 , ZrO 2 ) rather than grown on the surface of the substrate (e.g., SiO 2 , SiN x O y ).
  • High-k materials may incorporate metallic silicates or oxides (e.g., Ta 2 O 5 (k ⁇ 26), TiO 2 (k ⁇ 80), ZrO 2 (k ⁇ 25), Al 2 O 3 (k ⁇ 9), HfSiO, HfO 2 (k ⁇ 25)).
  • the high-k layers must be etched and removed in order to allow silicidation for the source/drain regions, and to reduce the risk of metallic impurities being implanted into the source/drain regions during ion implantation.
  • the present invention relates to a plasma process to modify a high-k dielectric layer through exposure of the high-k layer to the plasma, resulting in a modified layer that etches efficiently using wet etch processes.
  • the plasma process can comprise an inert gas and/or a reactive gas mixture, and the process can be implemented in-situ, as an additional step performed at the end of a gate-electrode etching process, or as an additional step added at the end of a spacer-etch process.
  • FIG. 1 shows a flowchart illustrating a method of modifying a layer of high-k material according to the present invention
  • FIGS. 2 a - 2 c show a schematic cross-sectional representation of the steps of modifying and removing a layer high-k dielectric material according to the present invention
  • FIG. 3 shows a plasma processing system according to a preferred embodiment of the present invention
  • FIG. 4 shows a plasma processing system according to an alternate embodiment of the present invention
  • FIG. 5 shows a plasma processing system according to an alternate embodiment of the present invention
  • FIG. 5A shows a plasma processing system according to an alternate embodiment of the present invention
  • FIG. 5B shows a plasma processing system according to an alternate embodiment of the present invention
  • FIG. 6 shows a plasma processing system according to an alternate embodiment of the present invention
  • FIG. 6A shows a plasma processing system according to an alternate embodiment of the present invention
  • FIG. 6B shows a plasma processing system according to an alternate embodiment of the present invention.
  • FIG. 7 shows a flowchart illustrating wet etching of a modified layer of high-k material.
  • a plasma processing system uses an inert gas to modify a high-k dielectric layer by exposure to the plasma region.
  • the inert gas species in the process gas can be selected from the group of noble gases He, Ne, Ar, Kr, and Xe, or other gases that are non-reactive towards a high-k layer in a plasma environment.
  • the gas-phase plasma ions bombard and modify the high-k layer, but the ions are physically prevented from attacking the underlying Si layer by the high-k layer.
  • the plasma modified high-k layers etch faster than high-k layers that were not subject to the plasma treatment.
  • the disclosed plasma treatment employs a reactive plasma that chemically reacts with the high-k layer, and the ions have sufficient energy to effectively disrupt and/or thin the high-k layer so that a wet etching process is able to efficiently remove the disrupted (modified) high-k layer.
  • a reactive plasma is used to modify the high-k layer
  • the process gas and plasma conditions are selected such that the patterned gate-conductor features and other materials may not be etched or damaged.
  • the process gas can comprise HBr or HCl, and an inert gas such as He.
  • the modification of the exposed high-k layer is substantially anisotropic due to ion bombardment that is parallel to the surface normal.
  • the increase in the wet etch rate of the modified high-k layer is anisotropic.
  • the result of the plasma modification of the high-k layer and the following wet etch step is anisotropic etching and removal of the exposed high-k layer.
  • the plasma treatment of the high-k layer gas according to the present invention can be carried out at different stages during the patterning process.
  • the plasma treatment can be added to the end of a normal gate etch process recipe, or added to a standard spacer-etch process.
  • a sequence for forming a gate electrode that is defined by a hard mask can comprise: 1) “break-through”, that etches through the hard mask; 2) “main-etch”, that forms the electrode features; and 3) “over-etch”, that etches and removes the (high-k) dielectric layer overlying the Si substrate.
  • Etch step 3) that removes the high-k layer frequently involves the use aggressive halogen containing precursors that have very low selectivity towards etching Si.
  • the above plasma etch step 3) can be replaced by a plasma modifying/thinning step, where the ions in the plasma bombard and modify the high-k layer without completely removing it.
  • the processing gas can comprise HBr or HCl, and an inert gas.
  • the wet etch process can comprise hot sulfuric acid, resulting in removal of the high-k layer by a standard wet clean process. Since the high-k layer is not traversed during the modifying/thinning step, the likelihood of damage occurring to the underlying Si layer is reduced. If the thinning step is carried out for too long, the high-k layer is traversed, resulting in damage to the underlying Si layer.
  • the plasma treatment may increase the amorphous content of the high-k layer and possibly breaks chemical bonds that create atomic fragments in the high-k layer.
  • the disclosed plasma treatment can utilize reactive gases, where the ion energy is adequate to disrupt the atomic structure of the high-k layer in such a way that the subsequent wet-etching process is able to remove the modified high-k layer.
  • the process conditions can be selected such that the existing gate-conductor features are not etched.
  • the plasma treatment of the high-k layer can be incorporated into manufacturing of semiconductor devices by carrying out the plasma treatment at the end of the spacer-etch process. Sidewall spacers are used to achieve isolation between the gate and source/drain regions, as well as to facilitate fabrication of self-aligned, drain-engineered dopant structures. Sometimes, it is desirable to have the high-k layer remaining on the source/drain region while performing the spacer-etch process, so that the plasma environment is exposed to the “sacrificial” high-k material instead of the Si. After the spacer is formed, plasma treatment of the high-k layer according to the current invention is performed in-situ to modify the high-k layer and facilitate fast wet etching of the high-k layer.
  • the additional plasma treatment step can be added onto the end of the gate-electrode etching process, or the additional plasma treatment step can be added onto the end of the spacer-etch process.
  • the invention can be performed in a separate process chamber or on a separate plasma etch tool.
  • the wafer can be wet-etched using standard wet etching methods to remove the high-k layer. Then an ion implant process step forms the source/drain regions without the presence of a high-k layer on the silicon surface, which alleviates the risk of a knock-on implantation of impurities from the high-k layer into the source/drain regions.
  • An additional benefit is that the high-k removal will not inhibit the silicidation of the source/drain regions, a process step that is extremely sensitive to interfacial silicon surface layers.
  • FIG. 1 shows a flowchart illustrating a method of modifying a layer of high-k material according to the present invention.
  • the method uses a plasma process to modify the high-k layer for the following wet etch process that removes the modified high-k layer from the substrate.
  • step 100 the process is started.
  • step 102 a layer is provided having a high-k material overlying a substrate, and the substrate is positioned in a plasma processing chamber.
  • a process gas comprising an inert gas and/or a reactive gas is introduced into the plasma processing chamber, and a plasma is started.
  • step 106 the layer of high-k material is exposed to the plasma, and the layer is modified due to ion bombardment in the plasma.
  • step 108 the process is ended in step 108 .
  • FIGS. 2 a - 2 c show a schematic cross-sectional representation of the steps of modifying and removing a layer high-k dielectric material.
  • FIG. 2 a shows a partially completed structure 200 comprising a high-k dielectric layer 204 overlying a semiconductor substrate 202 , etched gate electrode features 206 and hard mask or photoresist layer 208 defining the patterned structure.
  • FIG. 2 b shows the partially completed structure 200 from FIG. 2 a following a plasma etch process.
  • a modified high-k layer 210 is formed on the horizontal surface that is exposed to the plasma.
  • the structure 200 in FIG. 2 b is further processed using standard wet cleaning methods that are well known in the art to form the structure 200 in FIG. 2 c where the modified high-k layer and the hard mask (or photoresist layer) have been removed and the structure is ready for further processing to form a semiconductor device.
  • FIG. 3 shows a plasma processing system according to a preferred embodiment of the present invention.
  • a plasma processing system 1 that is capable of sustaining a plasma is depicted in FIG. 3, which includes a plasma process chamber 10 configured to facilitate the generation of plasma in processing region 45 .
  • the plasma processing system 1 further comprises a substrate holder 20 , upon which a substrate 25 to be processed is affixed, and a gas injection system 40 for introducing process gases 42 to the plasma process chamber 10 , and a vacuum pumping system 50 .
  • the gas injection system 40 allows independent control over the delivery of process gases to the process chamber from ex-situ gas sources.
  • An ionizable gas or mixture of gases is introduced via the gas injection system 40 and the process pressure is adjusted.
  • conroller 55 is used to control the vacuum pumping system 50 and gas injection system 40 .
  • plasma is utilized to create materials specific to a predetermined materials process, and to aid either the deposition of material to a substrate 25 or the removal of material from the exposed surfaces of the substrate 25 .
  • Substrate 25 is transferred into and out of chamber 10 through a slot valve (not shown) and chamber feed-through (not shown) via robotic substrate transfer system where it is received by substrate lift pins (not shown) housed within substrate holder 20 and mechanically translated by devices housed therein. Once the substrate 25 is received from the substrate transfer system, it is lowered to an upper surface of the substrate holder 20 .
  • the substrate 25 is affixed to the substrate holder 20 via an electrostatic clamp (not shown). Furthermore, the substrate holder 20 further includes a cooling system including a re-circulating coolant flow that receives heat from the substrate holder 20 and transfers heat to a heat exchanger system (not shown), or when heating, transfers heat from the heat exchanger system. Moreover, gas may be delivered to the backside of the substrate to improve the gas-gap thermal conductance between the substrate 25 and the substrate holder 20 . Such a system is utilized when temperature control of the substrate is required at elevated or reduced temperatures.
  • temperature control of the substrate may be useful at temperatures in excess of the steady-state temperature achieved due to a balance of the heat flux delivered to the substrate 25 from the plasma and the heat flux removed from substrate 25 by conduction to the substrate holder 20 .
  • heating elements such as resistive heating elements, or thermo-electric heaters/coolers are included.
  • the substrate holder 20 can further serve as an electrode through which radio frequency (RF) power is coupled to plasma in the processing region 45 .
  • the substrate holder 20 can be electrically biased at a RF voltage via the transmission of RF power from an RF generator 30 through an impedance match network 32 to the substrate holder 20 .
  • the RF bias serves to heat electrons and, thereby, form and maintain plasma.
  • the system operates as a RIE reactor, wherein the chamber and upper gas injection electrode serve as ground surfaces.
  • a typical frequency for the RF bias ranges from 1 MHz to 100 MHz and is preferably 13.56 MHz.
  • RF power can be applied to the substrate holder electrode at multiple frequencies.
  • the impedance match network 32 serves to maximize the transfer of RF power to plasma in processing chamber 10 by minimizing the reflected power.
  • Match network topologies e.g., L-type, ⁇ -type, T-type
  • automatic control methods are known in the art.
  • Gas injection system 40 can include a showerhead, wherein the process gas 42 is supplied from a gas delivery system (not shown) to the processing region 45 through a gas injection plenum (not shown), a series of baffle plates (not shown) and a multi-orifice showerhead gas injection plate (not shown).
  • Vacuum pump system 50 can include a turbo-molecular vacuum pump (TMP) capable of a pumping speed up to 5000 liters per second (and greater), and a gate valve for throttling the chamber pressure.
  • TMP turbo-molecular vacuum pump
  • a 1000 to 3000 liter per second TMP is employed.
  • TMPs are useful for low pressure processing, typically less than 50 mTorr.
  • a mechanical booster pump and dry roughing pump are used.
  • a controller 55 includes a microprocessor, a memory, and a digital I/O port capable of generating control voltages sufficient to communicate and activate inputs to the plasma processing system 1 as well as monitor outputs from the plasma processing system 1 . Moreover, the controller 55 is coupled to and exchanges information with the RF generator 30 , the impedance match network 32 , the gas injection system 40 , plasma monitor system 57 , and the vacuum pump system 50 . A program stored in the memory is utilized to control the aforementioned components of a plasma processing system 1 according to a stored process recipe.
  • controller 55 is a digital signal processor (DSP); model number TMS320, available from Texas Instruments, Dallas, Tex.
  • the plasma monitor system 57 can comprise, for example, an optical emission spectroscopy (OES) system to measure excited particles in the plasma environment and/or a plasma diagnostic system, such as a Langmuir probe, for measuring plasma density.
  • OES optical emission spectroscopy
  • the plasma monitor system 57 can be used with controller 55 to determine the status of the etching process and provide feedback to ensure process compliance.
  • plasma monitor system 57 can comprise a microwave and/or a RF diagnostic system.
  • FIG. 4 shows a plasma processing system according to an alternate embodiment of the present invention.
  • the plasma processing system 1 of FIG. 4 further includes either a mechanically or electrically rotating DC magnetic field system 60 , in order to potentially increase plasma density and/or improve plasma processing uniformity, in addition to those components described with reference to FIG. 3.
  • the controller 55 is coupled to the rotating magnetic field system 60 in order to regulate the speed of rotation and field strength.
  • FIG. 5 shows a plasma processing system according to an alternate embodiment of the present invention.
  • the plasma processing system 1 of FIG. 5 further includes an upper plate electrode 70 to which RF power is coupled from an RF generator 72 through an impedance match network 74 .
  • a typical frequency for the application of RF power to the upper electrode ranges from 10 MHz to 200 MHz and is preferably 60 MHz.
  • a typical frequency for the application of power to the lower electrode ranges from 0.1 MHz to 30 MHz and is preferably 2 MHz.
  • the controller 55 is coupled to the RF generator 72 and the impedance match network 74 in order to control the application of RF power to the upper electrode 70 .
  • FIG. 5A shows a plasma processing system according to an alternate embodiment of the present invention.
  • the plasma processing system 1 in FIG. 5 is modified to contain a grounded lower electrode 20 .
  • a DC bias can be applied to the lower electrode 20 .
  • FIG. 5B shows a plasma processing system according to an alternate embodiment of the present invention.
  • the plasma processing system 1 in FIG. 5 is modified to contain a lower electrode 20 that is electrically isolated from the plasma processing system 1 .
  • a floating potential can be formed on the lower electrode 20 and on the substrate 25 when the plasma is on.
  • FIG. 6 shows a plasma processing system according to an alternate embodiment of the present invention.
  • the plasma processing system of FIG. 3 is modified to further include an inductive coil 80 to which RF power is coupled via an RF generator 82 through an impedance match network 84 .
  • RF power is inductively coupled from the inductive coil 80 through a dielectric window (not shown) to the plasma-processing region 45 .
  • a typical frequency for the application of RF power to the inductive coil 80 ranges from 10 MHz to 100 MHz and is preferably 13.56 MHz.
  • a typical frequency for the application of power to the chuck electrode ranges from 0.1 MHz to 30 MHz and is preferably 13.56 MHz.
  • a slotted Faraday shield (not shown) can be employed to reduce capacitive coupling between the inductive coil 80 and plasma.
  • the controller 55 is coupled to the RF generator 82 and the impedance match network 84 in order to control the application of power to the inductive coil 80 .
  • the plasma is formed using electron cyclotron resonance (ECR).
  • ECR electron cyclotron resonance
  • the plasma is formed from the launching of a Helicon wave.
  • the plasma is formed from a propagating surface wave.
  • FIG. 6A shows a plasma processing system according to an alternate embodiment of the present invention.
  • the plasma processing system of FIG. 6 is modified to contain a grounded chuck electrode 20 .
  • a DC bias can be applied to the chuck electrode 20 .
  • FIG. 6B shows a plasma processing system according to an alternate embodiment of the present invention.
  • the plasma processing system 1 of FIG. 6 is modified to contain a chuck electrode 20 that is electrically isolated from the plasma processing system 1 .
  • a floating potential can be formed on the chuck electrode 20 and on the substrate 25 when the plasma is on.
  • FIG. 7 shows a flowchart illustrating wet etching of a modified layer of high-k material.
  • step 700 the process is started.
  • step 702 a modified layer of high-k material overlying a substrate is provided to a wet etch system.
  • step 704 the modified layer of high-k material is exposed to a wet etch fluid.
  • the etch fluid may be an acid such as sulfuric acid.
  • step 706 the modified layer of high-k material is etched.
  • the substrate is rinsed with deionized water and dried in step 708 , and the process is ended in step 710 .
  • the wet etching can be performed in a conventional cleaning or wet etching chamber, either operatively coupled to or within processing chamber 10 .
  • a test structure was used that comprised patterned Si gate electrodes and a HfO 2 dielectric layer (50 ⁇ thick) overlying a Si substrate.
  • the wet etch rate of the HfO 2 layer in hot sulfuric acid was about 2-3 A/hr. Removal of a HfO 2 layer that requires long wet etch runs, can introduce problems such as erosion of the interface between the HfO 2 layer and the gate electrode.
  • a plasma modifying step was performed on the above test structure in a capacitively coupled plasma process chamber, using a process gas comprising HBr and He gases.
  • the substrate temperature was maintained at 80° C. and the chamber pressure was 12 mTorr.
  • the test structure was exposed to the plasma for about 12 sec, which resulted in a modified HfO 2 layer with a thickness of about 5 A.
  • the modified HfO 2 layer wet etched in hot sulfuric acid at a rate of about 2-3 A/min, thereby showing greatly enhanced rate of removal when compared to a HfO 2 layer that was not subjected to the plasma modifying step.
  • the wet etch step showed good selectivity of the HfO 2 dielectric layer to the source/drain regions.
  • d1 is the initial HfO 2 layer thickness
  • d2 is the thickness of the plasma treated HfO 2 layer
  • d3 is the thickness of the remaining HfO 2 layer following the wet etch of the plasma treated HfO 2 layer.
  • T ESC is the temperature of the electrostatic chuck upon which the wafer is positioned
  • Upper/lower power is the RF power applied to the upper and lower electrodes, respectively
  • P is the chamber pressure
  • Ar flow is the flow of Ar gas in the process chamber during the plasma treatment.
  • the Ar gas flow further comprised 10 sccm of CF 4 in Runs 1 and 2, to keep the high-k surface clean from quartz contamination during the plasma treatment.
  • the spacing between the upper and lower electrodes is denoted by G, and Time is the length of the plasma treatment.
  • the frequency for the RF bias on the upper electrode was 60 MHz, and 13.56 MHz on the lower electrode.
  • the wet etch step was carried out in dilute HF.
  • Runs 5 and 6 the plasma treatment process was also run in RIE mode, but using a higher Ar gas flow than in Runs 3 and 4.
  • the higher Ar gas flows lead to sputtering of the HfO 2 layer with a sputtering rate greater than about 200 A during the plasma treatment.
  • the remainder of the plasma treated HfO 2 layer was effectively removed during the wet etch step.
  • the HfO 2 layer residual left on the wafer after the plasma treatment in Run 5 is thought to be Hf-rich, and therefore the true residual layer thickness d3 is expected to be less than the measured 7.5 A.

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US20050014380A1 (en) * 2003-07-18 2005-01-20 Yoshitaka Kai Plasma processing method and apparatus
US20050064716A1 (en) * 2003-04-14 2005-03-24 Hong Lin Plasma removal of high k metal oxide
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US20110175176A1 (en) * 2010-01-20 2011-07-21 International Business Machines Corporation High-k transistors with low threshold voltage
US10460953B2 (en) * 2017-04-25 2019-10-29 Hitachi High-Technologies Corporation Semiconductor manufacturing apparatus for manufacturing a semiconductor device having a high-K insulating film, and a method for manufacturing the semiconductor device
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US7037845B2 (en) * 2003-08-28 2006-05-02 Intel Corporation Selective etch process for making a semiconductor device having a high-k gate dielectric
US7115530B2 (en) * 2003-12-03 2006-10-03 Texas Instruments Incorporated Top surface roughness reduction of high-k dielectric materials using plasma based processes

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