TWM253056U - Compact chip packaging structure - Google Patents

Compact chip packaging structure Download PDF

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Publication number
TWM253056U
TWM253056U TW093202112U TW93202112U TWM253056U TW M253056 U TWM253056 U TW M253056U TW 093202112 U TW093202112 U TW 093202112U TW 93202112 U TW93202112 U TW 93202112U TW M253056 U TWM253056 U TW M253056U
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Taiwan
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scope
item
chip
miniaturized
patent application
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TW093202112U
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English (en)
Inventor
Shr-Shiung Lian
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Optimum Care Int Tech Inc
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Priority to TW093202112U priority Critical patent/TWM253056U/zh
Priority to JP2004005087U priority patent/JP3107385U/ja
Priority to US10/959,192 priority patent/US20050179119A1/en
Publication of TWM253056U publication Critical patent/TWM253056U/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
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    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

M253056 五、創作說明（1) 【創作之技術領域】 本創作係有關—種精小化晶元封裝結構， 減封裝後晶體其結構體積、增進晶片散熱及 括 能兼顧封裝成本降低之晶元封裝結構設^者。别、、 【先前技術】 户功Ϊ現ί:電晶體在被要求處理或連續儲存龐大資料且 $，極I於峰*例如電腦在使用同時經常同纟開啟多種程 " 易毛生電晶體過熱現像，因而造成系統不穩定等瑕 疲’又現今開發出來細RII等晶片，亦存 度過高之疑慮，因此者詈雷日锕#為A :于隹頁運作時，皿 曰辦Η恭拉v + 日散熱速率，一直是高階電 二開：時=善之重點。其次，現今電子及資訊相關 身：用】、朝向精小化及多功能化設計，以符合隨 办門，相斟的夕樣需求，是以不僅限縮電路板可使用之 工間=的必需令電晶體等電子元件體積更小。 +五t i晶體封裝組成結構，請參考第十四圖及第 線架10提=一，以一具有複數條片狀接腳101之外電性導 ' 、日日片2 〇承載，並於晶片2 0盆接點盥導蝮牟1 η 各接腳101 (引指）間焊*右* Λ 其接點與導線架10 讦诱過莫始加η 知5又有金屬導線30，藉此使晶片2〇 了透k導線木丨〇與外界接通 20及導線架1 0外邻祐淼以谕棚4電路板# )又該日日片 ，進而構# _ σ卩並採以塑膠或陶瓷等絕緣材料施以封裝 進f構成一密封狀態之封膠體40。由此可見，習知雷曰 體封裝組成結構，不僅因 各 電曰日 •且如按^ #不僅因封骖體40全面封裝而致體積增大 ’ -廉的封膠材料時，將影響晶片20散熱速率， 第5頁 M253056 —I I-, 五、創作說明（2) i之ϊ:ΐ料，又因全面封裝而致成本無法降 者，構存在著魚與熊掌不能得兼之矛盾；另 2〇之外i 1 0係以長條片f摺狀接腳1〇1作為晶片 A盎電如第十五圖所示，是以接腳101其接收點 =接點Β相對距離過長，因而直接影響傳輸 難u符合高階晶體之使用要求。 千 【創作内容】 Μ斗本創作主要目的，在於提供一種精小化晶元封裝結構 权汁’惟藉以導線架之塊狀引指結構改良，並配合晶片打 線部位的封膠體精巧化結構之實施設計，俾達成降低封裝 成本、增進晶片散熱速率，並縮減電晶體其結構體積之多 重功效增進者。 ^ 依上述目的，本創作係實施以包括有複數矩形塊狀引 指之導線架供至少一晶片貼合承置於上置面，於該導線架 之各引指下端面與晶片間分別接設有可導通之金屬導線， 藉此並特別選定設置金屬導線部位以絕緣材料封裝，進而 形成有結構體積精巧之封膠體，令該封膠體位於打線部位 構成密封，並預留引指下端面具有至少一外電性之導接面 ’俾達成精減晶片封裝完成後結構體積、增進散熱速率之 效益效果’並因矩形塊狀引指結構而縮短傳輸距離，增進 晶片對外傳輸之效率。 【實施方式】
第6頁 M253056 五、創作說明（3) 兹依附圖實施例將本創作結構 的詳細說明如下： 政及其他之作用、目 如附圖所示，本創作所為『精小曰一 計，係為-種可同步達成縮減電^體裝結構』設 散熱及傳輸速率，並且降低封裳 ^#體積增進晶片 之導線架引指及封裝結構創新改；序成本諸多效益 架1、晶片2、金屬導線3及經特殊ς ς 2有-導線 所組成，其中： —w α十之封膠體4 導線架1 ，係為一種具有複數排列金屬質 成之晶片外電性元件，其排列狀引指丨丨可依曰所構 J擇設為二排或四排或其他排列數目及位置:曰惟：， 係特別構形為矩形塊狀，以具有一引心 及可打線並作為外電部位之一下端面^之片上2置= =t用石夕、珅化卸或其他半導體材料所切割製成之半導 體曰曰片，並依需求而可作為各種功能性之晶體者； =屬導線3 ，係為一種用以連接晶片2與導線架丄各 曰 使曰曰片2獲致外電效果之金屬線，並可選擇常見 的金線構成； 藉此’請參考第一圖所示，以該導線架1之複數矩形 塊狀引指11其上置面j j丨共同承載至少一晶片2 ，使晶片 2以黏著物（如雙面膠等）貼固於導線架1其塊狀引指11 ’並於各弓丨指11其下端面11 2與晶片2之間接接設有至少 —金>1導線3 (打線作業），令該導線架1引指11成為晶 片2之外電性元件；藉此並選定晶片2連接有金屬導線3
五、創作說明（4) 紫係以絕緣材料（例如熱固性塑膠或陶瓷等） #、表2 /業，形成有一結構形狀精巧龙將金屬導線3及 :开=封之封膠體4 (其封膠體4並不揭限為矩形 -以=狀等）’且預留引指下端面112具有至少 為可縮減體積之晶元封裝結^導接面C，即組成本創作所 體4 2:ί f:ί揭導線架1引指11結構形態以及該封膠 篮4 <封裝結構創新設 狀而具有金屬導線3連接邱由於各引指11係構形為矩形塊 下端面11 Ρ π _ 連接崢及外電部位（導接面C )之一 二用Λ導接面c任何-點與外界其他設備 離缩小，^ π* =、屬導線3連接部D與導接面C其相對距 離細小，即可降低金屬質 六々日对此 輸速率；其次，因本_ ，阻值’進而增進訊號傳 線3連接部實施—封膠體=覆晶片2處及針對金屬導 定作用，可形成曰片 4封裝，即已達成具有保護及穩 故藉封膠體4所ΐ位^用導線架1對外連通之電晶體’ 積（封裝厚度及寬度等結構’係獲致電晶體體 用成本，並符合現今電子產”降低封膠材料使 創作並未針對晶片2上 ^ ^ 之需求，同時，因本 面間形成封製（填二於直 阻礙散熱等情事，自可態故無習見封膠材料 增進，尤其在貼覆有^ 導線架1獲得散熱速率 將晶片2所發生之埶二二散：·：片等散熱裝置時’即能 熱度迅速經由其他散熱設備或裝置排出 M253056 五、創作說明
態設計， 本降低等 :由此可見，本創作引指丨丨及封膠體4之結構形 係達成同步兼顧體積縮小、散熱、傳輸效^ 功效增進。 〃成 如上所述，本創作主要特徵係在導線架i與曰 有金屬導線3部位實施有一封膠體4構成局部：g結構, 基於此項結構特徵，本創作係可進一步實施令晶體^臻實 用之封裝結構，如第三圖所示，可令所述局部封裝之封^ 體4略凸出導線架1下方，並於封膠體4側部引丨下端 面11 2另設有一凸塊狀封膠體5，以於兩封膠體4、5間 形成一縫隙狀之夾持部51及引指11導接面c，藉此提供\乍 為錫球等電性連接物之巍入部位，俾於導線架1組裝在其 他外部設備後可構成電性連結。如第四圖所示，亦可於G 膠體4側部引指11下端面112另設有二凸塊狀間隔對應的 封膠體5 ’於二封膠體5間形成一縫隙狀之夾持部51， 及引指11導接面C，藉此作為錫球等電性連接物之嵌入部 位。次如第五圖所示，本創作亦可於晶片2與各引指11間 使用具有導電性質之連接物6結構（例如金屬溶液固化而 成或導電塑膠等），以代替所述之金屬導線3連接結構， 並可使連接物6連結於晶片2及引指11側面之間，令連接 物6隱藏於導線架1中間，以選定導線架1中間實施有局 部性封膠體4密封，且令該封膠體4可為與引指11底面齊 平，俾使封裝結構更臻精簡。或如第六圖所示，本創作亦 可擇用一種下端面112—體凸設有至少一隆凸部ι13，以隆 凸部11 3相鄰處之下端面11 2作為金屬導線3連接部，而隆
M253056 五、創作說明（6) 凸部113下端作為導接面C之引指u社槿 晶片2間連接金屬導、線3，並選定凹。霉’於下端面112與 施有局部性封膠體4密封，且入 =下端面112處實 凸部11 3之導接面C齊平，嫌^以、夕體4與引指11其隆 作用及封裝結構更臻精簡、增&進傳yn述之密封保護 基於本創作上述各種實例所示結構=逮率等效果。 2周圍另實施有—封膠體7形成包㈣選定晶片 所示），藉此另獲致更_^# = (t第七圖 果，俾令封裝完成之晶體更臻實用。持政熱性良好等效 另者，本創作前述對 體4結構實施例，其實施狀成局部封裝之封膠 圖所不，選疋具有二排^指 圃及弟九 屬導線3部位，分別，* γ::f糸1與晶片2間之金 始q描屮丛门心Γ 有一可將該排引指11局部及金屬導 線3構成共同封裝之封膠體 金屬導 封膠體4。次如第十圖所示，亦 11與晶片2間之金屬導魂qχ等碌木1其各引扣 引指11豆金屬導绩H 分別實施有一封裝各排 =個點封膠體4，以於晶片2 -面形 成數個”’占狀局口p封褒之結構形態。又如 創作亦可分別選定導線年 不，本 屬導線3部位12對稱狀二引指11内端與金 ST片2=Ϊ同於前述之效果。由是可見，本創作設 Γ i s 一 Γ部封裝之封膠體4，其所設數目及位置 ，ϋ ΐ際二造需求而簡易變化實施’並無限制；同理 ，’考第十一圖所示，本創作亦可於具有四排或其他排列 M253056
五、創作說明（7) 數引指11之導線架1與晶片2間，分別實施前述各種可任 意依需求而變化之封膠體4封裝結構，故凡運用本創作特 欲所為之簡易變更或置換或增加實施例者，均應包含於本 創作專利範圍中，順予指明。 至於，本創作所述封膠 之實施例，其應用組裝於電 三圖所示），係令導線架1 開槽81之電性板8等其他設 及保護打線部位之作用。 綜上所述，本創作所為 確具實用性與創作性，其手 功效與設計目的誠然符合， 法提出新型專利申請，惟懇 利為禱，至感德便。 體4可略凸出於導線架1下方 性板8等其他設備時（如第十 下方之封膠體4可容置於設有 備，進而獲致組裝完成後輕薄 『精小化晶元封裝結構』，已 段之運用亦出於新穎無疑，且 :稱合理進步至明。為此，板 。月鈞局惠予詳審，並賜准專
m
第11頁 M253056 圖式簡單說明 f 一圖為本創作封膠體局部封裝之斷面示意圖。 第=圖為本創作封膠體局部封裝之底視示意圖。 圖 第三圖為本創作封膠體實施有錫球等電性連接物之示意 〇 圖 第四圖為本創作具有錫球等電性連接物之另一實施示意 〇 第五圖為本創作以固化金屬溶液之連接物取代金屬導線並 局部封裝之示意圖。 第六圖為本創作引指下端面具有隆凸部之實施例及局部封 裝示意圖。 =七圖為本創作晶片周圍另實施封膠體之示意圖。 第八圖為本創作各排引指分別局部封裝實施例之斷面示意 圖。 第九圖為本創作各排引指分別局部封裝實施例之底視示意 圖〇 第十圖為本創作各引指分別呈點狀局部封裝之底視示意圖 施例之底視示 第十一圖為本創作各排引指分別局部封裝實 意圖。 =:ΐ圖為本創作四排引指之封裝結構示意圖。 I二圖為本創作導線架與電性板組裝之示意圖 四圖為習見晶片與導線架封裝結構之底視圖 五圖為習見晶片與導線架封裝結構之斷面圖
第12頁 M253056
第13頁

Claims (1)

  1. M253056 六、申請專利範圍 、一種精小化晶元封裝結構，包括·· 指；-晶片;及‘：J::ί ΐ排列形態之塊狀引 金屬導線所組成，其特=於ο別與晶片間連接一 *連接部位構成局部封:並==::1有導； 二:;外界連接之導接面，藉此組成精 2 、：：請專：範圍第！項所述之精小化晶 其I，該導線架其塊狀引指包括形成為矩 γ 、：：請專利範圍第工項所述之精小化晶元封裝： 其中，該封膠體所預留之引指導接面； ，指下端面具有一隆凸部，並以該隆凸部之 4 5 m利範圍第工項所述之精小化晶元封裝結構， 中，该引指下端其他部位可另實施有其他封膠 而形成一縫隙狀之錫球及電性連接物之嵌入部位。運 、如申請專利範圍第1項所述之精小化晶元封裝社 其中，該封膠體之厚度可為與引指之導接面齊^。 ’ 、如申請專利範圍第1項所述之精小化晶元封裳結構， 其中’該金屬導線可使用具有導電性質之連接物梦 連結於晶片與引指間所取代。 w m 7 、如申請專利範圍第1項所述之精小化晶元封裝結構， 第14頁 M253056 六、申請專利範圍 其中，該晶片周圍可另實施有封膠體結構。 8、如申請專利範圍第1項所述之精小化晶元封裝結構， 其中，各該引指之間可不填充封膠或填充封膠。 imii
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