TWI779729B - 具有瓶形矽穿孔的半導體元件結構及其製備方法 - Google Patents
具有瓶形矽穿孔的半導體元件結構及其製備方法 Download PDFInfo
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- TWI779729B TWI779729B TW110126646A TW110126646A TWI779729B TW I779729 B TWI779729 B TW I779729B TW 110126646 A TW110126646 A TW 110126646A TW 110126646 A TW110126646 A TW 110126646A TW I779729 B TWI779729 B TW I779729B
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Abstract
本揭露提供一種半導體元件結構及其製備方法。該半導體元件結構包括:一矽層,設置在一第一半導體晶粒上;以及一第一遮罩層,設置在該矽層上。該半導體元件結構亦包括一第二半導體晶粒,設置在該第一遮罩層上;以及一矽穿孔,穿經該矽層與該第一遮罩層。該矽穿孔的一下表面大於該矽穿孔的一上表面,以及該矽穿孔的該上表面大於該矽穿孔的一剖面,該剖面係位在該矽穿孔的該下表面與該上表面之間,且該剖面平行於該矽穿孔的該下表面與該上表面。
Description
本申請案主張2020年11月10日申請之美國正式申請案第17/093,974號的優先權及益處,該美國正式申請案之內容以全文引用之方式併入本文中。
本揭露係關於一種半導體元件結構及其製備方法。特別是有關於一種具有一瓶形矽穿孔的半導體元件結構及其製備方法。
對於許多現代應用,半導體元件是不可或缺的。隨著電子科技的進步,半導體元件的尺寸變得越來越小,於此同時提供較佳的功能以及包含較大的積體電路數量。由於半導體元件的規格小型化,實現不同功能的半導體元件之不同型態與尺寸規模,係整合(integrated)並封裝(packaged)在一單一模組中。再者,許多製造步驟執行於各式不同型態之半導體裝置的整合(integration)。
然而,該等半導體元件的製造與整合包含許多複雜步驟與操作。在該等半導體元件中的整合係變得越加複雜。該等半導體元件之製造與整合的複雜度中的增加可造成多個缺陷。據此,有持續改善該等半導
體元件之製造流程的需要,以便對付該等缺陷並可加強其效能。
上文之「先前技術」說明僅係提供背景技術,並未承認上文之「先前技術」說明揭示本揭露之標的,不構成本揭露之先前技術,且上文之「先前技術」之任何說明均不應作為本案之任一部分。
本揭露之一實施例提供一種半導體元件結構。該半導體元件結構包括:一矽層,設置在一第一半導體晶粒上;以及一第一遮罩層,設置在該矽層上。該半導體元件結構亦包括一第二半導體晶粒,設置在該第一遮罩層上;以及一矽穿孔,穿經該矽層與該第一遮罩層。該矽穿孔的一下表面大於該矽穿孔的一上表面,以及該矽穿孔的該上表面大於該矽穿孔的一剖面,該剖面係位在該矽穿孔的該下表面與該上表面之間,且該剖面平行於該矽穿孔的該下表面與該上表面。
在一些實施例中,該矽穿孔直接接觸在該第一半導體晶粒中的一第一導電墊以及在該第二半導體晶粒中的一第二導電墊。在一些實施例中,該半導體元件結構還包括一第三導電墊,設置在該第一半導體晶粒中,並鄰近該第一導電墊設置;以及一第四導電墊,設置在該第二半導體晶粒中,並鄰近該第二導電墊設置,其中,在該第一半導體晶粒中的該第三導電墊與該第一導電之間的一橫向距離,係大於在該第二半導體晶粒中的該第四導電墊與該第二導電墊之間的一橫向距離。在一些實施例中,該半導體元件結構還包括一第二遮罩層,設置在該第一遮罩層與該第二半導體晶粒之間,其中,該矽穿孔係穿經該第二遮罩層,以及其中,該第一遮罩層與該第二遮罩層係包含不同材料。
在一些實施例中,該第二遮罩層的一側壁係相對於該第一
遮罩層的一側壁傾斜。在一些實施例中,該半導體元件結構還包括一保護層,係覆蓋該第二遮罩層的該側壁、該第一遮罩層的該側壁以及該矽層的一上側壁,其中,該矽層的該上側壁係大致對準該第一遮罩層的該側壁。在一些實施例中,該矽穿孔包括一導電層;一阻障層,係覆蓋該導電層的各側壁與一下表面,其中,該阻障層直接接觸該第一半導體晶粒;以及一襯墊層,係覆蓋該阻障層的各側壁。
本揭露之另一實施例提供一種半導體元件結構。該半導體元件結構:包括一矽層,設置在一第一半導體晶粒上;以及一第一遮罩層,設置在該矽層上。該半導體元件結構亦包括一第二遮罩層,設置在該第一遮罩層上;以及一第二半導體晶粒,設置在該第二遮罩層上。該半導體元件結構還包括一矽穿孔,係穿經該矽層、該第一遮罩層以及該第二遮罩層,以電性連接該第一半導體晶粒與該第二半導體晶粒。該矽穿孔具有一瓶形部,該瓶形部係被該第一遮罩層與該矽層的一上部所圍繞,以及該矽穿孔與該第一半導體晶粒之間的一界面面積,係大於該矽穿孔與該第二半導體晶粒之間的一界面面積。
在一些實施例中,該第一半導體晶粒具有一第一臨界尺寸(critical dimension),以及該第二半導體晶粒具有一第二臨界尺寸,而該第一臨界尺寸係大於該第二臨界尺寸。在一些實施例中,該矽穿孔還包括一上部,係被該第二遮罩層所圍繞;以及一下部,係被該矽層的一下部所圍繞;其中,該矽穿孔的該瓶形部係夾置在該矽穿孔的該上部與該下部之間,以及該矽穿孔的該上部具有一錐形輪廓,該錐形輪廓係朝該矽穿孔的該瓶形部逐漸變細。
在一些實施例中,該矽穿孔的該下部具有多各圓形及凸面
上角落。在一些實施例中,該矽穿孔的該瓶形部與該上部係藉由一保護層而與該第一遮罩層、該第二遮罩層以及該矽層的該上部分隔開。在一些實施例中,該矽穿孔的該下部直接接觸該矽層的該下部。在一些實施例中,該保護層包含氧化鋁。
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法包括:形成一矽層在一第一半導體晶粒上;以及形成一第一遮罩層在該矽層上。該製備方法亦包括形成一第一開孔以穿經該第一遮罩層,以及形成一第二開孔以穿經該矽層;以及沉積一保護層在該第一遮罩層上。延伸該保護層以覆蓋該第一遮罩層的一側壁以及該矽層的一上側壁。該製備方法還包括藉由使用該保護層當作一遮罩以蝕刻該矽層,進而底切該矽層的一上部,以便形成一放大的第二開孔。此外,該製備方法包括以一矽穿孔充填該第一開孔與該放大的第二開孔;以及形成一第二半導體晶粒在該矽穿孔上。
在一些實施例中,該製備方法還包括形成一第二遮罩層在該第一遮罩層上;以及在穿經該第一遮罩的該第一開孔形成之前,係形成一第三開孔以穿經該第二遮罩層。在一些實施例中,在形成穿經該矽層的該第二開孔期間,蝕刻該第二遮罩層以形成一放大的第三開孔,以及該放大的第三開孔具有一錐形輪廓,該錐形輪廓係朝向該第一開孔逐漸變細。
在一些實施例中,該保護層的製作技術包含一非共形(non-conformal)沉積製程。在一些實施例中,該製備方法還包括在該矽穿孔形成之前,係移除該保護層。在一些實施例中,該矽層的該上部係覆蓋該矽穿孔的一下部。
本揭露的一些實施例提供一半導體元件結構及其製備方
法。在一些實施例中,該半導體元件結構具有一矽穿孔。該矽穿孔的下表面大於該矽穿孔的上表面,以及該矽穿孔的上表面大於該矽穿孔的一剖面,該剖面係位在該矽穿孔的上表面與下表面之間,且該剖面平行於該矽穿孔的上表面與下表面。因此,該矽穿孔可用於電性連接在垂直方向及具有不同設計規則的二半導體晶粒(或半導體晶圓)。結果,可增加功能密度(functional density)(意即,單位晶片面積之內連接裝置的數量),並提供多個好處,例如提高生產效率、降低成本以及改善效能。
上文已相當廣泛地概述本揭露之技術特徵及優點,俾使下文之本揭露詳細描述得以獲得較佳瞭解。構成本揭露之申請專利範圍標的之其它技術特徵及優點將描述於下文。本揭露所屬技術領域中具有通常知識者應瞭解,可相當容易地利用下文揭示之概念與特定實施例可作為修改或設計其它結構或製程而實現與本揭露相同之目的。本揭露所屬技術領域中具有通常知識者亦應瞭解,這類等效建構無法脫離後附之申請專利範圍所界定之本揭露的精神和範圍。
10:製備方法
100:半導體元件結構
101:半導體基底
103:介電層
105a:導電墊
105b:導電墊
105c:導電墊
110:第一半導體晶粒
111:矽層
111L:下部
111U:上部
113:第一遮罩層
115:第二遮罩層
117:圖案化遮罩
120:開孔
130:開孔
130’:開孔
140:開孔
150:開孔
161:保護層
161’:保護層
163:襯墊材料
163’:襯墊層
165:阻障材料
165’:阻障層
167:導電材料
167’:導電層
169:矽穿孔
169a:上部
169b:瓶頸形狀部
169B:下表面
169c:下部
169T:上表面
171:半導體基底
173:介電層
175a:導電墊
175b:導電墊
175c:導電墊
175d:導電墊
175e:導電墊
180:第二半導體晶粒
200:半導體元件結構
263:襯墊材料
263’:襯墊層
265:阻障材料
265’:阻障層
267:導電材料
267’:導電層
269:矽穿孔
269a:上部
269b:瓶頸形狀部
269B:下表面
269c:下部
269T:上表面
C:上角落
CS:剖面
D1:橫向距離
D2:橫向距離
S11:步驟
S13:步驟
S15:步驟
S17:步驟
S19:步驟
S21:步驟
S23:步驟
S25:步驟
S27:步驟
S29:步驟
SW1:側壁
SW2:側壁
USW:上側壁
W1:寬度
W2:寬度
W3:下寬度
W4:上寬度
W5:下寬度
W6:上寬度
θ:角度
參閱實施方式與申請專利範圍合併考量圖式時,可得以更全面了解本申請案之揭示內容,圖式中相同的元件符號係指相同的元件。
圖1例示本揭露一些實施例之一半導體元件結構的剖視示意圖。
圖2例示本揭露一些實施例之圖1的放大示意圖。
圖3例示本揭露一些實施例之一改良半導體元件結構的剖視示意圖。
圖4例示本揭露一些實施例之一圖3的放大示意圖。
圖5例示本揭露一些實施例之一半導體元件結構之製備方法的流程示意圖。
圖6例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,形成一矽層在一第一半導體晶粒上。
圖7例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,依序形成一第一遮罩層以及一第二遮罩層在該矽層上。
圖8例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,形成一開孔在該第二遮罩層中。
圖9例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,形成一開孔在該第一遮罩層中。
圖10例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,形成一開孔在該矽層中。
圖11例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,沉積一保護層。
圖12例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,藉由使用該保護層當作一遮罩以蝕刻該矽層。
圖13例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,移除該保護層。
圖14例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,形成一襯墊材料在該第一遮罩層、該第二遮罩層與該矽層的各開孔中。
圖15例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該
中間階段係在該半導體元件結構形成期間,蝕刻該襯墊材料以形成一襯墊層。
圖16例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,形成一阻障材料在該襯墊層上。
圖17例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在該半導體元件結構形成期間,形成一導電材料在該阻障材料上。
圖18例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在一半導體元件結構形成期間,平坦化該導電材料與該阻障材料以形成一矽穿孔(through silicon via)。
圖19例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在一改良半導體元件結構形成期間,形成一襯墊材料在該保護層上。
圖20例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在一改良半導體元件結構形成期間,蝕刻該襯墊材料以形成一襯墊層。
圖21例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在一改良半導體元件結構形成期間,形成一阻障材料在該襯墊層上。
圖22例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在一改良半導體元件結構形成期間,形成一導電材料在該阻障材料上。
圖23例示本揭露一些實施例之一中間階段的剖視示意圖,其中,該中間階段係在一改良半導體元件結構形成期間,平坦化該導電材料與該阻障材料以形成一矽穿孔。
以下描述了組件和配置的具體範例,以簡化本揭露之實施例。當然,這些實施例僅用以例示,並非意圖限制本揭露之範圍。舉例而言,在敘述中第一部件形成於第二部件之上,可能包含形成第一和第二部件直接接觸的實施例,也可能包含額外的部件形成於第一和第二部件之間,使得第一和第二部件不會直接接觸的實施例。另外,本揭露之實施例可能在許多範例中重複參照標號及/或字母。這些重複的目的是為了簡化和清楚,除非內文中特別說明,其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。
此外,為易於說明,本文中可能使用例如「之下(beneath)」、「下面(below)」、「下部的(lower)」、「上方(above)」、「上部的(upper)」等空間相對關係用語來闡述圖中所示的一個元件或特徵與另一(其他)元件或特徵的關係。所述空間相對關係用語旨在除圖中所繪示的取向外亦囊括元件在使用或操作中的不同取向。所述裝置可具有其他取向(旋轉90度或處於其他取向)且本文中所用的空間相對關係描述語可同樣相應地進行解釋。
圖1例示本揭露一些實施例之一半導體元件結構的剖視示意圖。如圖1所示,半導體元件結構100包括一第一半導體晶粒110;一矽層111,設置在第一半導體晶粒100上;一第一遮罩層113,設置在矽層111上;一第二遮罩層115,設置在第一遮罩層113上;以及一第二半導體
晶粒180,設置在第二遮罩層115上。
在一些實施例中,第一半導體晶粒110具有一半導體基底101;一介電層103,設置在半導體基底101上;以及複數個導電墊105a、105b、105c,設置在介電層103上。在一些實施例中,該等導電墊105a、105b、105c係面對矽層111配置。類似於第一半導體晶粒110,第二半導體晶粒180具有一半導體基底171;一介電層173;以及複數個導電墊175a、175b、175c、175d、175e,設置在介電層173上。在一些實施例中,導電墊175a、175b、175c、175d、175e係面對第二遮罩層115配置。
仍請參考圖1,依據一些實施例,半導體元件結構100亦包括一矽穿孔169,係穿經矽層111、第一遮罩層113以及第二遮罩層115。在一些實施例中,矽穿孔169將在第一半導體晶粒110中的導電墊105c電性連接到在第二半導體晶粒180中的導電墊175d。在一些實施例中,矽穿孔169設置在一排除區(keep-out zone)中,該排除區係用於界定沒有主動元件置放在其中的一區域。
尤其是,矽穿孔169包括一導電層167’;一阻障層165’,圍繞導電層167’設置;以及一襯墊層163’,圍繞阻障層165’設置。在一些實施例中,阻障層165’覆蓋導電層167’的下表面與各側壁,而襯墊層163’覆蓋阻障層165’的各側壁。在一些實施例中,阻障層165’與襯墊層163’係直接接觸導電墊105c,而導電層167’係藉由阻障層165’而與導電墊105c分隔開。
再者,如圖1所示,依據一些實施例,矽穿孔169具有一瓶形(bottle-shaped)輪廓。此外,依據一些實施例,第二遮罩層115的各側壁SW2係相對於第一遮罩層113的各側壁SW1傾斜,以及第一遮罩層113
的各側壁SW1係大致對準矽層111的各上側壁USW。在本揭露的內容中,字詞「大致地(substantially)」係指較佳者為至少90%,更佳者為95%,再更佳者為98%,以及最佳者為99%。
再者,依據一些實施例,第一半導體晶粒110的臨界尺寸係大於第二半導體晶粒180的臨界尺寸。在一些實施例中,第二半導體晶粒180的圖案密度係大於第一半導體晶粒110的圖案密度。在一些實施例中,直接接觸矽穿孔169的導電墊105c係具有一寬度W1,直接接觸矽穿孔169的導電墊175d係具有一寬度W2,而寬度W1大於寬度W2。在一些實施例中,在第一半導體晶粒110中的兩個相鄰導電墊105之間的一橫向距離,係大於在第二半導體晶粒180中的兩個相鄰導電墊175之間的一橫向距離。舉例來說,橫向距離D1大於橫向距離D2。由於矽穿孔169具有一瓶形輪廓,所以矽穿孔169可用於電性連接具有不同設計規則(例如不同圖案密度或是不同臨界尺寸)的第一半導體晶粒110與第二半導體晶粒180。舉例來說,具有較大寬度W1的導電墊105c係接觸矽穿孔169的一較寬下部,而具有較小寬度W2的導電墊175d係接觸矽穿孔169的一下部。
圖2例示本揭露一些實施例之圖1的放大示意圖。圖2係例示矽穿孔169及其周圍。在一些實施例中,矽穿孔169包括一上部169a、一下部169c以及一瓶頸形狀部169b,瓶頸形狀部169b夾置在上部169a與下部169c之間。虛線I-I’係表示上部169a與瓶頸形狀部169B的邊界,以及虛線II-II’係表示瓶頸形狀部169b與下部169c的邊界。如上所述,依據一些實施例,矽穿孔169具有一下寬度W3(意即下部169c的最下面寬度)以及一上寬度W4(意即上部169a的最上面寬度),下寬度W3大於上寬度W4。請參考圖1及圖2,矽穿孔169的下部169c接觸具有較大寬度W1的導電墊
105c,以及矽穿孔169的上部169a接觸具有較小寬度W2的導電墊175d。因此,矽穿孔169可用於電性連接具有不同設計規則的第一半導體晶粒110與第二半導體晶粒180。
在一些實施例中,矽穿孔169的上部169a係被第二遮罩層115所圍繞,且矽穿孔169的上部169a具有一錐形輪廓,係朝向矽穿孔169的瓶頸形狀部169b逐漸變細。換言之,矽穿孔169之上部169a的各寬度係沿從下到上的一方向逐漸增加。在一些實施例中,矽穿孔169的瓶頸形狀部169b係被第一遮罩層113與矽層111的一上部111U所圍繞,以及矽穿孔169之瓶頸形狀部169b的各寬度係大致相同。
再者,矽穿孔169的下部169c係被矽層111的一下部111L所圍繞。在一些實施例中,矽穿孔169的下部169c具有多個圓形及凸面的上角落C。在一些實施例中,矽穿孔169的下部169c係部分被矽層11所覆蓋。此外,矽穿孔169具有一上表面169T(意即矽穿孔169與在第二半導體晶粒180中的導電墊175d之間的界面)以及一下表面169B(意即矽穿孔169與在第一半導體晶粒110中的導電墊105c之間的界面)。在一些實施例中,下表面169B大於上表面169T,以及上表面169T大於矽穿孔169的一剖面,該剖面係在上表面169T與下表面169B之間,且平行於上表面169T與下表面169B,例如瓶頸形狀部169B的剖面CS。意即,依據一些實施例,矽穿孔169的下寬度W3大於矽穿孔169的上寬度W4。
圖3例示本揭露一些實施例之一改良半導體元件結構200的剖視示意圖,而半導體元件結構200係為半導體元件結構100之另外的實施例。出於一致性及清楚的原因,同時在圖1及圖3所出現的類似元件,係標示相同的元件編號。
類似於半導體元件結構100,半導體元件結構200具有一矽穿孔269,設置在一排除區中。矽穿孔269具有一導電層267’;一阻障層265’,圍繞導電層267’設置;以及一襯墊層263’,圍繞阻障層265’設置。半導體元件結構100與200之間的一差異還包括一保護層161’。如圖3所示,依據一些實施例,第二遮罩層115的各側壁SW2、第一遮罩層113的各側壁SW1以及矽層111的各上側壁USW係被保護層161’所覆蓋。
圖4例示本揭露一些實施例之一圖3的放大示意圖。圖4例示矽穿孔269、保護層161’及其周圍。在一些實施例中,矽穿孔269具有一上部269a、一下部269c以及一瓶頸形狀部269b,而瓶頸形狀部269b夾置在上部269a與下部269c之間。虛線I-I’係表示上部269a與瓶頸形狀部269b的邊界,而虛線II-II’係表示瓶頸形狀部269b與下部269c的邊界。
在一些實施例中,矽穿孔269的上部269a係被第二遮罩層115所圍繞,以及矽穿孔269的上部269a具有一錐形輪廓,係朝向矽穿孔269的瓶頸形狀部269b逐漸變細。換言之,矽穿孔269之上部269a的各寬度係沿從下到上的一方向逐漸增加。在一些實施例中,矽穿孔269的瓶頸形狀部269b係被第一遮罩層113與矽層111的一上部111U所圍繞,以及矽穿孔269之瓶頸形狀部269b的各寬度係大致相同。
再者,矽穿孔269的下部269c係被矽層111的一下部111L所圍繞。在一些實施例中,矽穿孔269的下部269c具有多個圓形及凸面上角落C。在一些實施例中,矽穿孔269的下部269c係部分被矽層111所覆蓋。此外,矽穿孔269具有一上表面269T(意即矽穿孔269與在第二半導體晶粒180中的導電墊175d之間的界面)以及一下表面269B(意即矽穿孔269與在第一半導體晶粒110中的導電墊105c之間的界面)。在一些實施例中,下表
面269B大於上表面269T,以及上表面269T大於矽穿孔269的一剖面,該剖面係位在上表面269T與下表面269B之間,請平行於上表面269T與下表面269B,例如瓶頸形狀部269b的剖面CS。在一些實施例中,矽穿孔269具有一下寬度W5(意即下部269c的最下面寬度)以及一上寬度W6(意即上部269a的最上面寬度),以及下寬度W5大於上寬度W4。請參考圖3及圖4,矽穿孔269的下部269c接觸具有較大寬度W1的導電墊105c,而矽穿孔269的上部269a接觸具有較小寬度W2的導電墊175d。因此,矽穿孔269可用於電性連接具有不同設計規格的第一半導體晶粒110與第二半導體晶粒180。
應當理解,依據一些實施例,第一遮罩層113、第二遮罩層115以及矽層111的上部111U係藉由保護層161’而與矽穿孔269分隔開。在一些實施例中,矽穿孔269的上部269a與瓶頸形狀部269b係被保護層161’所圍繞。在一些實施例中,矽穿孔269的下部269c直接接觸矽層111的下部111L。
圖5例示本揭露一些實施例之一半導體元件結構(包括半導體元件結構100與改良的半導體元件結構200)之製備方法10的流程示意圖,製備方法10包括步驟S11、S13、S15、S17、S19、S21、S23、S25、S27以及S29。圖5的該等步驟S11到S29係結合下列圖式進行詳細說明。
圖6到圖18例示本揭露一些實施例在半導體元件結構100形成期間之各中間階段的剖視示意圖。如圖6所示,依據一些實施例,係提供具有半導體基底101、介電層103以及導電墊105a、105b、105c的第一半導體晶粒110,以及矽層111形成在第一半導體晶粒110上。其個別步驟
係繪示在如圖5所示之製備方法10中的步驟S11。
第一半導體晶粒110可為積體電路(IC)晶片的一部分,其係具有各式不同的被動與主動微電子元件,例如電阻器、電容器、電感器、二極體、p型場效電晶體(pFETs)、n型場效電晶體(nFETs)、金屬氧化物半導體場效電晶體(MOSFETs)、互補式金屬氧化物半導體(complementary metal-oxide-semiconductor,CMOS)電晶體、雙極性電晶體(bipolar junction transistor,BJTs)、橫向擴散MOS(laterally diffused MOS,LDMOS)電晶體、高電壓電晶體、高頻率電晶體、鰭式場效電晶體(FinFETs)、其他適合的IC元件或其組合。
取決於IC的製造階段,第一半導體晶粒110可包括各式不同的材料層(例如介電層、半導體層及/或導電層),經配置以形成IC特徵(例如摻雜區、絕緣區、閘極特徵、源極/汲極特徵、內連接特徵、其他特徵或其組合)。為了清楚起見,係已簡化第一半導體晶粒110。應當理解,可在第一半導體晶粒110中加入額外的特徵,以及下列所描述的一些特徵係可在其他實施例中被取代、改良或排除。在一些實施例中,矽層111磊晶地生長在第一半導體晶粒110上。
接著,如圖7所示,依據一些實施例,第一遮罩層113形成在矽層111上,以及第二遮罩層115形成在第一遮罩層113上。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S13。在一些實施例中,第一遮罩層113與第二遮罩層115包含介電材料,例如氧化矽、氮化矽、氮氧化矽,且其製作技術包含多個沉積製程,例如化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程、旋轉塗佈製程。再者,依據一些實施例,一圖案化遮罩117形成在第二遮罩層115上。在一些實施例中,圖案化遮罩117
具有一開孔(opening)120,係暴露第二遮罩層115的一部分。
接下來,如圖8所示,依據一些實施例,藉由使用圖案化遮罩117當作一遮罩以蝕刻第二遮罩層115,以便形成穿經第二遮罩層115的一開孔130。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S15。在一些實施例中,第一遮罩層113的一部分係藉由在第二遮罩層115中的開孔130而暴露。該蝕刻製程可為一乾蝕刻製程、一濕蝕刻製程或其組合。在該蝕刻製程之後,可移除圖案化遮罩117。
然後,如圖9所示,依據一些實施例,藉由使用第二遮罩層115當作一遮罩以蝕刻第一遮罩層113,以便形成穿經第一遮罩層113的一開孔140。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S17。在一些實施例中,矽層111的一部分係藉由在第一遮罩層113中的開孔140而暴露。該蝕刻製程可為一乾蝕刻製程、一濕蝕刻製程或其組合。在一些實施例中,在第一遮罩層113中之開孔140的側壁係大致對準在第二遮罩層115中之開孔130的側壁。
如圖10所示,依據一些實施例,在開孔130與140形成之後,係藉由使用第一遮罩層113當作一遮罩以蝕刻矽層111,以便形成穿經矽層111的一開孔150。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S19。該蝕刻製程可為一乾蝕刻製程、一濕蝕刻製程或其組合。
在一些實施例中,導電墊105c係藉由開孔150而暴露。在一些實施例中,第二遮罩層115係包含一材料,相較於第一遮罩層113的材料,第二遮罩層115的該材料係具有一高蝕刻選擇性。因此,在用於形成位在矽層111中之開孔150的蝕刻製程期間,係蝕刻第二遮罩層115以形成一放大的開孔130’。
在一些實施例中,放大的開孔130’具有一錐形輪廓,係朝向位在第一遮罩層113中的開孔140逐漸變細。在一些實施例中,第二遮罩層115相對於第一遮罩層113的各側壁係具有多個傾斜側壁,以及一角度θ係位在第二遮罩層115的該等傾斜側壁與下表面之間。在一些實施例中,角度θ係介於大約46度到大約60度的範圍內。第二遮罩層115的該等側壁細可提供改善的階梯覆蓋(step coverage)給接下來形成的保護層161。
接著,如圖11所示,依據一些實施例,保護層161沉積在第二遮罩層115上,並覆蓋第二遮罩層115的各側壁、第一遮罩層113的各側壁以及矽層111的各上側壁(意即矽層111之上部111U的各側壁)。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S21。應當理解,矽層111的各下側壁(意即矽層111之下部111L的各側壁)並未被保護層161所覆蓋。
圖11的虛線係用於圖例說明矽層111之上部111U與下部111L的邊界。在一些實施例中,保護層161的製作技術包含一非共形的沉積製程,例如一非共形的線狀原子層沉積法(non-conformal liner atomic layer deposition,NOLA)製程。在一些實施例中,保護層161包括一氧化物材料,例如氧化鋁。
然後,如圖12所示,依據一些實施例,藉由使用保護層161當作一遮罩以蝕刻矽層111。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S23。在一些實施例中,矽層111的下部111L為橫向蝕刻,同時因為被保護層161所遮蔽,所以矽層111的上部111U係保持完整。
在一些實施例中,藉由用於形成放大的開孔150’之蝕刻製程以底切矽層111的上部111U。在一些實施例中,放大的開孔150’的製作
技術可包含一等向性蝕刻製程。該等向性蝕刻製程可為一濕蝕刻製程、一乾蝕刻製程或其組合。在一些實施例中,包含硝酸(nitric acid,HNO3)與氫氟酸(hydrofluoric acid,HF)的一蝕刻溶液係用於形成放大的開孔150’。在一些實施例中,該蝕刻溶液還包含磷酸(phosphoric acid,H3PO4)。在其他實施例中,氟基電漿(fluorine-based plasma)係用於形成放大的開孔150’。
如圖13所示,依據一些實施例,在放大的開孔150’形成之後,係移除保護層161。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S25。可藉由一濕蝕刻製程、一乾蝕刻製程或其組合而移除保護層161。在一些實施例中,包含磷酸(H3PO4)的一蝕刻溶液可用於移除保護層161。
接著,如圖14所示,依據一些實施例,一襯墊材料163形成在第二遮罩層115上,並覆蓋開孔130’的各側壁、開孔140的各側壁以及開孔150’的各側壁與下表面。換言之,第二遮罩層115的各傾斜側壁、第一遮罩層113的各側壁、矽層111的各側壁以及導電墊105c的暴露表面,係被襯墊材料163所覆蓋。
襯墊材料163共形地沉積在圖13的結構上,以及襯墊材料163係用於將接下來所形成的多個導電層與矽層111分隔開。在一些實施例中,襯墊材料163包含氧化矽、四乙氧基矽烷(tetraethylorthosilicate,TEOS)氧化物、氮化矽、聚醯亞胺(polyimide)、其他可應用的介電材料或其組合。再者,襯墊材料163的製作技術可包含一熱氧化製程、一CVD製程、一PVD製程或其他可應用的沉積製程。
然後,如圖15所示,依據一些實施例,在襯墊材料163上
執行一非等向性蝕刻製程,以在所有位置垂直地移除相同數量的襯墊材料163,在開孔130’、140、150的各側壁上留下襯墊層163’。執行在襯墊材料163上的非等向性蝕刻製程可為一乾蝕刻製程。依據一些實施例,在非等向性蝕刻製程執行之後,係藉由開孔150’、140、130’暴露導電墊105c。
接下來,如圖16所示,依據一些實施例,一阻障材料165形成在第二遮罩層115與襯墊層163’上。在一些實施例中,導電墊105c的暴露表面並未被阻障材料165所覆蓋。阻障材料165當作是一擴散阻障以避免金屬擴散,且阻障材料165當作在襯墊層163’與接下來所形成的導電材料之間的一黏著層。在一些實施例中,阻障材料165包含TaN、Ta、Ti、TiN、TiSiN、WN、CoW或其組合。阻障材料165的製作技術可包含一CVD製程、一PVD製程、一噴濺製程或其他可應用的製程。
然後,如圖17所示,依據一些實施例,一導電材料167形成在阻障材料165上。在一些實施例中,開孔130’、140、150’的該等餘留部分係被導電材料167所填滿。在導電材料167形成之前,一晶種層(圖未示)可形成在阻障材料165上。
晶種層可為一銅晶種層,且其製作技術可包含一CVD製程、一PVD製程、一噴濺製程、一鍍覆製程,或其他可應用的製程。在一些實施例中,導電材料167包含一低電阻率(resistivity)導電材料,例如銅(Cu)。在一些其他實施例中,導電材料167包含鎢(W)、鋁(Al)、鈦(Ti)、鉭(Ta)、金(Au)、銀(Ag)、其組合,或其他可應用的導電材料。導電材料167的製作技術可包含一CVD製程、一PVD製程、一噴濺製程、一鍍覆製程,或其他可應用的製程。
請參考圖18,依據一些實施例,在導電材料167形成之後,在導電材料167與阻障材料165上執行一平坦化製程,以形成矽穿孔169,且矽穿孔169包括襯墊層163’、阻障層165’以及導電層167’。該瓶碳化製程可包括一化學機械研磨(CMP)製程,其係移除導電材料167與阻障材料165在第二遮罩層115上的該等多餘部分。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S27。
接著,如圖1所示,依據一些實施例,第二半導體晶粒180形成在第二遮罩層115上。其個別步驟係繪示在如圖5所示之製備方法10中的步驟S29。在一些實施例中,第二半導體晶粒180接合到圖17的結構,以使導電墊175a、175b、175c、175d、175e面對矽穿孔169。在第二半導體晶粒180形成之後,係獲得半導體元件結構100。
類似於第一半導體晶粒110,第二半導體晶粒180可為IC晶片的一部分,其係包括各式不同的被動與主動微電子元件,而且第二半導體晶粒180可包括各式不同的材料層,經配置以形成多個IC特徵。在一些實施例中,矽穿孔169電性連接第一半導體晶粒110的導電墊105c與第二半導體晶粒180的導電墊175d。由於第二半導體晶粒180在矽穿孔169之後所形成,所以在用於形成矽穿孔169製程期間,可降低損傷在第二半導體晶粒180中之導電墊175a、175b、175c、175d、175e的風險。
圖19到圖23例示本揭露一些實施例在半導體元件結構200形成期間之各中間階段的剖視示意圖。如圖19所示,依據一些實施例,在藉由使用保護層161當作一遮罩以蝕刻矽層111之後(意即圖12之接下來的步驟),一襯墊材料263形成在保護層161上。使用於形成襯墊材料263的一些材料與製程,係類似於或相同於使用於形成圖14的襯墊材料163的材
料與製程,且其詳細說明不再在文中重複。[0080]
接著,如圖20所示,依據一些實施例,在襯墊材料263上執行一非等向性蝕刻製程,以在所有位置垂直地移除相同數量的襯墊材料263,在開孔130’、140、150’的各側壁上留下襯墊層263’。在襯墊材料263上所執行的非等向性蝕刻製程可為一乾蝕刻製程。依據一些實施例,在非等向性蝕刻製程執行之後,係藉由開孔150’、140、130’暴露導電墊105c。
接下來,如圖21所示,依據一些實施例,一阻障材料265形成在保護層161與襯墊層263’上。使用於形成阻障材料265的一些材料與製程,係類似於或相同於使用於形成圖16之阻障材料165的材料與製程,其詳細說明不再在文中重複。
然後,如圖22所示,依據一些實施例,一導電材料267形成在阻障材料265上。在一些實施例中,開孔130’、140、150’的該等餘留部分係被導電材料267所填滿。在導電材料267形成之前,一晶種層(圖未示)可形成在阻障材料265上。使用於形成導電材料267的一些材料與製程,係類似於或相同於使用於形成圖17之導電材料167的材料與製程,且其詳細說明不再在文中重複。
如圖23所示,依據一些實施例,在導電材料267形成之後,在導電材料267、阻障材料265與保護層161上執行一平坦化製程,一形成矽穿孔269以及保護層161’的一餘留部分。矽穿孔269包括襯墊層263’、阻障層265’以及導電層267’。該平坦化製程可包括一CMP製程,其係移除導電材料267、阻障材料265與保護層161在第二遮罩層115上的該等多餘部分。
接著,如圖3所示,依據一些實施例,第二半導體晶粒180形成在第二遮罩層115上。在一些實施例中,第二半導體晶粒180接合到圖23的結構,以使導電墊175a、175b、175c、175d、175e面對矽穿孔269。在一些實施例中,保護層161’直接接觸第二半導體晶粒180。在第二半導體晶粒180形成之後,係獲得半導體元件結構200。
在一些實施例中,矽穿孔269電性連接第一半導體晶粒110的導電墊105c與第二半導體晶粒180的導電墊175d。由於第二半導體晶粒180在矽穿孔169之後所形成,所以在用於形成矽穿孔169的製程期間,可降低損傷在第二半導體晶粒180中之導電墊175a、175b、175c、175d、175e的風險。
本揭露係提供半導體元件結構100與200的一些實施例。在一些實施例中,形成穿經矽層111、第一遮罩層113以及第二遮罩層115的矽穿孔169與269,以電性連接在垂直方向的第一半導體晶粒110與第二半導體晶粒180。矽穿孔169與269具有瓶形輪廓。舉例來說,矽穿孔169的下表面169B大於矽穿孔169的上表面169T,以及矽穿孔169的上表面169T大於矽穿孔169的一剖面(例如剖面CS),該剖面係在矽穿孔169的上表面169T與下表面169B之間,且平行於矽穿孔169的上表面169T與下表面169B。因此,矽穿孔169與269可用於電性連接具有不同設計規則(例如不同圖案密度或不同臨界尺寸)的第一半導體晶粒110與第二半導體晶粒180。結果,可增加功能密度(functional density)(意即,單位晶片面積之內連接裝置的數量),並提供多個好處,例如提高生產效率、降低成本以及改善效能。
本揭露之一實施例提供一種半導體元件結構。該半導體元
件結構包括一矽層,設置在一第一半導體晶粒上;以及一第一遮罩層,設置在該矽層上。該半導體元件結構亦包括一第二半導體晶粒,設置在該第一遮罩層上;以及一矽穿孔,穿經該矽層與該第一遮罩層。該矽穿孔的一下表面大於該矽穿孔的一上表面,以及該矽穿孔的該上表面大於該矽穿孔的一剖面,該剖面係位在該矽穿孔的該下表面與該上表面之間,且該剖面平行於該矽穿孔的該下表面與該上表面。
本揭露之另一實施例提供一種半導體元件結構。該半導體元件結構包括一矽層,設置在一第一半導體晶粒上;以及一第一遮罩層,設置在該矽層上。該半導體元件結構亦包括一第二遮罩層,設置在該第一遮罩層上;以及一第二半導體晶粒,設置在該第二遮罩層上。該半導體元件結構還包括一矽穿孔,係穿經該矽層、該第一遮罩層以及該第二遮罩層,以電性連接該第一半導體晶粒與該第二半導體晶粒。該矽穿孔具有一瓶形部,該瓶形部係被該第一遮罩層與該矽層的一上部所圍繞,以及該矽穿孔與該第一半導體晶粒之間的一界面面積,係大於該矽穿孔與該第二半導體晶粒之間的一界面面積。
本揭露之另一實施例提供一種半導體元件的製備方法。該製備方法包括形成一矽層在一第一半導體晶粒上;以及形成一第一遮罩層在該矽層上。該製備方法亦包括形成一第一開孔以穿經該第一遮罩層,以及形成一第二開孔以穿經該矽層;以及沉積一保護層在該第一遮罩層上。延伸該保護層以覆蓋該第一遮罩層的一側壁以及該矽層的一上側壁。該製備方法還包括藉由使用該保護層當作一遮罩以蝕刻該矽層,進而底切該矽層的一上部,以便形成一放大的第二開孔。此外,該製備方法包括以一矽穿孔充填該第一開孔與該放大的第二開孔;以及形成一第二半導體晶粒在
該矽穿孔上。
本揭露的該等實施例矽具有一些有利的特徵。藉由形成具有一瓶形輪廓的一矽穿孔,該矽穿孔可用於電性連接在垂直方向及具有不同設計規則的二半導體晶粒(或半導體晶圓)。如此,可提升生產效率,可降低成本,並可改善效能。
雖然已詳述本揭露及其優點,然而應理解可進行各種變化、取代與替代而不脫離申請專利範圍所定義之本揭露的精神與範圍。例如,可用不同的方法實施上述的許多製程,並且以其他製程或其組合替代上述的許多製程。
再者,本申請案的範圍並不受限於說明書中所述之製程、機械、製造、物質組成物、手段、方法與步驟之特定實施例。該技藝之技術人士可自本揭露的揭示內容理解可根據本揭露而使用與本文所述之對應實施例具有相同功能或是達到實質上相同結果之現存或是未來發展之製程、機械、製造、物質組成物、手段、方法、或步驟。據此,此等製程、機械、製造、物質組成物、手段、方法、或步驟係包含於本申請案之申請專利範圍內。
100:半導體元件結構
101:半導體基底
103:介電層
105a:導電墊
105b:導電墊
105c:導電墊
110:第一半導體晶粒
111:矽層
113:第一遮罩層
115:第二遮罩層
163’:襯墊層
165’:阻障層
167’:導電層
169:矽穿孔
171:半導體基底
173:介電層
175a:導電墊
175b:導電墊
175c:導電墊
175d:導電墊
175e:導電墊
180:第二半導體晶粒
D1:橫向距離
D2:橫向距離
SW1:側壁
SW2:側壁
USW:上側壁
W1:寬度
W2:寬度
Claims (20)
- 一種半導體元件結構,包括:一矽層,設置在一第一半導體晶粒上;一第一遮罩層,設置在該矽層上;一第二半導體晶粒,設置在該第一遮罩層上;以及一矽穿孔,穿經該矽層與該第一遮罩層,其中,該矽穿孔的一下表面大於該矽穿孔的一上表面,以及該矽穿孔的該上表面大於該矽穿孔的一剖面,該剖面係位在該矽穿孔的該下表面與該上表面之間,且該剖面平行於該矽穿孔的該下表面與該上表面。
- 如請求項1所述之半導體元件結構,其中該矽穿孔直接接觸在該第一半導體晶粒中的一第一導電墊以及在該第二半導體晶粒中的一第二導電墊。
- 如請求項2所述之半導體元件結構,還包括:一第三導電墊,設置在該第一半導體晶粒中,並鄰近該第一導電墊設置;以及一第四導電墊,設置在該第二半導體晶粒中,並鄰近該第二導電墊設置,其中,在該第一半導體晶粒中的該第三導電墊與該第一導電之間的一橫向距離,係大於在該第二半導體晶粒中的該第四導電墊與該第二導電墊之間的一橫向距離。
- 如請求項1所述之半導體元件結構,還包括一第二遮罩層,設置在該第一遮罩層與該第二半導體晶粒之間,其中,該矽穿孔係穿經該第二遮罩層,以及其中,該第一遮罩層與該第二遮罩層係包含不同材料。
- 如請求項4所述之半導體元件結構,其中該第二遮罩層的一側壁係相對於該第一遮罩層的一側壁傾斜。
- 如請求項5所述之半導體元件結構,還包括一保護層,係覆蓋該第二遮罩層的該側壁、該第一遮罩層的該側壁以及該矽層的一上側壁,其中,該矽層的該上側壁係大致對準該第一遮罩層的該側壁。
- 如請求項1所述之半導體元件結構,其中該矽穿孔包括:一導電層;一阻障層,係覆蓋該導電層的各側壁與一下表面,其中,該阻障層直接接觸該第一半導體晶粒;以及一襯墊層,係覆蓋該阻障層的各側壁。
- 一種半導體元件結構,包括:一矽層,設置在一第一半導體晶粒上;一第一遮罩層,設置在該矽層上;一第二遮罩層,設置在該第一遮罩層上;一第二半導體晶粒,設置在該第二遮罩層上;以及一矽穿孔,係穿經該矽層、該第一遮罩層以及該第二遮罩層,以 電性連接該第一半導體晶粒與該第二半導體晶粒,其中,該矽穿孔具有一瓶形部,該瓶形部係被該第一遮罩層與該矽層的一上部所圍繞,以及該矽穿孔與該第一半導體晶粒之間的一界面面積,係大於該矽穿孔與該第二半導體晶粒之間的一界面面積。
- 如請求項8所述之半導體元件結構,其中該第一半導體晶粒具有一第一臨界尺寸,以及該第二半導體晶粒具有一第二臨界尺寸,而該第一臨界尺寸係大於該第二臨界尺寸。
- 如請求項8所述之半導體元件結構,其中該矽穿孔還包括:一上部,係被該第二遮罩層所圍繞;以及一下部,係被該矽層的一下部所圍繞;其中,該矽穿孔的該瓶形部係夾置在該矽穿孔的該上部與該下部之間,以及該矽穿孔的該上部具有一錐形輪廓,該錐形輪廓係朝該矽穿孔的該瓶形部逐漸變細。
- 如請求項10所述之半導體元件結構,其中該矽穿孔的該下部具有多各圓形及凸面上角落。
- 如請求項10所述之半導體元件結構,其中該矽穿孔的該瓶形部與該上部係藉由一保護層而與該第一遮罩層、該第二遮罩層以及該矽層的該上部分隔開。
- 如請求項12所述之半導體元件結構,其中該矽穿孔的該下部直接接觸該矽層的該下部。
- 如請求項12所述之半導體元件結構,其中該保護層包含氧化鋁。
- 一種半導體元件的製備方法,包括:形成一矽層在一第一半導體晶粒上;形成一第一遮罩層在該矽層上;形成一第一開孔以穿經該第一遮罩層,以及形成一第二開孔以穿經該矽層;沉積一保護層在該第一遮罩層上,其中,延伸該保護層以覆蓋該第一遮罩層的一側壁以及該矽層的一上側壁;藉由使用該保護層當作一遮罩以蝕刻該矽層,進而底切該矽層的一上部,以便形成一放大的第二開孔;以一矽穿孔充填該第一開孔與該放大的第二開孔;以及形成一第二半導體晶粒在該矽穿孔上。
- 如請求項15所述之半導體元件的製備方法,還包括:形成一第二遮罩層在該第一遮罩層上;以及在穿經該第一遮罩的該第一開孔形成之前,係形成一第三開孔以穿經該第二遮罩層。
- 如請求項16所述之半導體元件的製備方法,其中在形成穿經該矽層 的該第二開孔期間,蝕刻該第二遮罩層以形成一放大的第三開孔,以及該放大的第三開孔具有一錐形輪廓,該錐形輪廓係朝向該第一開孔逐漸變細。
- 如請求項15所述之半導體元件的製備方法,其中該保護層的製作技術包含一非共形沉積製程。
- 如請求項15所述之半導體元件的製備方法,還包括在該矽穿孔形成之前,係移除該保護層。
- 如請求項15所述之半導體元件的製備方法,其中該矽層的該上部係覆蓋該矽穿孔的一下部。
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Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120001330A1 (en) * | 2010-06-30 | 2012-01-05 | Globalfoundries Inc. | Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism |
US9837312B1 (en) * | 2016-07-22 | 2017-12-05 | Lam Research Corporation | Atomic layer etching for enhanced bottom-up feature fill |
US20170365487A1 (en) * | 2017-08-31 | 2017-12-21 | L'air Liquide, Societe Anonyme Pour L'etude Et I'exploitation Des Procedes Georges Claude | Chemistries for etching multi-stacked layers |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7564115B2 (en) * | 2007-05-16 | 2009-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Tapered through-silicon via structure |
KR101374338B1 (ko) * | 2007-11-14 | 2014-03-14 | 삼성전자주식회사 | 관통 전극을 갖는 반도체 장치 및 그 제조방법 |
US9406561B2 (en) * | 2009-04-20 | 2016-08-02 | International Business Machines Corporation | Three dimensional integrated circuit integration using dielectric bonding first and through via formation last |
JP5697898B2 (ja) * | 2009-10-09 | 2015-04-08 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置及びその製造方法 |
US8975729B2 (en) * | 2012-01-13 | 2015-03-10 | Qualcomm Incorporated | Integrating through substrate vias into middle-of-line layers of integrated circuits |
US8609529B2 (en) * | 2012-02-01 | 2013-12-17 | United Microelectronics Corp. | Fabrication method and structure of through silicon via |
US9123730B2 (en) * | 2013-07-11 | 2015-09-01 | United Microelectronics Corp. | Semiconductor device having through silicon trench shielding structure surrounding RF circuit |
US8916471B1 (en) * | 2013-08-26 | 2014-12-23 | United Microelectronics Corp. | Method for forming semiconductor structure having through silicon via for signal and shielding structure |
KR102379165B1 (ko) * | 2015-08-17 | 2022-03-25 | 삼성전자주식회사 | Tsv 구조를 구비한 집적회로 소자 및 그 제조 방법 |
US9837394B2 (en) * | 2015-12-02 | 2017-12-05 | International Business Machines Corporation | Self-aligned three dimensional chip stack and method for making the same |
EP3531445B1 (en) * | 2016-09-07 | 2020-06-24 | IMEC vzw | A method for bonding and interconnecting integrated circuit devices |
JP2018157110A (ja) * | 2017-03-17 | 2018-10-04 | 東芝メモリ株式会社 | 半導体装置およびその製造方法 |
US11289402B2 (en) * | 2019-02-22 | 2022-03-29 | Samsung Electronics Co., Ltd. | Semiconductor device including TSV and method of manufacturing the same |
KR102633148B1 (ko) * | 2019-05-28 | 2024-02-06 | 삼성전자주식회사 | 관통 비아를 포함하는 반도체 장치 및 이의 제조 방법 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120001330A1 (en) * | 2010-06-30 | 2012-01-05 | Globalfoundries Inc. | Semiconductor Device Comprising Through Hole Vias Having a Stress Relaxation Mechanism |
US9837312B1 (en) * | 2016-07-22 | 2017-12-05 | Lam Research Corporation | Atomic layer etching for enhanced bottom-up feature fill |
US20170365487A1 (en) * | 2017-08-31 | 2017-12-21 | L'air Liquide, Societe Anonyme Pour L'etude Et I'exploitation Des Procedes Georges Claude | Chemistries for etching multi-stacked layers |
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