TWI741782B - 高頻放大器 - Google Patents

高頻放大器 Download PDF

Info

Publication number
TWI741782B
TWI741782B TW109131095A TW109131095A TWI741782B TW I741782 B TWI741782 B TW I741782B TW 109131095 A TW109131095 A TW 109131095A TW 109131095 A TW109131095 A TW 109131095A TW I741782 B TWI741782 B TW I741782B
Authority
TW
Taiwan
Prior art keywords
inductor
harmonic
frequency amplifier
capacitor
circuit
Prior art date
Application number
TW109131095A
Other languages
English (en)
Other versions
TW202123605A (zh
Inventor
佐佐木善伸
Original Assignee
日商三菱電機股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商三菱電機股份有限公司 filed Critical 日商三菱電機股份有限公司
Publication of TW202123605A publication Critical patent/TW202123605A/zh
Application granted granted Critical
Publication of TWI741782B publication Critical patent/TWI741782B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/193High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only with field-effect devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/58Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64Impedance arrangements
    • H01L23/66High-frequency adaptations
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/32Modifications of amplifiers to reduce non-linear distortion
    • H03F1/3205Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F1/00Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
    • H03F1/56Modifications of input or output impedances, not otherwise provided for
    • H03F1/565Modifications of input or output impedances, not otherwise provided for using inductive elements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/189High-frequency amplifiers, e.g. radio frequency amplifiers
    • H03F3/19High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
    • H03F3/195High-frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H03F3/601Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators using FET's, e.g. GaAs FET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6605High-frequency electrical connections
    • H01L2223/6611Wire connections
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/58Structural electrical arrangements for semiconductor devices not otherwise provided for
    • H01L2223/64Impedance arrangements
    • H01L2223/66High-frequency adaptations
    • H01L2223/6644Packaging aspects of high-frequency amplifiers
    • H01L2223/6655Matching arrangements, e.g. arrangement of inductive and capacitive components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49111Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4911Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
    • H01L2224/49112Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting a common bonding area on the semiconductor or solid-state body to different bonding areas outside the body, e.g. diverging wires
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491Disposition
    • H01L2224/4912Layout
    • H01L2224/49175Parallel arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42Wire connectors; Manufacturing methods related thereto
    • H01L24/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1902Structure including thick film passive components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901Structure
    • H01L2924/1903Structure including wave guides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19105Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2200/00Indexing scheme relating to amplifiers
    • H03F2200/387A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Nonlinear Science (AREA)
  • Amplifiers (AREA)
  • Microwave Amplifiers (AREA)

Abstract

放大元件(T1)放大輸入訊號。諧波匹配電路(3)經由第一電線(W1)連接於放大元件(T1)之輸出端。諧波匹配電路(3)具有:連接於第一電線(W1)之第一電感器(L1)、與第一電感器(L1)串聯之第一電容器(C1)、與第一電感器(L1)並聯之第二電感器(L2),以及與第二電感器(L2)串聯之第二電容器(C2)。第一電感器(L1)與第二電感器(L2)形成呈現減極性互感之減極性耦合。

Description

高頻放大器
本發明係關於高頻放大器。
運作時的低消耗電力化,也就是高效率化,為半導體放大器的基本課題。在以超越微波之高頻放大電力的高頻放大器中,對該課題從電路面的研討之一為所謂的諧波處理。此處,半導體放大信號的頻率為基波,基波之倍數之頻率為諧波。在諧波中,諧波處理為藉由控制從半導體放大器看入之周邊電路阻抗達成高效率運作的手法。
作為實現高頻放大器之高效率電路的例子有F類放大器。F類放大器,是藉由F類負載條件,使汲極電壓的時間波形接近矩形,減少汲極電壓的時間波形與電流的時間波形之重疊部分面積。該F類負載條件是從FET之汲極端子所見,對偶次諧波之負載短路,對奇次諧波之負載開路。藉由如此,可以得到以減少被FET消耗的電力為目的之極高的汲極效率。
然而,實際上存在起因於FET以及電線等部件之寄生電容以及電感,這些都會影響到汲極端子之電壓‧電流之時間波形。因此,F類負載電路在考慮到這些寄生成分下,有需要設計成對偶次諧波短路並對奇次諧波開路。(例如參照專利文獻1) [先前技術文獻] [專利文獻]
專利文獻1:日本特許第5958834號公報。
[發明概要] [發明所欲解決的課題]
然而在習知的高頻放大器中,同時達成基波、二次諧波、三次諧波之阻抗匹配是很困難的問題。
本發明是為了解決上述課題,目的為得到可以同時匹配基波、二次諧波、三次諧波之阻抗的高頻放大器。 [用以解決課題的手段]
關於本發明之高頻放大器,具有放大輸入訊號之放大元件,和經由第一電線連接到前述放大元件之輸出端之諧波匹配電路。前述諧波匹配電路,包含與前述第一電線連接之第一電感器、與前述第一電感器串聯之第一電容器、與前述第一電感器並聯之第二電感器,以及與前述第二電感器串聯之第二電容器。前述第一電感器與第二電感器,特徵為形成呈現減極性互感之減極性耦合。 [發明的效果]
本發明用以經由第一電感器與第二電感器生成減極性之互感,可以降低第一電線之寄生電感的影響。特別是可以實現三次諧波匹配所需之低電感。還有,因為經由第一電感器與第一電容器形成之電路降低諧波匹配電路之影響,使基波之匹配不受影響。因此,可以同時最佳化基波、二次諧波、三次諧波之阻抗
針對高頻放大器,參照圖式說明有關之實施方式。相同或對應之構成元件標示為相同符號,且有省略反覆說明的情況。
實施方式1 第1圖顯示關於實施方式1之高頻放大器之電路圖。第2圖顯示關於實施方式1之高頻放大器之俯視圖。高頻放大器之電路模型利用多層玻璃環氧樹脂基板1構成。
在玻璃環氧樹脂基板1最上層的金屬2上,電晶體T1與輸入匹配電路MC1經由導電性接著劑等被固定。輸入匹配電路MC1連接到電晶體T1之閘極。電晶體T1是從輸入端P1經由輸入匹配電路MC1放大輸入訊號之放大元件,例如為氮化鎵(GaN)系高電子移動率電晶體(High Electron Mobility Transistor,HEMT)。最上層之金屬2經由通孔連接到玻璃環氧樹脂基板1裡面之接地層。電晶體T1之輸出端之汲極焊盤經由電線W1連接諧波匹配電路3。電線W1具有寄生電感L3。
諧波匹配電路3具有:第一電感器L1,與電線W1連接;第一電容器C1,與第一電感器L1串聯;第二電感器L2,與第一電感器L1並聯;以及第二電容器C2,與第二電感器L2串聯。第一電容器C1以及第二電容器C2為晶片電容。
為了對輸入訊號的基波匹配阻抗,電線W1與諧波匹配電路3的連接點連接基波匹配電路MC2之一端。基波匹配電路MC2之另一端連接高頻放大器的輸出端P2。
第3圖顯示關於實施方式1之高頻放大器之透視圖。第4圖顯示第一電感器與第二電感器之透視圖。第一電感器L1由玻璃環氧樹脂基板1由表面數來第1層之配線層以及第3層之配線層形成。第二電感器L2由玻璃環氧樹脂基板1第二層之配線層形成。從玻璃環氧樹脂基板1上所見之平面圖中,第一電感器L1面向電晶體T1之汲極的第一電容器C1以順時針方向捲曲。第二電感器L2在平面圖中面向電晶體T1之汲極的第二電容器C2以逆時針方向捲曲。因為第一電感器L1與第二電感器L2互相以反方向捲曲重疊,形成呈現減極性之互感之減極性耦合。
不考慮互感的情況中,由於電線W1之寄生電感L3之影響,第二電感器L2與第二電容器C2構成之二次諧波共振電路之共振頻率,相較於基波頻率f0設定為比2f0更高。因此,二次諧波共振電路之阻抗,對二次諧波以下之頻率顯現電容性,以及對三次諧波顯現電感性。為了對基本波將二次諧波共振電路降低電容,第一電感器L1與第一電容器C1構成之共振電路之阻抗設定為對基本波顯現電感性。
接下來,針對考慮互感的情況的電路動作做說明。第5圖及第6圖為關於實施方式1之高頻放大器之電路動作之等價電路示意圖。為了簡略說明,基波匹配電路MC2作開路之處理。電晶體T1之內部負載設為Rds,電晶體T1之寄生電容設為Cds。流經第一電感器L1之電流設為i1,流經第二電感器L2之電流設為i2。第一電感器L1之電感值設為L(L1),第二電感器L2之電感值設為L(L2),互感設為-M。
高頻放大器為了進行理想的F類運作,從電晶體T1之輸出端看入諧波匹配電路3之阻抗,對基波為開路,對二次諧波為短路,對三次諧波期望與電晶體T1之寄生電容Cds共振而變成開路。
第5圖中,將第1圖之第一電感器L1與第二電感器L2替換為沒有耦合之電感器。電感器L4對應於由第一電感器L1與第二電感器L2生成之減極性互感。基波電感器L1a之電感值設為L(L1)+M,諧波電感器L2a之電感值設為L(L2)+M,電感器L4之電感值設為-M。調整各定值,使L1a、L2a、C1、C2形成之電路設為在基波顯現開路。藉由如此,基波從電晶體T1之輸出端看入之輸出阻抗可以不受該電路影響。
第5圖之電感器L4流經電流i1與電流i2兩者。第6圖中,將第5圖之電感器L4假想地分割為只流經電流i1的電感器L4a與只流經電流i2之電感器L4b。
電感器L4a之電感值設為L(M1a),電感器L4b之電感值設為L(M1b)。因為第5圖之節點N1與第6圖之節點N11以及N12為同一電位,L(M1a)、L(M1b)可以表示如下。 L(M1a)= - (i1+i2) / i1 × M L(M1b)= - (i1+i2) / i2 × M
此處設n=i1/i2。N為顯示流經第一電感器L1與第二電感器L2之電流之比。上述之L(M1a)、L(M1b)可以使用n表示如下。 L(M1a)= - (1+1/n) × M L(M1b)= - (1+n) × M
電感器L1a與電感器L4a之串聯設為電感器L1b。作為基波電感之電感器L1b之電感值L(L1b)可以表示如下: L(L1b)=L(L1a)+L(M1a)=L(L1)-(1/n)×M
電感器L2a與電感器L4b之串聯設為電感器L2b。作為二次諧波電感之電感器L2b之電感值L(L2b)可以表示如下: L(L2b)=L(L2a)+L(M1b)=L(L2)-n×M
第7圖顯示流經第一電感器與第二電感器之電流比n之頻率依存性。因為電流i1與電流i2之電流路徑只連接LC電路,n之值為實數。雖然主要影響諧波之阻抗的是L4b、L2a、C2,因為n之值會伴隨著頻率增加,可以理解等價之電感值L(L2b)隨著頻率減少。
諧波匹配,特別是三次諧波匹配,在基波的三倍高之頻率中,需要讓和電晶體T1之寄生電容Cds共振之電感值變小。然而,在沒有耦合之習知電路中很難實現。與之相對地,本實施方式中,因為經由第一電感器L1與第二電感器L2生成減極性之互感,可以降低電線W1之寄生電感L3之影響。特別是可以實現在三次諧波匹配需要的低電感值。還有,因為經由第一電感器L1與第一電容器C1形成之電路降低諧波匹配電路3之影響,使基波之匹配不會受到影響。因此,可以同時最佳化基波、二次諧波、三次諧波之阻抗。
接著,將本實施方式之效果與比較例比較進行說明。第8圖顯示關於比較例之高頻放大之電路圖。諧波匹配電路3具有電感器L4與電容器C3組成之二次諧波用共振電路,以及電感器L5與電容器C4組成之三次諧波共振電路。比較例中,電感器L4與電感器L5沒有形成減極性耦合。
第9圖顯示在實施方式1中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。第10圖與第11圖顯示在比較例中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。圖中,fl、fc、fh顯示基波之頻寬下限、頻寬中心、頻寬上限各自之阻抗。2fl、2fc、2fh顯示二次諧波之頻寬下限、頻寬中心、頻寬上限各自之阻抗。3fl、3fc、3fh顯示三次諧波之頻寬下限、頻寬中心、頻寬上限各自之阻抗。fc_o顯示沒有包含諧波匹配電路3的情況中,在基波頻寬中心之阻抗。電晶體T1之輸出阻抗為從電晶體T1之汲極端、內部電流源ls或內部負載Rds看入諧波匹配電路3之阻抗。
從第9~11圖可以理解,相對於實施方式1中對基波、二次諧波、三次諧波之各個頻率有進行匹配,比較例中沒有進行二次諧波之匹配。還有,相較於比較例,實施型態1之三次諧波頻率特性更好。
從第10圖可以理解,比較例中,經由將L4、C3、L5、C4最佳化,F類運作之必要條件:將二次諧波短路,將三次諧波開路的條件被滿足。然而,基波之阻抗從fc_o偏移到fc了。
在放大器中,在一定的反射係數以下進行匹配的頻率範圍寬度稱為寬頻帶性。眾所周知一般放大器的寬頻帶性與電晶體T1之Rds.Cds呈反比。在比較例中,如第10圖所示,fc從不含諧波電路的情況之阻抗fc_o偏移。若電晶體T1之等價寄生電容設為Cd’s,則Cds<Cds’使得寬頻帶性劣化。還有,當Cds’增加時需要補償電容增加之電路,會有輸出匹配電路之損失增加的問題。
在第11圖中,針對基波與三次諧波固定阻抗。從此圖中可以理解,針對基波固定阻抗fc_o,並針對三次諧波將阻抗3fl、3fc、3fh固定為開路時,針對二次諧波之阻抗2fl、2fc、2fh會有從短路端偏移的問題。因此,在比較例中,基波、二次諧波、三次諧波之阻抗難以同時達成匹配。
與之相對地,本實施方式,即使是在高頻放大器中主要的寄生成分之電晶體T1之汲極端焊盤與諧波匹配電路3連接之電線1引起寄生電感的情況中,可以同時達成基波、二次諧波、三次諧波之阻抗匹配。
實施方式2 第12圖顯示關於實施方式2之高頻放大器之電路圖。第13圖顯示關於實施方式2之高頻放大器之俯視圖。諧波匹配電路3經由電線W1與電晶體T1之汲極連接。另一方面,基波匹配電路MC2經由分開設置之電線W2與電晶體T1之汲極連接。電線W2具有寄生電感器L5。基波之基波匹配電路MC2以及諧波匹配電路3和電晶體T1之汲極分離。電線W2被配置為相對於電線W1傾斜。因為如此,可以降低電線間之耦合,基波匹配電路MC2與諧波匹配電路3間的干涉很少。因此,基波匹配電路MC2與諧波匹配電路3可以分別最佳化,使電路設計變得容易。
實施方式3 第14圖顯示關於實施方式3之高頻放大器之電路圖。實施方式1之第二電容器C2對應基波頻率的三倍高之頻率。例如若是3GHz頻帶的放大器,第2電容器C2對應9GHz。因此,第二電容器C2的電容值為1pF以下,並要求精準度。實施方式1中,使用作為第二電容器C2的晶片電容。然而,市售的晶片電容之電容值之步長為粗糙的0.1pF。還有,用以實裝晶片電容之焊盤很大,具有數分之一pF程度的寄生電容。因此,第二電容器C2之電容值的微調很困難。
因此,本實施方式中,將實施方式1的第二電容器C2置換為開路短截線STB1。因此,變得可以微調電容值。還有,因為不需要用以實裝電容的焊盤,可以將電路規模變小。另外,也可以使用與玻璃環氧樹脂基板1配線形成的層間電容代替開路短截線STB1。
實施方式4 在本實施方式中,將在實施方式1構成之電路中的第一電感器L1、第一電容器C1、第二電感器L2、第二電容器C2之定值設定為:從電晶體T1的輸出端看入諧波匹配電路3之阻抗針對二次諧波與電晶體T1內的寄生電容Cds共振開路,針對三次諧波變成短路。藉由如此,高頻放大器可以滿足進行反F類運作的諧波條件。
第15圖顯示在實施方式4中從電晶體之輸出端看入輸出阻抗的示意圖。藉由調整各定值,雖然對基波有很大的影響,但有反F類放大器的阻抗條件,可以理解可以實現對二次諧波之頻率開路、對三次諧波短路的狀態。還有,針對三次諧波,經由減極性互感滿足在寬頻帶上的短路條件。
實施方式5 第16圖顯示關於實施方式5之高頻放大器之電路圖。在實施方式4的構成之上,於第一電感器L1與第一電容器C1之間連接對應基波波長λ的電長度為λ/4之傳輸線TRL1。
實施方式4中,從電晶體T1的電流源看入之針對基波之阻抗受到兩個LC共振電路很大的影響。對此,經由***傳輸線TRL1,可以減少對基波的影響,使電路設計變得容易。
第17圖顯示在實施方式5中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。經由***傳輸線TRL1,可以理解到對基波的影響減少。
1:玻璃環氧樹脂基板 2:金屬 3:諧波匹配電路 C1:第一電容器 C2:第二電容器 C3,C4:電容器 Cds:寄生電容 fl:基波頻寬下限阻抗 fc:基波頻寬中心阻抗 fh:基波頻寬上限阻抗 2fl:二次諧波頻寬下限阻抗 2fc:二次諧波頻寬中心阻抗 2fh:二次諧波頻寬上限阻抗 3fl:三次諧波頻寬下限阻抗 3fc:三次諧波頻寬中心阻抗 3fh:三次諧波頻寬上限阻抗 fc_o:基波頻寬中心阻抗 i1,i2:電流 L1:第一電感器 L2:第二電感器 L1a,L2a:電感器 L3:寄生電感 L4,L4a,L4b,L5:電感器 M:互感 MC1:輸入匹配電路 MC2:基波匹配電路 N1,N11,N12:節點 P1:輸入端 P2:輸出端 Rds:電晶體內部負載 STB1:開路短截線 T1:電晶體(放大元件) TRL1:傳輸線 W1:第一電線 W2:第二電線
[第1圖]顯示關於實施方式1之高頻放大器之電路圖。 [第2圖]顯示關於實施方式1之高頻放大器之俯視圖。 [第3圖]顯示關於實施方式1之高頻放大器之透視圖。 [第4圖]顯示第一電感器與第二電感器之透視圖。 [第5圖]為關於實施方式1之高頻放大器之電路動作之等價電路示意圖。 [第6圖]為關於實施方式1之高頻放大器之電路動作之等價電路示意圖。 [第7圖]顯示流經第一電感器與第二電感器之電流比n之頻率依存性。 [第8圖]顯示關於比較例之高頻放大之電路圖。 [第9圖]顯示在實施方式1中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。 [第10圖]顯示在比較例中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。 [第11圖]顯示在比較例中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。 [第12圖]顯示關於實施方式2之高頻放大器之電路圖。 [第13圖]顯示關於實施方式2之高頻放大器之俯視圖。 [第14圖]顯示關於實施方式3之高頻放大器之電路圖。 [第15圖]顯示在實施方式4中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。 [第16圖]顯示關於實施方式5之高頻放大器之電路圖。 [第17圖]顯示在實施方式5中從電晶體之輸出端看入的輸出阻抗軌跡示意圖。
3:諧波匹配電路
C1:第一電容器
C2:第二電容器
L1:第一電感器
L2:第二電感器
L3:寄生電感
M:互感
MC2:基波匹配電路
P1:輸入端
P2:輸出端
T1:電晶體(放大元件)

Claims (13)

  1. 一種高頻放大器,包括: 放大元件,放大輸入訊號; 諧波匹配電路,經由第一電線與前述放大元件之輸出端連接; 前述諧波匹配電路具有與前述第一電線連接之第一電感器、與前述第一電感器串聯之第一電容器、與前述第一電感器並聯之第二電感器,以及與前述第二電感器串聯之第二電容器; 前述第一電感器與前述第二電感器形成呈現減極性互感之減極性耦合。
  2. 如請求項1之高頻放大器,其中前述第一電感器與前述第二電感器互相以反方向捲曲重疊。
  3. 如請求項1或2之高頻放大器,其中從前述放大元件之前述輸出端看入前述諧波匹配電路之阻抗對前述輸入訊號之基波為開路,對二次諧波為短路,對三次諧波為開路;前述高頻放大器進行F類運作。
  4. 如請求項3之高頻放大器,其中前述第二電感器與前述第二電容器構成之共振電路之阻抗,對前述二次諧波以下之頻率顯現電容性,以及對前述三次諧波顯現電感性; 前述第一電感器與前述第一電容器構成之共振電路之阻抗,對前述基波顯現電感性。
  5. 如請求項1或2之高頻放大器,其中從前述放大元件之前述輸出端看入前述諧波匹配電路之阻抗,成為對前述輸入訊號之二次諧波為開路,對三次諧波為短路;前述高頻放大器進行反F類運作。
  6. 如請求項5之高頻放大器,其中更包括:傳輸線,連接於前述第一電感器與前述第一電容器之間,對應前述輸入訊號之波長λ的電長度為λ/4。
  7. 如請求項1或2之高頻放大器,其中更包括:基波匹配電路,與前述第一電線以及前述諧波匹配電路之連接點連接。
  8. 如請求項1或2之高頻放大器,其中更包括:基波匹配電路,與前述放大元件之前述輸出端經由第二電線連接。
  9. 如請求項8之高頻放大器,其中前述第二電線被配置為相對於前述第一電線傾斜。
  10. 如請求項1或2之高頻放大器,其中前述第一電容器以及前述第二電容器為晶片電容。
  11. 如請求項1或2之高頻放大器,其中前述第二電容器為與多層之玻璃環氧樹脂基板配線形成的層間電容。
  12. 如請求項1或2之高頻放大器,其中前述第二電容器為開路短截線。
  13. 如請求項1或2之高頻放大器,其中前述放大元件為氮化鎵(GaN)系高電子移動率電晶體(HEMT)晶片;前述第一電感器以及前述第二電感器由玻璃環氧樹脂基板配線層形成。
TW109131095A 2019-12-10 2020-09-10 高頻放大器 TWI741782B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/JP2019/048325 WO2021117142A1 (ja) 2019-12-10 2019-12-10 高周波増幅器
WOPCT/JP2019/048325 2019-12-10

Publications (2)

Publication Number Publication Date
TW202123605A TW202123605A (zh) 2021-06-16
TWI741782B true TWI741782B (zh) 2021-10-01

Family

ID=76329986

Family Applications (1)

Application Number Title Priority Date Filing Date
TW109131095A TWI741782B (zh) 2019-12-10 2020-09-10 高頻放大器

Country Status (7)

Country Link
US (1) US20220337204A1 (zh)
JP (1) JP7251660B2 (zh)
KR (1) KR20220088486A (zh)
CN (1) CN114731141A (zh)
DE (1) DE112019007952T5 (zh)
TW (1) TWI741782B (zh)
WO (1) WO2021117142A1 (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020105384A1 (en) * 2000-12-07 2002-08-08 Dent Paul W. Harmonic matching network for a saturated amplifier
CN2872699Y (zh) * 2006-02-14 2007-02-21 沈阳华腾电器设备有限公司 负互感滤波器
US20180198433A1 (en) * 2015-09-09 2018-07-12 Murata Manufacturing Co., Ltd. Frequency-variable lc filter and high-frequency front end circuit

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2503917B2 (ja) * 1993-09-22 1996-06-05 日本電気株式会社 高効率電力増幅器
JP4936965B2 (ja) * 2007-04-12 2012-05-23 株式会社東芝 F級増幅回路
JP2009081605A (ja) * 2007-09-26 2009-04-16 Univ Of Electro-Communications 逆f級増幅回路
JP5958834B2 (ja) * 2011-06-28 2016-08-02 パナソニックIpマネジメント株式会社 高周波電力増幅器
US9531328B2 (en) 2014-12-16 2016-12-27 Nxp Usa, Inc. Amplifiers with a short phase path, packaged RF devices for use therein, and methods of manufacture thereof
JP2019041310A (ja) * 2017-08-28 2019-03-14 株式会社村田製作所 半導体装置
US10587226B2 (en) * 2018-03-20 2020-03-10 Nxp Usa, Inc. Amplifier device with harmonic termination circuit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020105384A1 (en) * 2000-12-07 2002-08-08 Dent Paul W. Harmonic matching network for a saturated amplifier
CN2872699Y (zh) * 2006-02-14 2007-02-21 沈阳华腾电器设备有限公司 负互感滤波器
US20180198433A1 (en) * 2015-09-09 2018-07-12 Murata Manufacturing Co., Ltd. Frequency-variable lc filter and high-frequency front end circuit

Also Published As

Publication number Publication date
JPWO2021117142A1 (zh) 2021-06-17
KR20220088486A (ko) 2022-06-27
US20220337204A1 (en) 2022-10-20
TW202123605A (zh) 2021-06-16
DE112019007952T5 (de) 2022-10-27
CN114731141A (zh) 2022-07-08
WO2021117142A1 (ja) 2021-06-17
JP7251660B2 (ja) 2023-04-04

Similar Documents

Publication Publication Date Title
EP2463905A1 (en) Packaged RF transistor with special supply voltage leads
CN108233881B (zh) 放大器电路和经封装的放大器电路
US10242960B2 (en) Integrated passive device for RF power amplifier package
JP2009232076A (ja) 高周波電力増幅器
JP2013118580A (ja) 高周波増幅器
TWI404085B (zh) 變壓器及其結構與功率放大裝置
US20110050383A1 (en) Planar inductive unit and an electronic device comprising a planar inductive unit
TWI741782B (zh) 高頻放大器
US20220293550A1 (en) Semiconductor device
JP5954974B2 (ja) 高周波増幅器
CN111989861A (zh) 高频功率放大器
US20200259468A1 (en) Power amplifier circuit
JP2014138305A (ja) 高周波電力増幅器
JP6729989B2 (ja) 増幅器
US9887675B2 (en) Power amplifier
JP7418662B2 (ja) ドハティ増幅器
JP6452315B2 (ja) 増幅器
CN113574797B (zh) 高频半导体放大器
JP2014096497A (ja) 半導体装置
JP6678827B2 (ja) 高周波増幅器
WO2021140563A1 (ja) 高周波半導体装置
JP2005311579A (ja) 半導体装置
JP2006025405A (ja) 接続回路装置
JP2012099609A (ja) 高周波半導体装置
JP2023000811A (ja) 高調波処理回路および増幅装置