TWI728604B - 具有封裝內隔室屏蔽及主動電磁相容屏蔽的半導體封裝及其製作方法 - Google Patents
具有封裝內隔室屏蔽及主動電磁相容屏蔽的半導體封裝及其製作方法 Download PDFInfo
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Abstract
一種半導體封裝,包含:一基板,在該基板的一頂表面上至少設置有一半導體晶片;一接地環,在該基板的該頂表面上,環繞著該半導體晶片;一金屬柱強化膠體牆,設在該接地環上,環繞著該半導體晶片;以及一成型模料,僅僅設置在該金屬柱強化膠體牆圍繞的範圍內,並覆蓋該半導體晶片。該金屬柱強化膠體牆包含磁性或可磁化填充物,構成主動電磁相容屏蔽。
Description
本發明係有關於半導體技術領域,特別是有關於一種具有封裝內隔室屏蔽(In-Package Compartmental Shielding)及主動電磁相容屏蔽(active electro-magnetic compatibility shielding)的半導體封裝。
可攜式電子設備,例如行動電話,通常利用多組件半導體模組在單個模製封裝中提供高度的電路整合。多組件半導體模組可包括例如半導體晶粒和安裝在電路板上的多個電子組件。安裝有半導體晶粒和電子組件的電路板係在模封製程中完成封裝,形成包覆成型的半導體封裝結構。
為了確保手機等設備在不同環境中正確操作能達到所需的性能水平,通常還要對包覆成型的半導體封裝進行屏蔽,使其免受電磁干擾(EMI)的影響。上述電磁干擾是由於電磁(例如射頻(RF))輻射和電磁傳導而在電氣系統中產生的不利於元件效能的影響。
隨著晶片模組,例如,系統級封裝(SiP)的體積越來越小,組件之間的距離也跟著縮小,也使得模組內的電路對EMI更敏感,因此有必要在模組內組件之間設置電磁干擾屏蔽。然而,現有技術要在模組內形成屏蔽,製程上十分複雜且成本高昂。因此,目前該技術領域面臨的挑戰是在不增加封裝尺寸及製程複雜度的情況下為包覆成型的半導體封裝提供有效的EMI屏蔽,並且不會顯
著增加封裝成本。
本發明的主要目的在提供一種具有封裝內隔室屏蔽及主動電磁相容屏蔽的半導體封裝,以解決上述先前技藝的不足與缺點。
本發明一方面提供一種半導體封裝,包含:一基板,在該基板的一頂表面上至少設置有一高頻晶片,以及易受高頻訊號干擾的一電路元件;一第一接地環,在該基板的該頂表面上,環繞著該高頻晶片;一第一金屬柱強化膠體牆,設在該第一接地環上,環繞著該高頻晶片;一第二接地環,在該基板的該頂表面上,環繞著該電路元件;一第二金屬柱強化膠體牆,設在該第二接地環上,環繞著該電路元件;一成型模料,至少覆蓋該高頻晶片及該電路元件;以及一導電層,設於該成型模料上,並且與該第一金屬柱強化膠體牆及/或該第二金屬柱強化膠體牆接觸,其中該金屬柱強化膠體牆、第二金屬柱強化膠體牆和導電層中的至少一個包括磁性或可磁化填充物,以構成主動電磁相容屏蔽。根據本發明一實施例,其中,該磁性或可磁化填充物包含黏結的釹鐵硼(NdFeB)磁體。
本發明另一方面提供一種半導體封裝,包含:一基板,在該基板的一頂表面上至少設置有一半導體晶片;一接地環,在該基板的該頂表面上,環繞著該半導體晶片;一金屬柱強化膠體牆,設在該接地環上,環繞著該半導體晶片,其中該金屬柱強化膠體牆包含磁性或可磁化填充物,構成主動電磁相容屏蔽;以及一成型模料,僅僅設置在該金屬柱強化膠體牆圍繞的範圍內,並覆蓋該半導體晶片。根據本發明一實施例,其中,該磁性或可磁化填充物包含黏結的釹鐵硼(NdFeB)磁體。
為讓本發明之上述目的、特徵及優點能更明顯易懂,下文特舉較佳
實施方式,並配合所附圖式,作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用,並非用來對本發明加以限制者。
1、2:半導體封裝
10~12:半導體晶片
13:被動元件
40:噴頭
401:膠體
401c:水平局部液滴
401d:垂直局部液滴
403g:模流通道
100:基板
100a:頂表面
100b:底表面
101:輸出/輸入墊
102、122:打線
108:連接件
120:防焊層
202:接合墊
210~212:接地環
213:重疊處
310~312:金屬柱
410、411、412:金屬柱強化膠體牆
500、501、502、503:成型模料
520:導電層
d1、d2:線徑
h:高度
P1、P2、P3:間距
S:橫向距離
t1:第一厚度
t2:第二厚度
402、522:磁性或可磁化填充物
所附圖式係提供用以方便對本發明更進一步的了解,其構成本說明書的一部分。所附圖式與說明書內容一同闡述之本發明實施例,有助於解釋本發明的原理原則。在圖式中:圖1至圖5為依據本發明一實施例所繪示的一種具有封裝內隔室屏蔽的半導體封裝的製作方法示意圖;圖6及圖7例示設置在半導體晶片之間的重疊處的金屬柱的部份上視示意圖;圖8及圖9為依據本發明另一實施例所繪示的一種具有封裝內隔室屏蔽的半導體封裝的製作方法示意圖;圖10及圖11為依據本發明其它實施例所繪示的單晶片封裝側視示意圖;圖12例示局部液滴被佈置在金屬柱上形成膠體網絡;以及圖13例示通過選擇特定的磁化方向而增強EMI屏蔽效果的示意圖。
在下文中,將參照附圖說明細節,該些附圖中之內容亦構成說明書細節描述的一部份,並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。當然,亦可採行其他的實施例,或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此,下文之細節描述不應被視為是限制,反之,其中所包含的實施例將由隨附的申請專利範圍來加以界定。
本公開披露一種具有封裝內隔室屏蔽(In-Package Shielding)的半導體封裝,例如,系統級封裝(System in a Package,SiP),及其製作方法。SiP係指將多個功能晶片,包括處理器、記憶體等功能晶片及其他組件,例如被動元件,整合在單一封裝內,而能實現一完整的功能。如前所述,隨著電子系統變得越來越小以及SiP封裝內電子組件的密度越來越高,因此容易產生系統內的電磁干擾(EMI),尤其一些高頻晶片封裝結構,例如,射頻晶片、GPS晶片、藍芽晶片等高頻晶片透過SiP封裝為一體式結構,容易產生封裝內電子組件之間的電磁干擾。本發明於是提出一種製程簡化、低成本且有效的半導體封裝的製作方法,能夠具體解決現有技術面臨的問題。
圖1至圖5為依據本發明一實施例所繪示的一種具有封裝內隔室屏蔽的半導體封裝1的製作方法示意圖。如圖1所示,首先提供一基板100,例如,一電路板或一封裝基板。根據本發明一實施例,例如,基板100可以是雙層基板(例如,具有核心層和兩個金屬層的基板),但不限於此。基板100可包括陶瓷材料、層壓絕緣材料或其他合適類型的材料。儘管未在圖1中示出,基板100還可以包括在其頂表面100a和底表面100b和通孔上的圖案化金屬層或跡線(trace)。此外,在基板100頂表面100a和底表面100b上可以另設有一防焊層120(又稱為綠漆)。
根據本發明一實施例,在基板100的頂表面100a上可以設置有多個彼此靠近的半導體晶片10~12。例如,半導體晶片10可以是電源管理晶片(power management IC,PMIC),半導體晶片11可以是射頻晶片(RFIC),半導體晶片12可以是功率放大器晶片(power amplifier IC,PAIC),但不限於此。
熟習該項技藝者應理解以上半導體晶片10~12的種類僅為例示說明。為達到不同的電路功能,基板100上還可以設置其他不同的半導體晶片或元件,例如,處理器、快閃記憶體(flash memory)或動態隨機存取記憶體(dynamic random access memory,DRAM)、控制晶片等。根據本發明一實施例,在基板100
的頂表面100a上至少設置有一高頻晶片,例如,半導體晶片11,以及易受高頻訊號干擾的電路元件或晶片,例如,半導體晶片12。
根據本發明一實施例,例如,半導體晶片10及12可以是以打線接合(wire bonding)方式設置在基板100的頂表面100a上,半導體晶片11可以是以覆晶接合(flip chip bonding)方式設置在基板100的頂表面100a上,但不限於此。根據本發明一實施例,半導體晶片10~12可以是裸晶(bare die)形式或者晶片封裝(chip package)形式。
例如,半導體晶片10的主動面上可以設置有多個輸出/輸入墊(input/output pad,I/O pad)101,經由打線102電連接至基板100的頂表面100a上的相應接合墊202(通常又稱金手指)。根據本發明一實施例,打線102可以是金線或銅線等,而接合墊202的表面通常設置有可焊接鍍層(solderable coating),例如,鎳金層或銅金層等。例如,半導體晶片12可以透過打線122電連接至基板100的頂表面100a。
根據本發明一實施例,在基板100的頂表面100a上可以另設置有多個被動元件13。例如,被動元件13可以是電容元件、電感元件、電阻元件等,但不限於此。根據本發明一實施例,被動元件13可以是利用表面黏著技術(surface-mount technology,SMT)設置在基板100的頂表面100a上,但不限於此。根據本發明一實施例,被動元件13可以設置在半導體晶片10~12之間的基板100的頂表面100a上。
根據本發明一實施例,例如,在半導體晶片11及12的周圍的基板100的頂表面100a上,分別設置有接地環211及212,其中,接地環211環繞著半導體晶片11,而接地環212環繞著半導體晶片12。根據本發明一實施例,接地環211及212可以是連續的環狀圖案,但不限於此。在其他實施例中,接地環211及212可以是連續的環狀圖案或者是排列成環狀的接墊圖案。
例如,接地環211及212可以是由基板100內的圖案化金屬層所構成,其表面具有可焊接鍍層,例如,鎳金層或銅金層等。接地環211及212可以進一步透過通孔與一接地層(圖未示)電連接。根據本發明一實施例,接地環211及212可以有部分重疊或共用部分,例如,在半導體晶片11及12的之間的重疊處213,但不限於此。在其他實例中,接地環211及212可以是彼此獨立的環狀圖案。
根據本發明一實施例,在接地環211上設置有多個金屬柱311,而在接地環212上設置有多個金屬柱312。根據本發明一實施例,金屬柱311、312可以是包含銅、銀、金、鋁、鎳、鈀、其任何組合或合金,或任何合適的導電材料。例如,金屬柱311、312可以是銅柱或銅鎳合金柱,但不限於此。根據本發明一實施例,金屬柱311至少排列成一列,且金屬柱312至少排列成一列,但不限於此。根據本發明一實施例,在前述的半導體晶片11及12的之間的重疊處213,金屬柱311與金屬柱312之間是彼此交錯的排列,如圖1中右側放大側視圖所示,如此以達到較佳的電磁干擾屏蔽效果。
根據本發明一實施例,金屬柱311、312可以是利用打線方式形成的,其中各金屬柱311、312一端固定在接地環211、212上,另一端則是懸空的,如圖1所示,各金屬柱311、312筆直的朝向上,如同圍籬般分別圍繞著半導體晶片11及12。根據本發明一實施例,金屬柱311、312具有一約略相同的高度h,其中高度h高於後續預定形成的成型模料的目標厚度(研磨後)。圖1雖繪示金屬柱311、312分別圍繞著半導體晶片11及12,然而,熟習該項技藝者應理解,金屬柱311、312可以分別圍繞著半導體晶片11及12的部分周邊,例如,半導體晶片11及12的單邊或雙邊等,而不是完全圍繞,例如,在另一實施例中,金屬柱311、312僅設置在半導體晶片11及12的之間的重疊處213。
請參閱圖6及圖7,其例示設置在半導體晶片11及12之間的重疊處213的金屬柱311、312的部份上視示意圖。如圖6所示,金屬柱311的線徑d1與金屬柱
312的線徑d2可以彼此相等或不相等。金屬柱311之間的間距P1、金屬柱312之間的間距P2及金屬柱311、312之間的間距P3,彼此可以相等或不相等。金屬柱311、312之間的橫向距離S可以是大於或等於0。根據本發明一實施例,例如,金屬柱311、312之間的橫向距離S可以是介於欲屏蔽電磁波的波長的約十分之一約到百分之一的範圍內,但不限於此。可以選擇金屬柱311、312的橫向距離S的值以為特定頻率或頻率範圍提供EMI屏蔽。
舉例來說,如圖7所示,金屬柱311的線徑d1與金屬柱312的線徑d2可以彼此相等,例如,大於或等於15微米,而金屬柱311之間的間距P1與金屬柱311、312之間的間距P3彼此相等,例如,約等於30微米。需理解的是,上述參數,包括金屬柱311的線徑d1、金屬柱312的線徑d2、金屬柱311之間的間距P1、金屬柱312之間的間距P2及金屬柱311、312之間的間距P3,均可以視實際設計需求而調整。
根據本發明一實施例,金屬柱311、312可以是與半導體晶片10及12的打線接合步驟同時進行並且可以在同一打線機台中完成。此外,根據本發明一實施例,金屬柱311、312的線徑可以與半導體晶片10及12上的打線102及打線122的線徑相同,也可以不相同。例如,金屬柱311、312的線徑可以大於半導體晶片10及12上的打線102及打線122的線徑。此外,金屬柱311、312的材料可以與半導體晶片10及12上的打線102及打線122的材料相同,也可以不相同。
如圖2所示,在完成金屬柱311、312的設置後,接著進行一噴膠製程,利用一噴頭40將一膠體401沿著接地環211及212噴灑在金屬柱311、312上,其中使膠體401附著在金屬柱311、312的表面上並填入金屬柱311、312之間的空隙。根據本發明一實施例,膠體401可以是熱固性樹脂、熱塑性樹脂、UV固化樹脂等,但不限於此。根據本發明一實施例,膠體401可以是導電膠,例如,銀膠或鋁膠。根據本發明一實施例,膠體401可以包含有導電顆粒,例如,銅、銀、金、鋁、鎳、鈀、其任何組合或合金、石墨烯,或任何合適的導電材料。根據本發明一
實施例,膠體401還可以包含有填充物(filler),例如,石英顆粒、鑽石顆粒等。根據本發明一實施例,膠體401還可以包含有溶劑或添加劑(例如,交聯劑、催化劑或改質劑)等。
根據本發明一實施例,膠體401可以進一步包括磁性或可磁化填充物402。例如,所述磁性或可磁化填充物402可以是粉末或微球的形式,但不限於此。例如,所述磁性或可磁化填充物402可包括混合或塗覆有樹脂的稀土磁性粉末。例如,所述磁性或可磁化填充物402可以包括黏結的釹鐵硼(NdFeB)磁體。黏結的NdFeB磁體的表面可以塗覆環氧樹脂,以防止氧化和腐蝕。根據設計要求,黏結的NdFeB磁體可以製成多極磁化強度,例如圓周、內徑或上下。如果產品需要承受高溫環境,例如,可以使用AlNiCo磁體。
圖12例示局部液滴可用於在各層的金屬柱310a和310b上形成膠體網絡。如圖12所示,垂直局部液滴401d和水平局部液滴401c在金屬柱310a和310b上可以形成倒U形膠體圖案。倒U形膠體圖形在金屬柱310a和310b之間產生模流通道403g。膠體401的流動性可以通過控制塗膠期間的溫度來調節。
後續,可以進行一固化製程,例如,加熱或UV照射,使得黏附在金屬柱311、312表面上的膠體401達到固化或者半固化的程度。膠體401可以強化金屬柱311、312,使其在製程中不會倒塌,此外,也可以提升電磁干擾的屏蔽效果及散熱效能。在完成固化製程之後,即在基板100的頂表面100a上形成金屬柱強化膠體牆(metal-pillar reinforced glue walls)411及412,其中金屬柱強化膠體牆411包含環繞著半導體晶片11的金屬柱311及經過固化或半固化的膠體401,金屬柱強化膠體牆412包含環繞著半導體晶片12的金屬柱312及經過固化或半固化的膠體401。根據本發明一實施例,上述固化製程的固化溫度不超過混合在膠體401中的磁性或可磁化填充物402的居里點(Curie point),以防止磁性或可磁化填充物402失去其永久磁性。根據另一實施例,可在封裝階段或後SMT系統階段之後執行
對磁性或可磁化填充物402進行磁化的過程。
根據本發明其它實施例,若金屬柱311的線徑d1與金屬柱312的線徑d2較粗,例如,大於或等於25微米,或者,大於或等於35微米,此時,也可以省略噴膠製程。此外,在其他實施例中,也可以選擇在圖2中所示的在接地環上設置金屬柱之後,才進行圖1中所示在基板的頂表面上設置半導體晶片(包括晶片接合、打線或覆晶接合等)步驟。
如圖3所示,接著進行一模封製程,在基板100的頂表面100a上形成一成型模料500。根據本發明一實施例,成型模料500可以包含樹脂材料,例如,熱固性樹脂、熱塑性樹脂、UV固化樹脂等,但不限於此。根據本發明一實施例,成型模料500的組成與膠體401的組成不同,例如,膠體401的組成中可以包含有導電顆粒,而成型模料500的組成中則通常不含有導電顆粒。然而,本發明並不限於此,在其它實施例中,成型模料500的組成與膠體401的組成可以相同,或者使成型模料500與膠體401的熱膨脹係數(CTE)、應力或彈性係數等物性能夠互相匹配。
根據本發明一實施例,成型模料500溢出金屬柱強化膠體牆411及412而覆蓋在金屬柱強化膠體牆411及412以外的區域,包括半導體晶片10、打線102、122及被動元件13均被成型模料500包封住。根據本發明一實施例,成型模料500可以利用各種合適的方法形成,例如,壓縮模製(compression molding),但不限於此。根據本發明一實施例,上述模封製程可以進一步包含一固化製程,例如,熱固化製程。根據本發明一實施例,上述固化製程的固化溫度不超過混合在膠體401中的磁性或可磁化填充物402的居里點,以防止磁性或可磁化填充物402失去其永久磁性。對磁性或可磁化填充物402進行磁化的過程可以在封裝階段或後SMT系統階段之後執行。此時,如圖3所示,成型模料500在經過熱固化後,可以具有一第一厚度t1,其中第一厚度t1大於金屬柱311、312的高度h及金屬柱強化膠
體牆411及412的高度。
如圖4所示,在完成模封製程之後,接著可以進行一拋光或研磨製程,將成型模料500的厚度從第一厚度t1縮減至一第二厚度t2,使得金屬柱強化膠體牆411及412的頂面被顯露出來,而且金屬柱311、312的上端面也被顯露出來。此時,成型模料500的上表面與金屬柱強化膠體牆411及412的頂面是約略齊平的。
最後,如圖5所示,在成型模料500上的預定區域,形成一導電層520。根據本發明一實施例,導電層520可以位於半導體晶片11及12和金屬柱強化膠體牆411及412的正上方。導電層520可包括導電塗層,例如,導電墨水,其可包括銅、銀或其他導電金屬。在另一實施例中,導電層520可包括銅、鋁或其他合適金屬的層。根據本發明一實施例,導電層520可以包括磁性或可磁化的填充物522。例如,所述磁性或可磁化的填充物522可以是粉末或微球的形式,但不限於此。例如,所述磁性或可磁化填充物522可以包括混合或塗覆有樹脂的稀土磁性粉末。例如,所述磁性或可磁化的填充物522可以包括黏結的NdFeB磁體。所述黏結的NdFeB磁體的表面可以塗環氧樹脂,以防止氧化和腐蝕。導電層520直接接觸到金屬柱311、312的顯露出的上端面,並透過金屬柱311、312構成接地組態。
需理解的是,圖5中的導電層520的覆蓋範圍及圖案僅為例示說明,本發明不應以此為限。在其它實施例中,成型模料500上的全部表面包括上表面及側表面)可以被導電層520覆蓋。在一些實施例中,導電層520可以僅覆蓋半導體晶片11或12。此時,導電層520會與第一金屬柱強化膠體牆411或412及部分的成型模料500的上表面接觸。
通過在膠體401和導電層520中提供磁性或可磁化的填充物402和522,可以在受屏蔽的半導體晶片周圍產生磁場,從而形成主動電磁相容(EMC)屏蔽。此外,膠體401和導電層520可以經過磁化處理。不同的磁化方向可以形成不同的磁場線圖案。通過選擇特定的磁化方向,如圖13所示,可以針對特定方
向增強EMI屏蔽效果。對磁性或可磁化填充物402進行磁化的過程可以在封裝階段或後SMT系統階段之後執行。
根據另一實施例,在將半導體晶片10~12安裝在基板100上之前,可以先形成金屬柱強化膠體牆411和412。已形成有金屬柱強化膠體牆411和412的基板100可以先存放在存放區域中以便後續進行組裝。
結構上,如圖4及圖5所示,本發明實施例披露一種具有封裝內隔室屏蔽的半導體封裝1,包含:一基板100,在基板100的一頂表面100a上至少設置有一高頻晶片,例如半導體晶片11,以及易受高頻訊號干擾的一電路元件12,例如半導體晶片11。一接地環211,在基板100的頂表面100a上,環繞著高頻晶片,例如半導體晶片11。一金屬柱強化膠體牆411,設在接地環211上,環繞著高頻晶片。一接地環212,在基板100的頂表面100a上,環繞著電路元件。一金屬柱強化膠體牆412,設在接地環212上,環繞著電路元件。一成型模料500,至少覆蓋高頻晶片及電路元件;以及一導電層520,設於成型模料500上,並且與金屬柱強化膠體牆411及/或該金屬柱強化膠體牆412接觸。
根據本發明一實施例,金屬柱強化膠體牆411包含複數個金屬柱311,其中各金屬柱311的一端固定在接地環211上,另一端則懸空,複數個金屬柱311圍繞著高頻晶片。
根據本發明一實施例,金屬柱強化膠體牆412包含複數個金屬柱312,其中各金屬柱312的一端固定在接地環212上,另一端則懸空,複數個金屬柱312圍繞著電路元件。
根據本發明一實施例,金屬柱強化膠體牆411或金屬柱強化膠體牆412另包含一膠體401,附著在金屬柱311或金屬柱312的表面上。根據本發明一實施例,成型模料500的組成與膠體401的組成不同。
請參閱圖8及圖9,其為依據本發明另一實施例所繪示的一種具有封
裝內隔室屏蔽的半導體封裝的製作方法示意圖,其中相同的層、元件或材料仍沿用相同的符號來表示。如圖8所示,類似的,半導體封裝2在基板100的頂表面100a上可以設置有多個彼此靠近的半導體晶片10~12。例如,半導體晶片10可以是電源管理晶片(PMIC),半導體晶片11可以是射頻晶片(RFIC),半導體晶片12可以是功率放大器晶片(PAIC),但不限於此。根據本發明一實施例,在基板100的頂表面100a上至少設置有一高頻晶片,例如,半導體晶片11,以及易受高頻訊號干擾的電路元件或晶片,例如,半導體晶片12。
根據本發明一實施例,例如,半導體晶片10及12可以是以打線接合方式設置在基板100的頂表面100a上,半導體晶片11可以是以覆晶接合方式設置在基板100的頂表面100a上,但不限於此。根據本發明一實施例,半導體晶片10~12可以是裸晶形式或者晶片封裝形式。
根據本發明一實施例,在基板100的頂表面100a上可以另設置有多個被動元件13。例如,被動元件13可以是電容元件、電感元件、電阻元件等,但不限於此。根據本發明一實施例,被動元件13可以是利用表面黏著技術(SMT)設置在基板100的頂表面100a上,但不限於此。根據本發明一實施例,被動元件13可以設置在半導體晶片10~12之間的基板100的頂表面100a上。
根據本發明一實施例,例如,在半導體晶片10~12的周圍的基板100的頂表面100a上,分別設置有接地環210、211及212,其中,接地環210環繞著半導體晶片10,接地環211環繞著半導體晶片11,而接地環212環繞著半導體晶片12。根據本發明一實施例,接地環210~212可以是連續的環狀圖案,但不限於此。在其他實施例中,接地環210~212可以是連續的環狀圖案或者是排列成環狀的接墊圖案。
根據本發明一實施例,在接地環210上設置有多個金屬柱310,在接地環211上設置有多個金屬柱311,而在接地環212上設置有多個金屬柱312。根據
本發明一實施例,金屬柱310~312可以是包含銅、銀、金、鋁、鎳、鈀、其任何組合或合金,或任何合適的導電材料。例如,金屬柱310~312可以是銅柱或銅鎳合金柱,但不限於此。根據本發明一實施例,金屬柱310~312至少排列成一列,但不限於此。
根據本發明一實施例,金屬柱310~312可以是利用打線方式形成的,其中各金屬柱310~312一端分別固定在接地環210~212上,另一端則是懸空的,如圖1所示,各金屬柱310~312筆直的朝向上,如同圍籬般分別圍繞著半導體晶片10~12。圖8繪示金屬柱310~312分別完全連續的圍繞著半導體晶片10~12。
接著進行一噴膠製程,利用一噴頭40將一膠體401沿著接地環210~212噴灑在金屬柱310~312上,其中使膠體401附著在金屬柱310~312的表面上並填入金屬柱310~312之間的空隙。根據本發明一實施例,膠體401可以是熱固性樹脂、熱塑性樹脂、UV固化樹脂等,但不限於此。根據本發明一實施例,膠體401可以是導電膠,例如,銀膠或鋁膠。根據本發明一實施例,膠體401可以包含有導電顆粒,例如,銅、銀、金、鋁、鎳、鈀、其任何組合或合金、石墨烯,或任何合適的導電材料。根據本發明一實施例,膠體401還可以包含有填充物(filler),例如,石英顆粒、鑽石顆粒等。根據本發明一實施例,膠體401還可以包含有溶劑或添加劑(例如,交聯劑、催化劑或改質劑)等。
根據本發明一實施例,膠體401可以進一步包括磁性或可磁化的填充物402。例如,所述磁性或可磁化的填充物402可以是粉末或微球的形式,但不限於此。例如,所述磁性或可磁化填充物402可包括混合或塗覆有樹脂的稀土磁性粉末。例如,所述磁性或可磁化的填充物402可以包括黏結的釹鐵硼(NdFeB)磁體。黏結的NdFeB磁體的表面可以塗覆環氧樹脂,以防止氧化和腐蝕。根據設計要求,黏結的NdFeB磁體可以製成多極磁化強度,例如圓周、內徑或上下。如
果產品需要承受高溫環境,例如,可以使用AlNiCo磁體。
後續,可以進行一固化製程,例如,加熱或UV照射,使得黏附在金屬柱310~312表面上的膠體401達到固化或者半固化的程度。膠體401可以強化金屬柱310~312,使其在製程中不會倒塌,此外,也可以提升電磁干擾的屏蔽效果及散熱效能。在完成固化製程之後,即在基板100的頂表面100a上形成金屬柱強化膠體牆410~412,其中金屬柱強化膠體牆410包含環繞著半導體晶片10的金屬柱310及經過固化或半固化的膠體401,金屬柱強化膠體牆411包含環繞著半導體晶片11的金屬柱311及經過固化或半固化的膠體401,金屬柱強化膠體牆412包含環繞著半導體晶片12的金屬柱312及經過固化或半固化的膠體401。
根據本發明其它實施例,若金屬柱310~312的線徑較粗,例如,大於或等於25微米,或者,大於或等於35微米,此時,也可以省略噴膠製程。或者,只有部分的金屬柱310~312有被噴膠。
如圖9所示,接著進行一模封製程,分別在基板100的頂表面100a上的金屬柱強化膠體牆410~412內形成成型模料501~503。根據本發明一實施例,成型模料501~503可以包含樹脂材料,例如,熱固性樹脂、熱塑性樹脂、UV固化樹脂等,但不限於此。根據本發明一實施例,成型模料501~503的組成與膠體401的組成不同,例如,膠體401的組成中可以包含有導電顆粒,而成型模料501~503的組成中則通常不含有導電顆粒。然而,本發明並不限於此,在其它實施例中,成型模料501~503的組成與膠體401的組成可以相同,或者使成型模料501~503與膠體401的熱膨脹係數、應力或彈性係數等物性能夠互相匹配。
膠體401可以進行磁化處理。不同的磁化方向可以形成不同的磁場線圖案。磁化磁性或可磁化的填充物402的過程可以在封裝階段或後SMT系統階段之後進行。可以選擇磁化方向(因此可以選擇磁場方向)以增強要保護的方向。由磁性或可磁化填充物402產生的磁場可以在單個封裝上主動屏蔽α粒子、β粒
子和EMI。
根據本發明一實施例,成型模料501~503不會溢出金屬柱強化膠體牆410~412,故不會覆蓋金屬柱強化膠體牆410~412以外的區域。換言之,成型模料501覆蓋住半導體晶片10和打線102,成型模料502覆蓋住半導體晶片11,成型模料503覆蓋住半導體晶片12打線122。金屬柱強化膠體牆410~412以外的區域,包括被動元件13不會被成型模料501~503包封住,而可以顯露出來。根據本發明一實施例,成型模料501~503可以利用各種合適的方法形成,例如,壓縮模製或點膠製程,但不限於此。根據本發明一實施例,上述模封製程可以進一步包含一固化製程,例如,熱固化製程。由於僅部分重要的組件是被成型模料501~503包封保護住,故基板100的受到成型模料501~503的應力影響可以減小,進而改善半導體封裝2的翹曲(warpage)問題。後續,可以再進行如圖4及圖5所示的研磨製程及導電層塗佈製程,不另贅述。
根據本發明另一實施例,本公開另揭露一種單晶片封裝。如圖10及圖11所示,在基板100的頂表面100a上設有單顆半導體晶片10,例如,處理器等。在基板100的底表面100b上設有連接件108,例如,球柵陣列(ball grid array,BGA)錫球。半導體晶片10可以透過以打線接合方式設置在基板100的頂表面100a上(如圖10所示的打線102),或者半導體晶片10可以透過以覆晶接合方式設置在基板100的頂表面100a上(如圖11)。在基板100的頂表面100a上,同樣設有一接地環210,環繞著半導體晶片10。在接地環210上設有一金屬柱強化膠體牆410,環繞著半導體晶片10。金屬柱強化膠體牆410包含複數個金屬柱310,其中各金屬柱310的一端固定在接地環210上,另一端則懸空,且複數個金屬柱310圍繞著半導體晶片10。
金屬柱強化膠體牆410另包含一膠體401,附著在金屬柱310的表面上。根據本發明一實施例,膠體401可以進一步包括磁性或可磁化的填充物402。
例如,所述磁性或可磁化的填充物402可以是粉末或微球的形式,但不限於此。例如,所述磁性或可磁化填充物402可包括混合或塗覆有樹脂的稀土磁性粉末。例如,所述磁性或可磁化的填充物402可以包括黏結的釹鐵硼(NdFeB)磁體。黏結的NdFeB磁體的表面可以塗覆環氧樹脂,以防止氧化和腐蝕。根據設計要求,黏結的NdFeB磁體可以製成多極磁化強度,例如圓周、內徑或上下。如果產品需要承受高溫環境,例如,可以使用AlNiCo磁體。
在金屬柱強化膠體牆410內設有一成型模料501。根據本發明一實施例,成型模料501的組成與膠體401的組成不同,例如,膠體401的組成中可以包含有導電顆粒,例如銅、銀、金、鋁、鎳、鈀、其任何組合或合金、石墨烯。成型模料501的組成中則不含有導電顆粒。然而,本發明並不限於此,在其它實施例中,成型模料501的組成與膠體401的組成可以相同,或者使成型模料501與膠體401的熱膨脹係數、應力或彈性係數等物性能夠互相匹配。成型模料501不會溢出金屬柱強化膠體牆410,故不會覆蓋金屬柱強化膠體牆410以外的區域。成型模料501可以利用各種合適的方法形成,例如,壓縮模製或點膠製程,但不限於此。由於僅半導體晶片10是被成型模料501包封保護住,故基板100的受到成型模料501的應力影響可以減小,進而改善翹曲問題。後續,可以再進行如圖4及圖5所示的研磨製程及導電層塗佈製程,不另贅述。
相較於現有技術,本發明至少具有以下優點:(1)能與現有製程相容,且製程步驟簡化因此成本相對較低;(2)可以最小化半導體封裝或模組的尺寸;(3)在基板上形成金屬柱強化膠體牆或隔室屏蔽結構具有高度彈性;(4)能達到高產能量產(high UPH mass production);以及(5)透過調整金屬柱的排數(tier)、線徑及/或間隔等,可以彈性的應用到各種所欲遮蔽電磁輻射的頻率範圍。
以上所述僅為本發明之較佳實施例,凡依本發明申請專利範圍所做之均等變
化與修飾,皆應屬本發明之涵蓋範圍。
10、11:半導體晶片
100:基板
311:金屬柱
411:金屬柱強化膠體牆
500:成型模料
402、522:磁性或可磁化填充物
Claims (20)
- 一種半導體封裝,包含:一基板,在該基板的一頂表面上至少設置有一高頻晶片,以及易受高頻訊號干擾的一電路元件;一第一接地環,在該基板的該頂表面上,環繞著該高頻晶片;一第一金屬柱強化膠體牆,設在該第一接地環上,環繞著該高頻晶片,其中該第一金屬柱強化膠體牆包含複數個第一金屬柱;一第二接地環,在該基板的該頂表面上,環繞著該電路元件;一第二金屬柱強化膠體牆,設在該第二接地環上,環繞著該電路元件,其中該第二金屬柱強化膠體牆包含複數個第二金屬柱,其中該第一金屬柱強化膠體牆或該第二金屬柱強化膠體牆包含一膠體,其中該膠體包含局部液滴在該複數個第一金屬柱和該複數個第二金屬柱的表面上形成一膠體網絡;一成型模料,至少覆蓋該高頻晶片及該電路元件,其中該成型模料的組成與該膠體的組成不同;以及一導電層,設於該成型模料上,並且與該第一金屬柱強化膠體牆及/或該第二金屬柱強化膠體牆接觸,其中該第一金屬柱強化膠體牆、第二金屬柱強化膠體牆和導電層中的至少一個包括磁性或可磁化填充物,以構成主動電磁相容屏蔽。
- 如申請專利範圍第1項所述的半導體封裝,其中各該複數個第一金屬柱的一端固定在該第一接地環上,另一端則懸空,該複數個第一金屬柱圍繞著該高頻晶片。
- 如申請專利範圍第2項所述的半導體封裝,其中各該複數個第二金屬 柱的一端固定在該第二接地環上,另一端則懸空,該複數個第二金屬柱圍繞著該電路元件。
- 如申請專利範圍第3項所述的半導體封裝,其中該局部液滴包含一垂直局部液滴和一水平局部液滴,在該複數個第一金屬柱和該複數個第二金屬柱的表面上形成至少一倒U形膠體圖案,其中該倒U形膠體圖形在該複數個第一金屬柱和該複數個第二金屬柱之間產生至少一模流通道。
- 如申請專利範圍第1項所述的半導體封裝,其中該膠體包含熱固性樹脂、熱塑性樹脂或UV固化樹脂。
- 如申請專利範圍第1項所述的半導體封裝,其中該膠體係為一導電膠。
- 如申請專利範圍第1項所述的半導體封裝,其中該膠體包含有導電顆粒。
- 如申請專利範圍第7項所述的半導體封裝,其中該導電顆粒包含銅、銀、金、鋁、鎳、鈀、其任何組合或合金、石墨烯。
- 如申請專利範圍第1項所述的半導體封裝,其中該成型模料的上表面與該第一及該第二金屬柱強化膠體牆的頂面是齊平的。
- 如申請專利範圍第1項所述的半導體封裝,其中該磁性或可磁化填充物包含黏結的釹鐵硼(NdFeB)磁體。
- 一種半導體封裝,包含:一基板,在該基板的一頂表面上至少設置有一半導體晶片;一接地環,在該基板的該頂表面上,環繞著該半導體晶片;一金屬柱強化膠體牆,設在該接地環上,環繞著該半導體晶片,其中該金屬柱強化膠體牆包含磁性或可磁化填充物,構成主動電磁相容屏蔽,其中該金屬柱強化膠體牆包含複數個金屬柱,其中該金屬柱強化膠體牆另包含一膠體,附著在該金屬柱的表面上,其中該膠體包含局部液滴在該複數個金屬柱的表面上形成一膠體網絡;以及一成型模料,僅僅設置在該金屬柱強化膠體牆圍繞的範圍內,並覆蓋該半導體晶片。
- 如申請專利範圍第11項所述的半導體封裝,其中各該複數個金屬柱的一端固定在該接地環上,另一端則懸空,該複數個金屬柱圍繞著該半導體晶片。
- 如申請專利範圍第11項所述的半導體封裝,其中該局部液滴包含一垂直局部液滴和一水平局部液滴,在該複數個金屬柱的表面上形成至少一倒U形膠體圖案,其中該倒U形膠體圖形在該複數個金屬柱之間產生至少一模流通道。
- 如申請專利範圍第11項所述的半導體封裝,其中該膠體包含熱固性樹脂、熱塑性樹脂或UV固化樹脂。
- 如申請專利範圍第11項所述的半導體封裝,其中該膠體係為一導電 膠。
- 如申請專利範圍第11項所述的半導體封裝,其中該膠體包含有導電顆粒。
- 如申請專利範圍第16項所述的半導體封裝,其中該導電顆粒包含銅、銀、金、鋁、鎳、鈀、其任何組合或合金、石墨烯。
- 如申請專利範圍第11項所述的半導體封裝,其中該成型模料的組成與該膠體的組成不同。
- 如申請專利範圍第11項所述的半導體封裝,其中該成型模料的上表面與該金屬柱強化膠體牆的頂面是齊平的。
- 如申請專利範圍第11項所述的半導體封裝,其中該磁性或可磁化填充物包含黏結的釹鐵硼(NdFeB)磁體。
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US16/718,156 US11211340B2 (en) | 2018-11-28 | 2019-12-17 | Semiconductor package with in-package compartmental shielding and active electro-magnetic compatibility shielding |
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US20160073496A1 (en) * | 2014-09-04 | 2016-03-10 | Michael B. Vincent | Fan-out wafer level packages having preformed embedded ground plane connections and methods for the fabrication thereof |
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