TWI721848B - 封裝結構及其製造方法 - Google Patents

封裝結構及其製造方法 Download PDF

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TWI721848B
TWI721848B TW109111127A TW109111127A TWI721848B TW I721848 B TWI721848 B TW I721848B TW 109111127 A TW109111127 A TW 109111127A TW 109111127 A TW109111127 A TW 109111127A TW I721848 B TWI721848 B TW I721848B
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chip
circuit structure
connection
conductive
insulator
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TW109111127A
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TW202127619A (zh
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張簡上煜
林南君
徐宏欣
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力成科技股份有限公司
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Abstract

一種封裝結構，其包括重佈線路結構、絕緣體、多個導電連接件、第一晶片、第二晶片、模封體、第三晶片以及多個導電端子。重佈線路結構具有彼此相對的第一連接面及第二連接面。絕緣體嵌入且貫穿重佈線路結構。導電連接件貫穿絕緣體。第一晶片及第二晶片位於第一連接面上。模封體位於重佈線路結構上且至少側向覆蓋第一晶片及第二晶片。第三晶片位於第二連接面上。第三晶片藉由多個導電連接件電性連接第一晶片及第二晶片。導電端子位於第二連接面上。導電端子藉由重佈線路結構電性連接第一晶片或第二晶片。

Description

封裝結構及其製造方法
本發明是有關於一種封裝結構及其製造方法，且特別是有關於一種具有多個晶片的封裝結構及其製造方法。
近年來，電子設備對於人類的生活越來越重要。為了加速各種功能的整合，可以將多個主動晶片整合在一個封裝結構。因此，如何提升多個晶片之間的訊號傳輸的品質或效率，實已成目前亟欲解決的課題。
本發明提供一種封裝結構及其製造方法，可以使多個晶片之間具有較佳的訊號傳輸的品質或效率。
本發明的封裝結構包括重佈線路結構、絕緣體、多個導電連接件、第一晶片、第二晶片、模封體、第三晶片以及多個導電端子。重佈線路結構具有第一連接面以及相對於第一連接面的第二連接面。絕緣體嵌入且貫穿重佈線路結構。多個導電連接件 貫穿絕緣體。第一晶片位於重佈線路結構的第一連接面上。第二晶片位於重佈線路結構的第一連接面上。模封體位於重佈線路結構的第一連接面上且至少側向覆蓋第一晶片及第二晶片。第三晶片位於重佈線路結構的第二連接面上。第三晶片藉由多個導電連接件電性連接第一晶片及第二晶片。多個導電端子位於重佈線路結構的第二連接面上。多個導電端子藉由重佈線路結構電性連接第一晶片或第二晶片。
本發明的封裝結構的製造方法包括以下步驟。提供第一晶片；提供第二晶片；形成覆蓋第一晶片及第二晶片的模封體；形成電性連接於第一晶片及第二晶片的重佈線路結構，且重佈線路結構具有暴露出部分的第一晶片及部分的第二晶片的開口；形成絕緣體，其至少位於重佈線路結構的開口內且暴露出部分的第一晶片及部分的第二晶片；形成多個導電連接件，其貫穿絕緣體；配置第三晶片於絕緣體上，且第三晶片藉由多個導電連接件電性連接第一晶片及第二晶片；以及形成多個導電端子於重佈線路結構上，且多個導電端子藉由重佈線路結構電性連接第一晶片或第二晶片。
基於上述，本發明的封裝結構至少藉由貫穿絕緣體的導電連接件，可以使多個晶片(如：第三晶片與第一晶片；或第三晶片與第二晶片)之間具有較佳的訊號傳輸的品質或效率。
100、200、300:封裝結構
110:第一晶片
110a:主動面
111:基材
112:連接墊
113:絕緣層
114:保護層
115、115a、115b:第一晶片連接件
115c:鍍覆核心層
115d:頂面
115s:種子層
120:第二晶片
120a:主動面
121:基材
122:連接墊
123:絕緣層
124:保護層
125、125a、125b:第二晶片連接件
125d:頂面
130:第三晶片
130a:主動面
131:基材
132:連接墊
133:絕緣層
134:保護層
135:第三晶片連接件
135c:鍍覆層
135s:種子層
135d:導電連接層
149:模封材料
140:模封體
140d:模封頂面
150、350:重佈線路結構
150a:第一連接面
150b:第二連接面
150c、350c:開口
351a:第一絕緣材料層
151:第一絕緣層
151c:第一開口
151d、151e:開口
152:線路層
153a、153a1、153a2、153a3、353a:第二絕緣材料層
153:第二絕緣層
153c:第二開口
153d:開口
156:最頂端絕緣層
157:最頂端線路層
169:絕緣材料
160、360:絕緣體
160c:通孔
161:第一絕緣部分
161R:投影範圍
162:第二絕緣部分
162R:投影範圍
170:導電連接件
171:第一導電連接部分
171R:投影範圍
172:第二導電連接部分
172R:投影範圍
170c:鍍覆核心層
170s:種子層
170e:側壁
181、182:導電端子
191:底膠
292、292a、292b:圖案化導電層
91:載板
92:離型層
P1、P2、P3、P4:間距
R1、R2:區域
圖1A至圖1K是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。
圖1L是依照本發明的第一實施例的一種封裝結構的剖視示意圖。
圖1M是依照本發明的第一實施例的一種封裝結構的部分剖視示意圖。
圖1N是依照本發明的第一實施例的一種封裝結構的部分立體示意圖。
圖1O是依照本發明的第一實施例的一種封裝結構的部分立體示意圖。
圖2A是依照本發明的第二實施例的一種封裝結構的部分製造方法的部分剖視示意圖。
圖2B是依照本發明的第二實施例的一種封裝結構的剖視示意圖。
圖3A至3B是依照本發明的第三實施例的一種封裝結構的部分製造方法的部分剖視示意圖。
圖3C是依照本發明的第三實施例的一種封裝結構的剖視示意圖。
本文所使用之方向用語(例如，上、下、右、左、前、 後、頂部、底部)僅作為參看所繪圖式使用且不意欲暗示絕對定向。另外，為求清楚表示，於圖式中可能省略繪示了部分的膜層或構件。
除非另有明確說明，否則本文所述任何方法絕不意欲被解釋為要求按特定順序執行其步驟。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層或區域的厚度、尺寸或大小會為了清楚起見而放大。相同或相似之參考號碼表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1K是依照本發明的第一實施例的一種封裝結構的部分製造方法的部分剖視示意圖。圖1L是依照本發明的第一實施例的一種封裝結構的剖視示意圖。圖1M是依照本發明的第一實施例的一種封裝結構的剖視示意圖。圖1N是依照本發明的第一實施例的一種封裝結構的部分立體示意圖。圖1O是依照本發明的第一實施例的一種封裝結構的部分立體示意圖。舉例而言，圖1M例如是對應於圖1L中區域R2的放大圖。圖1N例如依照本發明的一實施例的一種封裝結構的絕緣體的部分立體示意圖。圖1O例如依照本發明的一實施例的一種封裝結構的導電連接件的部分立體示意圖。
請參照圖1A，提供第一晶片110及提供第二晶片120。值得注意的是，提供第一晶片110及提供第二晶片120的先後順 序於本發明中並未加以限制。
舉例而言，可以將第一晶片110及提供第二晶片120配置於載板91上。載板91可以由玻璃、晶圓基板、金屬或其他適宜的材料所製成，只要前述的材料能夠於後續的製程中，承載形成於其上的結構或構件。另外，本發明對於配置於載板91上的第一晶片110或第二晶片120的個數並不加以限制。以圖1A為例，配置於載板91上的第一晶片110的個數例如為二個，且配置於載板91上的第二晶片120的個數例如為二個。
在本實施例中，載板91上可以具有離型層92。離型層92可以為光熱轉換(light to heat conversion；LTHC)黏著層，但本發明不限於此。
在本實施例中，第一晶片110可以包括基材111、多個連接墊112以及多個第一晶片連接件115。基材111的一側具有元件區(未繪示)，而元件區所位於的表面可以被稱為主動面110a。連接墊112可以位於主動面110a上。第一晶片連接件115可以位於連接墊112上。在一般晶片設計中，元件區內的元件(如：第一晶片110的元件區內的元件)可以藉由對應的後段金屬內連線(Back End of Line Interconnect；BEOL Interconnect)電性連接於對應的連接墊112(如：第一晶片110的部分連接墊112)及對應的晶片連接件(如：第一晶片110的部分第一晶片連接件115)。
在本實施例中，連接墊112例如為鋁墊或銅墊，但本發明不限於此。
在一實施例中，連接墊112可以被絕緣層113部分覆蓋，且絕緣層113可以暴露出部分的連接墊112。
在一實施例中，保護層(passivation layer)114可以覆蓋絕緣層113，且保護層114可以暴露出部分的連接墊112。
在一實施例中，第一晶片連接件115可以藉由微影製程、濺鍍製程、電鍍製程及/或蝕刻製程形成，但本發明不限於此。舉例而言，第一晶片連接件115可以包括種子層(seed layer)115s(標示於圖1M)以及位於種子層115s上的鍍覆層(plating layer)115c(標示於圖1M)，但本發明不限於此。
在一未繪示的實施例中，第一晶片連接件(如：類似於第一晶片連接件115的第一晶片連接件)可以包括預先成型(pre-formed)的導電件。舉例而言，第一晶片連接件可以包括預先成型的導電柱(pre-formed conductive pillar)，但本發明不限於此。
在本實施例中，多個第一晶片連接件115可以包括多個第一晶片連接件115a以及多個第一晶片連接件115b，但本發明不限於此。
在一實施例中，多個第一晶片連接件115a之間的間距P1可以小於多個第一晶片連接件115b之間的間距P3，但本發明不限於此。
在本實施例中，第二晶片120可以包括基材121、多個連接墊122以及多個第二晶片連接件125。基材121的一側具有元件 區(未繪示)，而元件區所位於的表面可以被稱為主動面120a。
在本實施例中，第二晶片120可以相同或相似於第一晶片110。舉例而言，基材121可以相同或相似於基材111，連接墊122可以相同或相似於連接墊112，絕緣層123可以相同或相似於絕緣層113，保護層124可以相同或相似於保護層114，第二晶片連接件125可以相同或相似於第一晶片連接件115，故於此不加以贅述。
在本實施例中，多個第二晶片連接件125可以包括多個第二晶片連接件125a以及多個第二晶片連接件125b，但本發明不限於此。
在一實施例中，多個第二晶片連接件125a之間的間距P2可以小於多個第二晶片連接件125b之間的間距P4，但本發明不限於此。
在本實施例中，第一晶片110與第二晶片120可以是以並排(side by side)的方式配置。並且，各晶片是以其較小間距的晶片連接件彼此靠近的方式配置。
請參照圖1B及圖1C，形成覆蓋第一晶片110及第二晶片120的模封體140。模封體140可以暴露出部分的第一晶片110及部分的第二晶片120。舉例而言，模封體140可以暴露出第一晶片110的第一晶片連接件115a、115b及第二晶片120的第二晶片連接件125a、125b。
在本實施例中，形成模封體140的步驟舉例如下。
請參照圖1B，可以形成覆蓋第一晶片110及第二晶片120的模封材料149。在一實施例中，模封材料149例如是藉由模塑製程(molding process)或其他適宜的方法將熔融的模塑化合物(molding compound)形成於載板91上。然後，使熔融的模塑化合物冷卻並且固化。在一實施例中，第一晶片110及第二晶片120並不會被暴露於模封材料149之外，但本發明不限於此。
請參照圖1C，在形成模封材料149(標示於圖1B)之後，可以進行減薄製程，以移除部分的模封材料149(標示於圖1B)，以形成側向覆蓋第一晶片110及第二晶片120的模封體140，且暴露出第一晶片110的第一晶片連接件115及第二晶片120的第二晶片連接件125。
在本實施例中，減薄製程例如包括化學機械研磨(chemical mechanical polishing；CMP)、機械研磨(mechanical grinding)、蝕刻(etching)或其他適宜的製程，但本發明不限於此。
在本實施例中，在經由上述的減薄製程之後，第一晶片連接件115的頂面115d、第二晶片連接件125的頂面125d及模封體140的模封頂面140d可以基本上共面(coplanar)。
在一實施例中，在上述的減薄製程中，第一晶片連接件115的一部分(如：第一晶片連接件115遠離基材111的一部分)或第二晶片連接件125的一部分(如：第二晶片連接件125遠離基材121的一部分)可能可以被些微地移除。
在一實施例中，在上述的減薄製程中，第一晶片110的第一晶片連接件115可以降低第一晶片110的主動面110a或元件區受損的可能；且/或第二晶片120的第二晶片連接件125可以降低第二晶片120的主動面120a或元件區受損的可能。
請參照圖1D，形成電性連接於第一晶片110及第二晶片120的重佈線路結構150，且重佈線路結構150具有暴露出部分的第一晶片110、部分的第二晶片120的開口150c及部分的模封體140。舉例而言，重佈線路結構150的開口150c可以暴露出第一晶片110的部分第一晶片連接件115(如：第一晶片連接件115a)、第二晶片120的部分第二晶片連接件125(如：第二晶片連接件125a)及模封體140的部分模封頂面140d。
請參照圖1D及圖1E至圖1G，其中圖1E至圖1G可以是對應於圖1D中區域R1的步驟示意圖。在本實施例中，形成具有開口150c的重佈線路結構150的步驟舉例如下。
請參照圖1E，於模封體140上形成第一絕緣層151。第一絕緣層151具有暴露出第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a的第一開口151c。
在一實施例中，可以藉由沉積製程或其他適宜的製程在模封體140上形成第一絕緣材料層。第一絕緣材料層的材料可以包含無機材料(例如：氧化矽、氮化矽、氮氧化矽、其他適宜的材料、或上述至少二種無機材料的堆疊層)或其他適宜的絕緣材料。然後，例如可以藉由微影及蝕刻製程以將第一絕緣材料層圖 案化，而形成具有開口151c、151d、151e的第一絕緣層151。第一開口151c可以暴露出第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a，開口151d可以暴露出第一晶片110的第一晶片連接件115b，且開口151e可以暴露出第二晶片120的第二晶片連接件125b。
請參照圖1F，在形成第一絕緣層151之後，可以於第一絕緣層151上形成線路層152。線路層152例如可以藉由一般常用的沉積製程及/或電鍍製程等其他適宜的製程所形成，故於此不加以贅述。線路層152可以填入開口151d，以電性連接於第一晶片連接件115b。線路層152可以填入開口151e，以電性連接於第二晶片連接件125b。
請繼續參照圖1F，在形成線路層152之後，可以於於第一絕緣層151上形成第二絕緣材料層153a。第二絕緣材料層153a可以覆蓋線路層152，且第二絕緣材料層153a更填入第一開口151c(標示於圖1E)內。第二絕緣材料層153a可以覆蓋且直接接觸第一晶片連接件115a及第二晶片連接件125a。第二絕緣材料層153a的材質或形成方式可以相同或相似於前述的第一絕緣材料層的材質或形成方式，故於此不加以贅述。
請參照圖1G，移除部分的第二絕緣材料層153a(標示於圖1F)，以形成具有第二開口153c的第二絕緣層153。舉例而言，可以藉由微影及蝕刻製程以將第二絕緣材料層153a圖案化，而形成具有開口153c、153d的第二絕緣層153。第二開口153c可以暴 露出第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a，開口153d可以暴露出部分的線路層152。
在一實施例中，在形成第二絕緣層153的第二開口153c的步驟中，第一絕緣層151的一部分(如：第一開口151c附近的區域)可能可以被些微地移除。
在一實施例中，可以藉由相同或相似於圖1F及圖1G的步驟，而可以形成具有開口150c的重佈線路結構150。
在一實施例中，在用於暴露出第一晶片連接件115a及第二晶片連接件125a的各個絕緣層開口中，後形成的絕緣層開口重疊於先形成的絕緣層開口。並且，移除部分的絕緣材料層以暴露出晶片連接件及對應的線路層的步驟是藉由同一濕蝕刻製程所形成。也就是說，在前述的濕蝕刻製程中，所欲移除的部分絕緣材料層的厚度及材質基本上相似或相同。以圖1F至圖1G為例，第二絕緣層153的第二開口153c重疊於第一絕緣層151的第一開口151c。並且，移除部分的第二絕緣材料層153a，以形成第二開口153c(即，暴露出第一晶片連接件115a及第二晶片連接件125a)及開口153d(如：即，暴露出部分的線路層152)的步驟是藉由同一濕蝕刻製程所形成。填入第一開口151c內的部分第二絕緣材料層153a1、鄰近於第一開口151c的部分第二絕緣材料層153a2(如：構成第一開口151c的邊緣的第一絕緣層151的上方的部分第二絕緣材料層153a)及/或位於線路層152上的部分第二絕緣材料層153a3的厚度及材質基本上相似或相同。如此一來，在前述 的濕蝕刻製程中，可能可以降低側向蝕刻而造成底切(undercut)或膜層剝離(film peeling)的可能。
在一實施例中，在用於暴露出晶片連接件的各個絕緣層開口中，後形成的絕緣層開口的開口口徑大於先形成的絕緣層開口的開口口徑。以圖1F至圖1G為例，第二開口153c的開口口徑大於第一開口151c的開口口徑。如此一來，在前述多次的濕蝕刻製程以形成重佈線路結構150的開口150c的過程(如：蝕刻前的對位步驟；及/或蝕刻參數的設定)中，可能可以提升製程裕度(process window)。
在一實施例中，在前述多次的濕蝕刻製程以形成重佈線路結構150的開口150c的過程中，第一晶片110的第一晶片連接件115a、位於第一晶片110的主動面110a上的部分模封體140及/或第一晶片110的保護層114可能可以降低第一晶片110的主動面110a或元件區受損的可能；且/或第二晶片120的第二晶片連接件125a、位於第二晶片120的主動面120a上的部分模封體140及/或第二晶片120的保護層124可能可以降低第二晶片120的主動面120a或元件區受損的可能。
請參照圖1H，在本實施例中，可以形成覆蓋重佈線路結構150的絕緣材料169。在一實施例中，絕緣材料169包括有機材料。舉例而言，絕緣材料169可以包括有機的光敏介電材(photoimageable dielectric material；PID material)。在一實施例中，絕緣材料169可以藉由塗佈法或其他適宜的製程形成，但本 發明不限於此。
在本實施例中，絕緣材料169至少填入重佈線路結構150的開口150c內，且覆蓋及第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a。也就是說，填入於開口150c內的絕緣材料169的外型基本上對應於開口150c的形貌。在一實施例中，絕緣材料169可以更覆蓋重佈線路結構150的最頂端線路層157(即，重佈線路結構150中最遠離第一晶片110或第二晶片120的線路層)或最頂端絕緣層156(即，重佈線路結構150中最遠離第一晶片110或第二晶片120的絕緣層)。
請參照圖11，形成絕緣體160。絕緣體160至少位於重佈線路結構150的開口150c內，且絕緣體160暴露出第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a。
在本實施例中，可以藉由光聚合(photopolymerization)及/或烘烤(baking)的方式將部分的絕緣材料169(標示於圖1H)固化。然後，可以藉由濕清洗(wet clean)或其他適宜的方式移除未被固化的其餘絕緣材料169。如此一來，可以形成具有多個通孔160c的絕緣體160。絕緣體160的通孔160c可以暴露出第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a。
在一實施例中，絕緣體160的通孔160c可以不暴露出模封體140，但本發明不限於此。
在本實施例中，絕緣體160可以更位於重佈線路結構150 的一表面(如：最頂端絕緣層156的外表面及最頂端線路層157的外表面所構成的第二連接面150b)上，且絕緣體160可以更暴露重佈線路結構150的最頂端線路層157的一部分。
請參照圖1J，形成多個導電連接件170。導電連接件170可以形成於絕緣體160的通孔160c(標示於圖11)內。也就是說，導電連接件170可以貫穿絕緣體160，且可以電性連接於對應的第一晶片連接件115a或對應的第二晶片連接件125a。
在本實施例中，導電連接件170可以藉由微影製程、濺鍍製程、電鍍製程及/或蝕刻製程形成，但本發明不限於此。舉例而言，導電連接件170可以包括鍍覆核心層(plating core layer)170c(標示於圖1M)及環繞鍍覆核心層170c的種子層170s(標示於圖1M)，但本發明不限於此。
請參照圖1K，在形成導電連接件170之後，可以移除載板91(標示於圖1J)。在本實施例中，於移除載板91後，可以暴露出第一晶片110、第二晶片120或模封體140。
請參照圖1K，在形成導電連接件170之後，可以將第三晶片130配置於絕緣體160上。第三晶片130可以藉由導電連接件170電性連接第一晶片110及第二晶片120。舉例而言，第三晶片130可以藉由對應的導電端子182以及對應的導電連接件170電性連接第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a。
在一實施例中，導電端子182可以是導電柱(conductive pillar)、焊球(solder ball)、導電凸塊(conductive bump)或具有其他形式或形狀的導電端子。導電端子182可以經由電鍍、沉積、置球(ball placement)、迴焊(reflow)及/或其他適宜的製程來形成。
在本實施例中，第三晶片130可以包括基材131、多個連接墊132以及多個第三晶片連接件135。基材111的一側具有元件區(未繪示)，而元件區所位於的表面可以被稱為主動面130a。
在本實施例中，第三晶片130可以相同或相似於第一晶片110。舉例而言，基材131可以相同或相似於基材111，連接墊132可以相同或相似於連接墊112，絕緣層133可以相同或相似於絕緣層113，保護層134可以相同或相似於保護層114，第三晶片連接件135可以相同或相似於第一晶片連接件115，故於此不加以贅述。舉例而言，第三晶片連接件135可以包括種子層(seed layer)135s(標示於圖1M)以及位於種子層135s上的鍍覆層(plating layer)135c(標示於圖1M)，但本發明不限於此。在一實施例中，第三晶片連接件135可以更包括導電連接層135d(標示於圖1M)，但本發明不限於此。
在本實施例中，第三晶片130與絕緣體160之間可以形成底膠(underfill)191，但本發明不限於此。
請參照圖1K，在形成導電連接件170之後，可以形成多個導電端子181於重佈線路結構150上。導電端子181可以藉由重佈線路結構150電性連接第一晶片110或第二晶片120。舉例而 言，導電端子181可以藉由重佈線路結構150中對應的線路電性連接第一晶片110的第一晶片連接件115b及第二晶片120的第二晶片連接件125b。
導電端子181可以是導電柱(conductive pillar)、焊球(solder ball)、導電凸塊(conductive bump)或具有其他形式或形狀的導電端子。導電端子181可以經由電鍍、沉積、置球(ball placement)、迴焊(reflow)及/或其他適宜的製程來形成。
請參照圖1K至圖1L，在本實施例中，可以經由單一化製程(singulation process)，以構成多個封裝結構100。單一化製程例如可以包括切割製程(dicing process/cutting process)，以切穿模封體140及/或重佈線路結構150。
值得注意的是，在進行單一化製程之後，相似的元件符號將用於單一化後的元件。舉例而言，重佈線路結構150(如圖1K所示)於單一化後可以為重佈線路結構150(如圖1L所示)，絕緣體160(如圖1K所示)於單一化後可以為絕緣體160(如圖1L所示)，多個導電連接件170(如圖1K所示)於單一化後可以為多個導電連接件170(如圖1L所示)，第一晶片110(如圖1K所示)於單一化後可以為第一晶片110(如圖1L所示)，第二晶片120(如圖1K所示)於單一化後可以為第二晶片120(如圖1L所示)，模封體140(如圖1K所示)於單一化後可以為模封體140(如圖1L所示)，第三晶片130(如圖1K所示)於單一化後可以為第三晶片130(如圖1L所示)，多個導電端子181(如圖1K所 示)於單一化後可以為多個導電端子181(如圖1L所示)，諸如此類。其他單一化後的元件將依循上述相同的元件符號規則，於此不加以贅述或特別繪示。
值得注意的是，本發明並未限定移除載板91(若有)、配置第三晶片130、配置多個導電端子181以及單一化製程(若有)的順序。
經過上述步驟後即可大致上完成本實施例的封裝結構100的製作。
請參照圖11至圖1L，封裝結構100包括重佈線路結構150、絕緣體160、多個導電連接件170、第一晶片110、第二晶片120、模封體140、第三晶片130以及多個導電端子181。重佈線路結構150具有第一連接面150a以及相對於第一連接面150a的第二連接面150b。絕緣體160嵌入且貫穿重佈線路結構150。導電連接件170貫穿絕緣體160。第一晶片110及第二晶片120位於重佈線路結構150的第一連接面150a上。模封體140位於重佈線路結構150的第一連接面150a上且至少側向覆蓋第一晶片110及第二晶片120。第三晶片130位於重佈線路結構150的第二連接面150b上。第三晶片130藉由對應的導電連接件170電性連接第一晶片110及第二晶片120。導電端子181位於重佈線路結構150的第二連接面150b上。導電端子181藉由重佈線路結構150中對應的線路電性連接第一晶片110或第二晶片120。
在本實施例中，第三晶片130與第一晶片110之間或第 三晶片130與第二晶片120之間可以不藉由重佈線路結構150電性連接。
在本實施例中，重佈線路結構150包括線路層(如：線路層152或線路層157；標示於圖1H)。重佈線路結構150的線路層不位於第三晶片130與第一晶片110之間或第三晶片130與第二晶片120之間。舉例而言，屬於重佈線路結構150中的任何線路層可以不位於第三晶片130與第一晶片110之間及/或第三晶片130與第二晶片120之間。在一實施例中，重佈線路結構150的線路層可以是經由相同或相似於圖1E至圖1G中所繪示的步驟所形成。
在一實施例中，第三晶片130與第一晶片110之間的訊號傳輸距離基本上相同於第三晶片130與第一晶片110之間的物理距離。舉例而言，第三晶片130與第一晶片110之間的訊號可以藉由對應的導電件(如：對應的導電連接件170及對應的導電端子182)傳輸，且第三晶片130的第三晶片連接件135與第一晶片110的第一晶片連接件115a之間的距離基本上等於前述的導電件的高度或厚度(如：對應的導電連接件170的高度及對應的導電端子182的高度)。如此一來，可能可以提升第三晶片130與第一晶片110之間訊號傳輸的品質及效率。
在一實施例中，第三晶片130與第二晶片120之間的訊號傳輸距離基本上相同於第三晶片130與第二晶片120之間的物理距離。舉例而言，第三晶片130與第二晶片120之間的訊號可 以藉由對應的導電件(如：對應的導電連接件170及對應的導電端子182)傳輸，且第三晶片130的第三晶片連接件135與第二晶片120的第二晶片連接件125a之間的距離基本上等於前述的導電件的高度或厚度(如：對應的導電連接件170的高度及對應的導電端子182的高度)。如此一來，可能可以提升第三晶片130與第二晶片120之間訊號傳輸的品質及效率。
一般而言，在多個導電結構所構成的導體中，沿著導體傳輸的信號會因為多個導電結構之間的不連續(如：可能因材質或晶格的不同而具有介面或阻抗不匹配)而會有對應的反射訊號。這種現象可以被稱為回波損耗(return loss)。因此，相較於以一般重佈線路的方式進行晶片間的訊號傳輸，藉由導電連接件170可能可以提升第三晶片130與第一晶片110及/或第三晶片130與第二晶片120之間訊號傳輸的品質及效率。
在一實施例中，第一晶片110與第二晶片120之間可以是同質的(homogeneous)晶片，且第三晶片130與第一晶片110/第二晶片120之間可以是異質的(heterogeneous)晶片。舉例而言，第一晶片110及/或第二晶片120例如是相同或相似的高頻寬記憶體(High Bandwidth Memory；HBM)，且第三晶片130應用處理器(application processor，AP)或其他類似的處理器晶片，但本發明不限於此。
在本實施例中，部分的絕緣體160更可以位於重佈線路結構150的第二連接面150b上。
在本實施例中，絕緣體160可以包括第一絕緣部分161以及第二絕緣部分162。第一絕緣部分161與第三晶片130之間的距離大於第二絕緣部分162與第三晶片130之間的距離。
在本實施例中，第一絕緣部分161可以完全重疊於第二絕緣部分162。舉例而言，如圖1N所示，於一平行於第一連接面150a或第二連接面150b的虛擬面S1上，第一絕緣部分161的邊緣於前述虛擬面S1上的投影範圍161R可以完全位於第二絕緣部分162的邊緣於前述虛擬面S1上的投影範圍162R內。也就是說，第一絕緣部分161的尺寸(即：對應的投影面積)可以小於第二絕緣部分162的尺寸(即：對應的投影面積)。
在本實施例中，導電連接件170的側壁170e基本上可以為平面。舉例而言，如圖1M或圖1O所示，導電連接件170可以為柱狀(如：圓柱)或錐台狀(cone)(如：圓台(truncated cone))，於一垂直於第一連接面150a或第二連接面150b的截面(如：圖1M所繪示的平面)上，導電連接件170的側壁170e基本上可以呈一直線。
在一實施例中，導電連接件170可以被平行於第一連接面150a或第二連接面150b的任意截面S3分為第一導電連接部分171及第二導電連接部分172，其中第一導電連接部分171較第二導電連接部分172接近重佈線路結構150。第一導電連接部分171於前述截面S3上的接觸面積基本上相同於第二導電連接部分172於前述截面S3上的接觸面積。並且，於一平行於第一連接面150a 或第二連接面150b的虛擬面S2上，第一導電連接部分171的邊緣於前述虛擬面上S3的投影範圍171R可以完全位於第二導電連接部分172於前述虛擬面S3上的投影範圍172R內。
在本實施例中，部分的模封體140更可以位於絕緣體160與第一晶片110之間以及絕緣體160與第二晶片120之間。
在本實施例中，第一晶片110可以包括第一晶片連接件115，且第二晶片120可以包括第二晶片連接件125。模封體140可以側向覆蓋第一晶片連接件115及第二晶片連接件125。第一晶片連接件115的頂面115d、第二晶片連接件125的頂面125d、模封體140的模封頂面140d及重佈線路結構150的第一連接面150a基本上共面。
圖2A是依照本發明的第二實施例的一種封裝結構的部分製造方法的部分剖視示意圖。圖2B是依照本發明的第二實施例的一種封裝結構的剖視示意圖。第二實施例的封裝結構200的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方式，並省略描述。舉例而言，圖2A可以是繪示接續圖1J的步驟的封裝結構的製造方法的剖面示意圖。
接續圖1J，請參照圖2A，在本實施例中，在形成導電連接件170之後，可以於絕緣體160上形成圖案化導電層292。圖案化導電層292可以電性連接於重佈線路結構150中最頂端線路層157或導電連接件170。
在一實施例中，圖案化導電層292可以包括圖案化導電層292a。圖案化導電層292a可以嵌入絕緣體160且電性連接於最頂端線路層157。在一實施例中，電性連接於最頂端線路層157的圖案化導電層292a可以被稱為凸塊底金屬(Under Bump Metallurgy；UBM)。
在一實施例中，圖案化導電層292可以包括圖案化導電層292b。圖案化導電層292b可以電性連接於導電連接件170。
在本實施例中，在形成圖案化導電層292之後，可以藉由相同或相似圖1K中所敘述的步驟，以構成如圖2B所示的封裝結構200。
請參照圖2B，封裝結構200包括重佈線路結構150、絕緣體160、多個導電連接件170、第一晶片110、第二晶片120、模封體140、第三晶片130、多個導電端子181以及圖案化導電層292。
在一實施例中，圖案化導電層292a可以位於重佈線路結構150與對應的導電端子181之間。重佈線路結構150中線路可以藉由對應的圖案化導電層292a電性連接於對應的導電端子181。
在一實施例中，圖案化導電層292b可以位於第三晶片130與第一晶片110之間，且第三晶片130與第一晶片110之間的訊號傳輸距離基本上相同於第三晶片130與第一晶片110之間的物理距離。舉例而言，第三晶片130與第一晶片110之間的訊號可以藉由對應的導電件(如：對應的導電連接件170、對應的圖案 化導電層292b及對應的導電端子182)傳輸，且第三晶片130的第三晶片連接件135與第一晶片110的第一晶片連接件115a之間的距離基本上等於前述的導電件的高度或厚度(如：對應的導電連接件170的高度、對應的圖案化導電層292b的厚度及對應的導電端子182的高度)。如此一來，可能可以提升第三晶片130與第一晶片110之間訊號傳輸的品質及效率。
在一實施例中，圖案化導電層292b可以位於第三晶片130與第二晶片120之間，且第三晶片130與第二晶片120之間的訊號傳輸距離基本上相同於第三晶片130與第二晶片120之間的物理距離。舉例而言，第三晶片130與第二晶片120之間的訊號可以藉由對應的導電件(如：對應的導電連接件170、對應的圖案化導電層292b及對應的導電端子182)傳輸，且第三晶片130的第三晶片連接件135與第二晶片120的第二晶片連接件125a之間的距離基本上等於前述的導電件的高度或厚度(如：對應的導電連接件170的高度、對應的圖案化導電層292b的厚度及對應的導電端子182的高度)。如此一來，可能可以提升第三晶片130與第二晶片120之間訊號傳輸的品質及效率。
圖3A至3B是依照本發明的第三實施例的一種封裝結構的部分製造方法的部分剖視示意圖。圖3C是依照本發明的第三實施例的一種封裝結構的剖視示意圖。第三實施例的封裝結構300的製造方法與第一實施例的封裝結構100的製造方法相似，其類似的構件以相同的標號表示，且具有類似的功能、材質或形成方 式，並省略描述。舉例而言，圖3A可以是繪示接續圖1C的步驟的封裝結構的製造方法的剖面示意圖。
接續圖1C，請參照圖3A，在本實施例中，可以於模封體140上形成圖案化的第一絕緣材料層351a。然後，在形成第一絕緣材料層351a之後，可以於第一絕緣材料層351a上形成線路層152。然後，在形成線路層152之後，可以於第一絕緣材料層351a上形成圖案化的第二絕緣材料層353a。第二絕緣材料層353a可以覆蓋線路層152。然後，可以藉由類似的方式，以形成一個或多個線路層，或更形成一個或多個圖案化的絕緣材料層。
請參照圖3B，在形成多個圖案化的絕緣材料層(如：第一絕緣材料層351a及第二絕緣材料層353a)之後，可以移除位於第一晶片110及第二晶片120上的各個絕緣材料層的一部分，以形成具有開口350c的重佈線路結構350。重佈線路結構350的開口350c暴露出第一晶片110的第一晶片連接件115a及第二晶片120的第二晶片連接件125a。
在一實施例中，可以藉由雷射鑽孔(laser drilling)、反應離子蝕刻(reactive-ion etching；RIE)或其他適宜的乾蝕刻製程，以一次性的方式移除各個絕緣材料層的一部分。也就是說，移除部分的第一絕緣材料層351a(標示於圖3A)的步驟及部分的所述第二絕緣材料層353a(標示於圖3A)的步驟可以為同一製程。
在本實施例中，重佈線路結構350的開口350c的側壁基本上可以垂直於模封體140的模封頂面140d。
在本實施例中，在形成重佈線路結構350的開口350c之後，可以藉由相同或相似圖1H及其之後中所敘述的步驟，以構成如圖3C所示的封裝結構300。
請參照圖3C，封裝結構300包括重佈線路結構350、絕緣體360、多個導電連接件170、第一晶片110、第二晶片120、模封體140、第三晶片130以及多個導電端子181、182。絕緣體360嵌入且貫穿重佈線路結構350。導電連接件170貫穿絕緣體360。
在本實施例中，部分的絕緣體360更可以位於重佈線路結構350的第二連接面350b上。
在本實施例中，位於重佈線路結構350的開口350c(標示於圖3B)內的部分絕緣體360基本上可以是柱狀。舉例而言，絕緣體360可以被平行於第一連接面350a或第二連接面350b的任意截面分為兩部分。並且，於一平行於第一連接面350a或第二連接面350b的虛擬面上，前述兩部分的邊緣於前述虛擬面上的投影範圍可以完全重疊。也就是說，前述兩部分的尺寸(即：對應的投影面積)基本上可以相同。
在本實施例中，部分的模封體140更可以位於絕緣體360與第一晶片110之間以及絕緣體360與第二晶片120之間。
綜上所述，本發明的封裝結構至少藉由貫穿絕緣體的導電連接件，可以使多個晶片(如：第三晶片與第一晶片；或第三晶片與第二晶片)之間具有較佳的訊號傳輸的品質或效率。
100:封裝結構
110:第一晶片
115、115a、115b:第一晶片連接件
115d:頂面
120:第二晶片
125、125a、125b:第二晶片連接件
125d:頂面
130:第三晶片
130a:主動面
140:模封體
140d:模封頂面
150:重佈線路結構
150a:第一連接面
150b:第二連接面
160:絕緣體
170:導電連接件
181、182:導電端子
191:底膠
R2:區域

Claims (9)

  1. 一種封裝結構，包括：重佈線路結構，具有第一連接面以及相對於所述第一連接面的第二連接面；絕緣體，嵌入且貫穿所述重佈線路結構；多個導電連接件，貫穿所述絕緣體；第一晶片，位於所述重佈線路結構的所述第一連接面上；第二晶片，位於所述重佈線路結構的所述第一連接面上；模封體，位於所述重佈線路結構的所述第一連接面上且至少側向覆蓋所述第一晶片及所述第二晶片；第三晶片，位於所述重佈線路結構的所述第二連接面上，且所述第三晶片藉由所述多個導電連接件電性連接所述第一晶片及所述第二晶片；以及多個導電端子，位於所述重佈線路結構的所述第二連接面上，且所述多個導電端子藉由所述重佈線路結構電性連接所述第一晶片或所述第二晶片，其中：所述第一晶片包括第一晶片連接件；所述第二晶片包括第二晶片連接件；所述模封體側向覆蓋所述第一晶片連接件及所述第二晶片連接件；且所述第一晶片連接件的頂面、所述第二晶片連接件的頂面、所述模封體的模封頂面及所述重佈線路結構的所述第一連接 面基本上共面。
  2. 如請求項1所述的封裝結構，其中所述第三晶片與所述第一晶片之間或所述第三晶片與所述第二晶片之間不藉由所述重佈線路結構電性連接。
  3. 如請求項1所述的封裝結構，其中所述重佈線路結構包括線路層，且所述線路層不位於所述第三晶片與所述第一晶片之間或所述第三晶片與所述第二晶片之間。
  4. 如請求項1所述的封裝結構，其中部分的所述絕緣體更位於所述重佈線路結構的所述第二連接面上。
  5. 如請求項1所述的封裝結構，其中：所述絕緣體包括第一絕緣部分以及第二絕緣部分；所述第一絕緣部分與所述第三晶片之間的距離大於所述第二絕緣部分與所述第三晶片之間的距離；且所述第一絕緣部分的尺寸小於或等於所述第二絕緣部分的尺寸。
  6. 如請求項5所述的封裝結構，其中所述第一絕緣部分完全重疊於所述第二絕緣部分。
  7. 如請求項1所述的封裝結構，其中所述多個導電連接件的側壁基本上為平面。
  8. 如請求項1所述的封裝結構，其中部分的所述模封體更位於所述絕緣體與所述第一晶片之間以及所述絕緣體與所述第二晶片之間。
  9. 一種封裝結構的製造方法，包括：提供第一晶片，包括第一晶片連接件；提供第二晶片，包括第二晶片連接件；形成覆蓋所述第一晶片及所述第二晶片的模封體，且所述模封體側向覆蓋所述第一晶片連接件及所述第二晶片連接件；形成電性連接於所述第一晶片及所述第二晶片的重佈線路結構，且所述重佈線路結構具有暴露出部分的所述第一晶片及部分的所述第二晶片的開口，其中所述重佈線路結構具有面向所述第一晶片、所述第二晶片及所述模封體的第一連接面，且所述第一晶片連接件的頂面、所述第二晶片連接件的頂面、所述模封體的模封頂面及所述重佈線路結構的所述第一連接面基本上共面；形成絕緣體，至少位於所述重佈線路結構的所述開口內且暴露出部分的所述第一晶片及部分的所述第二晶片；形成多個導電連接件，貫穿所述絕緣體；配置第三晶片於所述絕緣體上，且所述第三晶片藉由所述多個導電連接件電性連接所述第一晶片及所述第二晶片；以及形成多個導電端子於所述重佈線路結構上，且所述多個導電端子藉由所述重佈線路結構電性連接所述第一晶片或所述第二晶片。
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