TWI736780B - 晶片封裝及其形成方法 - Google Patents

晶片封裝及其形成方法 Download PDF

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TWI736780B
TWI736780B TW107122077A TW107122077A TWI736780B TW I736780 B TWI736780 B TW I736780B TW 107122077 A TW107122077 A TW 107122077A TW 107122077 A TW107122077 A TW 107122077A TW I736780 B TWI736780 B TW I736780B
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Taiwan
Prior art keywords
interposer substrate
semiconductor die
forming
protective layer
substrate
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TW107122077A
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TW201919134A (zh
Inventor
鄭心圃
蔡柏豪
莊博堯
翁得期
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台灣積體電路製造股份有限公司
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Priority claimed from US15/874,374 external-priority patent/US11322449B2/en
Application filed by 台灣積體電路製造股份有限公司 filed Critical 台灣積體電路製造股份有限公司
Publication of TW201919134A publication Critical patent/TW201919134A/zh
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Abstract

提供晶片封裝之結構及其形成方法。此方法包含：設置半導體晶粒於載體基板之上。此方法也包含設置中介層基板於此載體基板之上。此中介層基板具有凹槽，此凹槽穿過該中介層基板之相反面。此中介層基板具有圍繞半導體晶粒之內部側壁，並且此半導體晶粒等高於或高於此中介層基板。此方法更包含在中介層基板之凹槽中形成保護層，以圍繞半導體晶粒。另外，此方法包含移除載體基板以及堆疊封裝結構於該中介層基板之上。

Description

晶片封裝及其形成方法
本揭露係有關於一種半導體裝置的結構及其形成方法，且特別有關於一種散出型(Fan-Out)晶片封裝之結構及其形成方法。
半導體裝置用於各種不同的電子應用，例如，個人電腦、手機、數位相機和其他電子設備。半導體裝置的製造通常藉由在半導體基板上依序沉積絕緣或介電層、導電層和半導體層的材料，並且使用微影和蝕刻製程將各種材料層圖案化，以形成電路組件以及元件於半導體基底上。
半導體工業藉由持續微縮最小部件的尺寸，使得更多組件整合至給定的區域中，以持續改善各種電子組件(例如電晶體、二極體、電阻器、電容器等)的積體密度。在一些應用中，這些較小的電子組件也使用了應用較小面積或較低高度的較小的封裝。
新的封裝技術，例如：堆疊式封裝(package on package，PoP)已經開始發展，在其中具有裝置晶片的頂部封裝接合至具有另一裝置晶片的底部封裝。藉由採用這些新的封裝技術，可將具有不同或相似功能的各種封裝整合在一起。這 些較新穎的半導體裝置之封裝技術態樣面臨了製程的挑戰。
根據一些實施例提供一種晶片封裝之形成方法。此方法包含：設置半導體晶粒於載體基板之上。此方法也包含設置中介層基板於此載體基板之上。此中介層基板具有凹槽，此凹槽穿過該中介層基板之相反面。此中介層基板具有圍繞半導體晶粒之內部側壁，並且此半導體晶粒等高於或高於此中介層基板。此方法更包含在中介層基板之凹槽中形成保護層，以圍繞半導體晶粒。另外，此方法包含移除載體基板以及堆疊封裝結構於該中介層基板之上。
根據一些實施例提供一種晶片封裝之形成方法。此方法包含：形成第一重佈結構於載體基板之上，並且接合一半導體晶粒與此第一重佈結構。此方法也包含接合中介層基板與此第一重佈結構。此中介層基板具有圍繞此半導體晶粒之環型結構，並且此半導體晶粒等高於或高於此中介層基板。此方法更包含形成保護層以圍繞此半導體晶粒。此保護層之一部分在此中介層基板與此半導體晶粒之間。另外，此方法包含移除此載體基板，以及接合封裝結構於此中介層基板之上。此半導體晶粒在此封裝結構與此第一重佈結構之間。
根據一些實施例提供晶片封裝。此晶片封裝包含：第一重佈結構，以及接合於此第一重佈結構之上的半導體裝置。此晶片封裝也包含接合於此第一重佈結構之上的中介層基板。此中介層基板具有圍繞此半導體裝置之內部側壁，並且此半導體裝置等高於或高於此中介層基板。此晶片封裝更包含 圍繞此半導體裝置的保護層。另外，此晶片封裝包含第二重佈結構於此保護層之上。此第二重佈結構之第一導電部件電性連接至此中介層基板之第二導電部件。
100:載體基板
102、136、504:互連結構
104、506:絕緣層
106、116、116’、137、508:導電部件
108、108A、108B、134:半導體晶粒、元件
110、122、140、206、540:接合結構
112:中介層基板
114:基座部分
118、120:鈍化層
124:內部側壁
126:凹槽
128、128’、142、208、542:底膠層
130:保護層
131、132、138、502、510:導電元件
133:封裝結構
202:黏合層
204:基板
302:開口
702:阻隔元件
H1、H2:高度
W1、W2:距離
藉由以下的詳述配合所附圖式，可以更加理解本揭露實施例的觀點。應注意的是，依據在業界的標準慣例，各種部件並未按照比例繪製且僅用以說明例示。事實上，為了討論的明確易懂，各種部件的尺寸可任意增加或減少。
第1A至1K圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。
第2A至2D圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。
第3A至3E圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。
第4A至4B圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。
第5A至5F圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。
第6A至6B圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。
第7A至7I圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。
第8圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。
第9圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。
第10圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。
第11圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。
第12圖係根據一些實施例繪示出晶片封裝之剖面圖。
第13圖係根據一些實施例繪示出晶片封裝之剖面圖。
以下提供許多不同的實施例或示範，用於實行本揭露的不同部件。以下描述了組件和配置的具體範例，以簡化本揭露之實施例。當然，這些實施例僅用以例示，並非意圖限制本揭露之範圍。舉例而言，在敘述中第一部件形成於第二部件之上，可能包含形成第一和第二部件直接接觸的實施例，也可能包含額外的部件形成於第一和第二部件之間，使得第一和第二部件不會直接接觸的實施例。另外，本揭露之實施例可能在許多範例中重複參考符號及/或字母。這些重複的目的是為了簡化和清楚，除非內文中特別說明，其本身並非代表各種實施例及/或所討論的配置之間有特定的關係。
此外，在以下敘述中可使用空間上相對用語，例如「在......之下」、「在......下方」、「較低的」、「在......上方」、「較高的」和其他類似的用語，以簡化圖式中一個(些)元件或部件與另一個(些)元件或部件之間的關係之陳述。此空間相對用語除了包含圖式所繪示之方位，還包含裝置在使用或 操作中的不同方位。裝置亦可轉向至其他方位(旋轉90度或在其他方位)，且在此使用的空間相對描述亦依轉向後的方位相應地解讀。
討論了本揭露之一些實施例。在這些實施例中，可在所討論的階段之前、過程中、及/或之後提供額外的步驟。可為了不同的實施例而取代或刪除所討論的一些階段。可增加額外的部件至半導體裝置結構中。可為了不同的實施例而取代或刪除下文所討論的一些部件。雖然所討論的一些實施例以一特定的順序來執行步驟，但是這些步驟可以其他邏輯性的順序來執行。
也可包含其他部件或製程。舉例來說，可包含檢測結構(testing structure)以支援三維封裝(3D packaging)或三維積體電路(3DIC)裝置之驗證測試(verification testing)。此檢測結構可包含，例如：形成於重佈層中或基板之上的測試墊(test pad)，其可允許使用探針(probe)及/或探針卡(probe card)、以及類似的裝置來測試三維封裝或三維積體電路裝置。可執行此驗證測試於中間結構及最終結構。此外，此處所揭露之結構與方法可與測試方法結合使用，其可作為晶片良品的中間驗證以增加產出並減少成本。
第1A至1K圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。如第1A圖所示，提供或接收載體基板100。載體基板100可在後續的形成製程中作為暫時的支撐基板。載體基板100可包含絕緣基板、半導體基板、導電基板、一或多個其他適合的基板、或前述之組合。在一些實施例 中，載體基板100係為玻璃基板，例如：玻璃晶圓。在一些其他實施例中，載體基板100係為半導體基板，例如：矽晶圓。在一些其他實施例中，載體基板100係為支撐框(support frame)，例如金屬框(metal frame)。
如第1A圖所示，根據一些實施例，形成互連結構102於載體基板100之上。可使用互連結構102作為用來佈線(routing)的重佈結構(redistribution structure)。如第1A圖所示，互連結構102包含了多個絕緣層104及多個導電部件106。在一些實施例中，一些導電部件106在絕緣層104之頂部之頂面曝露出來或者從絕緣層104之頂部之頂面突出。曝露或突出的導電部件106可作為接合墊(bonding pad)，而之後導電凸塊(bump)(例如：含錫焊料凸塊(tin-containing solder bump))及/或導電柱(例如：銅柱)可形成於此處。
絕緣層104可由或包含一或多種高分子材料所形成。高分子材料可包含聚苯噁唑(polybenzoxazole，PBO)、聚醯亞胺(polyimide，PI)、一或多種其他適合的高分子材料、或前述之組合。在一些實施例中，高分子材料係為感光性(photosensitive)。在一些實施例中，一些或全部的絕緣層104係由或包含除了高分子材料以外的介電材料所形成。介電材料可包含氧化矽、碳化矽、氮化矽、氮氧化矽、一或多種其他適合的材料、或前述之組合。導電部件106可包含提供水平方向電性連接的導電線(conductive line)以及提供垂直方向電性連接的導電通孔(conductive via)。導電部件106可由或包含銅、鋁、金、鈷、鈦、石墨烯、一或多種其他適合的導電材料、或 前述之組合所形成。
互連結構102之形成可包含多重沉積或塗佈製程、多重圖案化製程、及/或多重平坦化製程。可使用沉積或塗佈製程來形成絕緣層及/或導電層。沉積或塗佈製程可包含旋轉塗佈(spin-on)製程、電鍍(electroplating)製程、無電鍍(electroless plating)製程、化學氣相沉積(Chemical Vapor Deposition，CVD)製程、物理氣相沉積(Physical Vapor Deposition，PVD)製程、一或多種其他可應用的製程、或前述之組合。可使用圖案化製程來圖案化所形成的絕緣層及/或所形成的導電層。圖案化製程可包含光微影(photolithography)製程、能量束鑽孔(energy beam drilling)製程、蝕刻製程、機械鑽孔製程、一或多種其他可應用的製程、或前述之組合。可使用平坦化製程來提供平坦的頂面給所形成的絕緣層及/或所形成的導電層。平坦化製程可包含機械研磨(grinding)製程、化學機械研磨(Chemical Mechanical Polish，CMP)、一或多種其他可應用的製程、或前述之組合。
然而，可對本揭露之實施例進行許多變化及/或改良。在一些其他實施例中，未形成互連結構102。
如第1B圖所示，根據一些實施例，設置半導體裝置(例如：半導體晶粒108)於載體基板100之上。半導體裝置可包含一個晶片、多個晶片、或系統積體電路(system-on-integrated-circuit，SoIC)晶片裝置。在一些實施例中，設置多個半導體晶粒108於載體基板100之上。半導體晶粒108可具有系統單晶片(system-on-chip，SoC)晶片。在一些其他 實施例中，元件108係為系統積體電路(system-on-integrated-circuit，SoIC)裝置，其包含二或多個具有整合功能的晶片。在這些情況中，使用參考符號「108」來表示半導體裝置。在一些實施例中，設置半導體晶粒108於形成於載體基板100之上的互連結構102之上。在一些實施例中，半導體晶粒108藉由接合結構110接合至互連結構102的一些導電部件106。
在一些實施例中，接合結構110係為導電性。半導體晶粒108中的裝置元件與互連結構102的一些導電部件106之間的電性連接，可藉由接合結構110來形成。在一些實施例中，接合結構110係為或包含焊料凸塊，例如：含錫焊料凸塊。含錫焊料凸塊可更包含銅、銀、金、鋁、鉛、一或多種其他適合的材料、或前述之組合。在一些實施例中，含錫焊料凸塊不具有鉛。接合結構110之形成可包含一或多道回焊(reflow)製程及/或一或多道電鍍製程。
在一些實施例中，接合結構110包含金屬柱，例如：銅柱。接合結構110之形成可包含電鍍(electroplating)製程或無電鍍(electroless plating)製程。在一些實施例中，可形成含錫焊接材料於接合結構110與互連結構102之一些導電部件106之間。
如第1C圖所示，根據一些實施例，設置中介層基板112於載體基板100之上。在一些實施例中，設置中介層基板112於形成於載體基板100之上的互連結構102之上。在一些實施例中，中介層基板112藉由接合結構122接合至互連結構102 的一些導電部件106。接合結構122之材料及形成方法可與接合結構110之材料及形成方法相同或相似。
在一些實施例中，中介層基板112包含基座部分114及多個導電部件116。基座部分114可由或包含一或多種絕緣材料、一或多種半導體材料、一或多種其他適合的材料、或前述之組合所形成。在一些實施例中，基座部分114包含具有填充物分散在其中的高分子材料(例如：環氧基樹脂(epoxy-based resin))。在一些實施例中，填充物可包含纖維，例如：玻璃纖維。在一些實施例中，基座部分114係為多層絕緣層之堆疊。
在一些實施例中，導電部件116包含導電結構，其穿過基座部分114之相反面。在一些其他實施例中，導電部件116包含多個導電通孔及導電線。在一些其他實施例中，基座部分114係由半導體材料(例如：矽)所形成。在這些情況中，形成絕緣層(未繪示)於基座部分114及導電部件116之間。
在一些實施例中，中介層基板112包含形成於基座部分114之相反面之上的鈍化層118及120。在一些實施例中，鈍化層118及120具有開口，其曝露出一些導電部件116。舉例來說，曝露的導電部件116可為導電墊(conductive pad)。在一些實施例中，接合結構122部分覆蓋鈍化層118。
第8圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。在一些實施例中，第8圖繪示出第1C圖所繪示之結構之上視圖。在一些實施例中，如第1C、8圖所示，中介層基板112係為具有凹槽126的環形結構。凹槽126穿過中 介層基板112之相反面。如第1C、8圖所示，中介層基板112具有環形且具有多個內部側壁124。內部側壁124圍繞凹槽126。內部側壁124也圍繞半導體晶粒108。
在一些實施例中，凹槽126寬於半導體晶粒108。在一些實施例中，凹槽126曝露出互連結構102之一部分。舉例來說，絕緣層104之頂面藉由凹槽126曝露出來。
如第8圖所示，半導體晶粒108具有第一邊緣(edge)，其距離對應之最靠近的內部側壁124為距離W1。半導體晶粒108具有第二邊緣，其距離所對應之最靠近的內部側壁124為距離W2。在一些實施例中，距離W1與W2大致上相同。距離W1可在約20微米(μm)至約400微米(μm)的範圍。在一些其他實施例中，距離W1可在約400微米(μm)至約1500微米(μm)的範圍。在一些其他實施例中，距離W1與W2彼此不相同。
在一些實施例中，如第8圖所示，凹槽126之上視圖具有矩形。在一些其他實施例中，凹槽126之上視圖具有除了矩形以外之其他形狀。凹槽126之上視圖的形狀可包含方形、橢圓形、圓形、或其他適合的形狀。
在一些實施例中，半導體晶粒108高於中介層基板112。半導體晶粒108之頂面設置在高於中介層基板112之頂面的高度。在一些其他實施例中，半導體晶粒108等高於中介層基板112。半導體晶粒108之頂面設置在與中介層基板112之頂面相同的高度。
可對本揭露之實施例進行許多變化及/或改良。雖然在處理半導體晶粒108之後設置中介層基板112於互連結構 102之上，但本揭露之實施例並不限定於此。在一些其他實施例中，在設置半導體晶粒108之前設置中介層基板112於互連結構102之上。舉例來說，中介層基板具有先設置的多個凹槽。然後設置半導體晶粒於互連結構之上。可挑揀及放置每一個半導體晶粒至凹槽所圍繞的互連結構之對應區之上。
如第1D圖所示，根據一些實施例，形成底膠(underfill)層128在半導體晶粒108與互連結構102之間。底膠層128圍繞且保護接合結構110。在一些實施例中，底膠層128與接合結構110直接接觸。在一些實施例中，底膠層128側向(laterally)延伸至接合結構122。在一些實施例中，底膠層128也圍繞並保護結合結構122。在一些實施例中，底膠層128直接接觸接合結構122。
在一些實施例中，底膠層128係由或包含高分子材料所形成。底膠層128可包含環氧基樹脂(epoxy-based resin)。在一些實施例中，底膠層128包含填充物分散在環氧基樹脂(epoxy-based resin)之中。在一些實施例中，底膠層128較軟於中介層基板112之基座部分114。在一些實施例中，基座部分114之填充物濃度較大於底膠層128之填充物濃度。在一些實施例中，基座部分114中每一填充物較長於底膠層128中每一填充物。舉例來說，基座部分114中的填充物係為纖維(fiber)，而底膠層128中的填充物係為顆粒(particle)。在一些實施例中，底膠層128之形成包含射出(injecting)製程、旋塗製程、灌膠(dispensing)製程、薄膜層合(film lamination)製程、塗敷製程(application process)、一或多種其他可應用的製程、或前述之 組合。在一些實施例中，在底膠層128之形成過程中使用熱固化製程(thermal curing process)。
如第1E圖所示，根據一些實施例，形成保護層130於第1D圖所示之結構之上。在一些實施例中，保護層130延伸至凹槽126中以圍繞並保護半導體晶粒108。在一些實施例中，保護層130與半導體晶粒108直接接觸。在一些實施例中，保護層130與中介層基板112直接接觸。在一些實施例中，保護層130係由或包含成型複合材料(molding compound material)所形成。成型複合材料可包含高分子材料，例如：具有填充物分散在其中的環氧基樹脂。在一些實施例中，保護層130較軟於中介層基板112之基座部分114。在一些實施例中，基座部分114之填充物濃度較大於保護層130之填充物濃度。在一些實施例中，基座部分114中每一填充物較長於保護層130中每一填充物。舉例來說，基座部分114中的填充物係為纖維(fiber)，而保護層130中的填充物係為顆粒(particle)。
在一些實施例中，應用液態成型複合材料於中介層基板112及半導體晶粒108之上。液態成型複合材料可流進凹槽126內，以封裝(encapsulate)半導體晶粒108。之後使用熱製程以固化此液態成型複合材料並且將其轉換為保護層130。
如第1F圖所示，根據一些實施例，薄化保護層130以曝露出導電部件116。在一些實施例中，在薄化保護層130之後也會曝露出鈍化層120。可使用機械研磨製程來薄化保護層130。在一些實施例中，使用曝露的成型製程(molding process)或灌膠製程(dispensing process)來形成保護層130。在曝露的成 型製程中，在射出成型複合材料以形成保護層130之過程中藉由模具(mold)來保護導電部件116。保護層130不會覆蓋導電部件116。在這些情況中，因為導電部件116已經曝露出，可不執行薄化製程。
然後，如第1F圖所示，根據一些實施例，形成導電元件131於中介層基板112之導電部件116之上。在一些實施例中，導電元件131係為焊料凸塊。在一些實施例中，導電元件131係為或包含含錫焊料凸塊。含錫焊料凸塊可更包含銅、銀、金、鋁、鉛、一或多種其他適合的材料、或前述之組合。在一些實施例中，含錫焊料凸塊不具有鉛。在一些實施例中，導電元件131可包含一或多道回焊(reflow)製程及/或一或多道電鍍製程。
可對本揭露之實施例進行許多變化及/或改良。在一些其他實施例中，如第1E圖所示之保護層130並未薄化而曝露導電部件116。在一些實施例中，之後在保護層130中形成開口以曝露導電部件116。然後，形成導電元件131於曝露的導電部件116之上。導電元件131可完全在形成於保護層130中的開口中。在這些情況中，導電元件131之頂面低於保護層130之頂面。在一些其他實施例中，每一導電元件131具有大於形成於保護層130中的開口深度的高度。在這些情況中，導電元件131從保護層130之頂面突出。
可對本揭露之實施例進行許多變化及/或改良。在一些其他實施例中，在設置中介層基板112於互連結構102之上之前形成導電元件131。
如第1G圖所示，根據一些實施例，由上朝下倒裝第1F圖中所示的結構，然後移除載體基板100。在一些實施例中，在移除載體基板100之前，由上朝下倒裝第1F圖中所示的結構至第二載體基板(未繪示)之上。第二載體基板可為承載帶框(carrier tape frame)。在一些實施例中，在移除載體基板100之後曝露出中介層基板102之一些導電部件106。在一些實施例中，使用光照射(light irradiation)製程、研磨製程、熱製程、一或多種其他可應用的製程、或前述之組合來移除載體基板100。舉例來說，在經過以適合的光線光照後，分離在載體基板100與互連結構102之間的黏合層(未繪示)。因此，移除了載體基板100。
如第1H圖所示，根據一些實施例，形成導電元件132於互連結構102之曝露的導電部件106之上。在一些實施例中，導電元件132係為焊料凸塊。導電元件132之材料及形成方法可與導電元件131或接合結構122之材料及形成方法相同或相似。
如第1I圖所示，根據一些實施例，由上朝下倒裝第1H圖所示之結構以接合至封裝結構133。在一些實施例中，在接合至封裝結構133之前，切開第1I圖所示之結構以形成多個獨立的封裝結構。
封裝結構133可包含元件134、互連結構136、及導電元件138。在一些實施例中，元件134係為半導體晶粒。半導體晶粒可包含多個動態隨機存取記憶體(dynamic random access memory，DRAM)裝置、快閃記憶體(flash memory)裝置、 固態隨機存取記憶體(static random access memory，SRAM)裝置、被動裝置、無線電頻率模組(radio frequency module)裝置、其他適合的裝置、或前述之組合，在一些實施例中，元件134包含半導體晶粒及封裝半導體晶粒的封裝層。半導體晶粒可包含多個動態隨機存取記憶體(DRAM)裝置、快閃記憶體(flash memory)裝置、固態隨機存取記憶體(SRAM)裝置、被動裝置、無線電頻率模組(radio frequency module)裝置、其他適合的裝置、或前述之組合。
互連結構136之結構、材料、及形成方法可與互連結構102的之結構、材料、及形成方法相同或相似。舉例來說，互連結構136包含了多個導電線及/或導電通孔。導電元件138之材料及形成方法可與導電元件132之材料及形成方法相同或相似。
如第1J圖所示，根據一些實施例，堆疊封裝結構133並接合至中介層基板112之上。在一些實施例中，封裝結構133延伸越過半導體晶粒108。在一些實施例中，封裝結構133延伸越過填充凹槽126的保護層130。
在一些實施例中，藉由接合結構140接合封裝結構133與中介層基板112。可使用一或多道回焊(reflow)來形成接合結構140。在上述所提之回焊(reflow)製程中，可將導電元件131與138(如第1I圖所示)熔融在一起以形成接合結構140。每一接合結構140可包含焊接材料部分以及接合墊。可形成接合墊於焊接材料部分與互連結構136之間。
可對本揭露之實施例進行許多變化及/或改良。在 一些其他實施例中，未堆疊封裝結構133於中介層基板112之上。在一些其他實施例中，未提供封裝結構133。
如第1K圖所示，形成底膠層142以環繞並保護接合結構140。底膠層142之材料及形成方法可與底膠層128之材料及形成方法相同或相似。
可對本揭露之實施例進行許多變化及/或改良。在一些其他實施例中，未形成底膠層128。
可對本揭露之實施例進行許多變化及/或改良。在一些其他實施例中，未形成底膠層128、保護層130、以及底膠層142。
可對本揭露之實施例進行許多變化及/或改良。在一些其他實施例中，在接合封裝結構133至中介層基板112之後，形成保護材料層。保護材料層圍繞接合結構140、半導體晶粒108、及接合結構122及110。在一些實施例中，形成具有圍繞接合結構及半導體晶粒之部分的保護材料層於單一的形成製程中。圍繞接合結構之保護材料層的部分可作為底膠層。圍繞半導體晶粒之保護材料層的部分可作為保護層。
第2A至2D圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。如第2A圖所示，接受或形成類似於第1C圖所示之結構。在一些實施例中，半導體晶粒108高於中介層基板112。在一些實施例中，設置半導體晶粒108之頂面於高於中介層基板112之頂面的高度。
如第2A圖所示，中介層基板112具有高度H1，而半導體晶粒具有高度H2。在一些實施例中，高度H2大於高度H1。 中介層基板112之高度H1可在20微米(μm)至約300微米(μm)的範圍。
如第2B圖所示，根據一些實施例，形成底膠層128以保護接合結構110及122。第2B圖所示之底膠層128之材料及形成方法可與第1D圖所示之底膠層128之材料及形成方法相同或相似。在一些實施例中，如第2B圖所示，底膠層128向上延伸以部分或完全填充由中介層基板112之內部側壁124所圍繞之凹槽126。在這些情況中，底膠層128也可作為保護半導體晶粒108之保護層。在一些實施例中，如第2B圖所示，半導體晶粒108之頂面高於底膠層128之頂面。
如第2C圖所示，相似於第1J圖所繪示之實施例，根據一些實施例，堆疊封裝結構113並接合至中介層基板112之上。使用接合結構140以達成在封裝結構133與中介層基板112之間的物理性(physical)接合及電性連接。藉由中介層基板112及互連結構102來建立封裝結構133中的裝置元件與半導體晶粒108中的裝置元件之間的電性連接。
如第2C圖所示，根據一些實施例，使用黏合層202以增加半導體晶粒108與封裝結構133之間的黏著力(adhesion)。黏合層202可為晶片接合膜(die attachment film，DAF)。在一些實施例中，在封裝結構133與中介層基板112藉由接合結構140接合之前，形成黏合層202於半導體晶粒108之上。在一些其他實施例中，在接合封裝結構133與中介層基板112之前，形成黏合層202於封裝結構133之上。
可對本揭露之實施例進行許多變化及/或改良。在 一些其他實施例中，未形成黏合層202。
如第2D圖所示，根據一些實施例，藉由接合結構206接合第2C圖中所示的結構至基板204。接合結構206之材料及形成方法可與接合結構122之材料及形成方法相同或相似。在一些實施例中，基板204係為印刷電路板。在一些實施例中，基板204係為半導體基板，其具有導電部件形成於其之上。
在一些實施例中，如第2D圖所示，形成底膠層208於基板204之上以圍繞並保護接合結構206。底膠層208之材料及形成方法可與底膠層128之材料及形成方法相同或相似。在一些實施例中，底膠層208向上延伸以覆蓋互連結構102之側壁。在一些實施例中，底膠層208向上延伸以覆蓋底膠層128之側壁。在一些實施例中，底膠層208向上延伸以部分覆蓋中介層基板112之側壁。
第3A至3E圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。如第3A圖所示，接收或提供相似於第1E圖所示之結構。在一些實施例中，半導體晶粒108與中介層基板112等高。然而，本揭露之實施例不限定於此。在一些其他實施例中，相似於第2A圖所繪示之實施例，半導體晶粒108高於中介層基板112。在這些情況中，半導體晶粒108之頂面與互連結構102的距離大於中介層基板112之頂面與互連結構102的距離。
然後，如第3A圖所示，根據一些實施例，形成開口302在保護層130中以部分曝露導電部件116。可使用能量束鑽孔(energy beam drilling)製程、機械鑽孔製程、光微影 (photolithography)製程、蝕刻製程、一或多種其他可應用的製程、或前述之組合來形成開口302。
如第3A圖所示，根據一些實施例，形成導電元件131於中介層基板112之曝露的導電部件116之上。第3A圖所示之導電元件131之材料及形成方法可與第1F圖所示之導電元件131之材料及形成方法相同或相似。在一些其他實施例中，設置每一導電元件131於對應的開口302中。在一些其他實施例中，導電元件302之部分從開口302突出(未繪示)。在這些情況中，導電元件302之頂面高於保護層130之頂面。
如第3B圖所示，根據一些實施例，由上朝下倒裝第3A圖中所示之結構，之後移除載體基板100以曝露出一些導電部件106。在一些實施例中，在移除載體基板100之前，由上朝下倒裝第3A圖中所示的結構至第二載體基板(未繪示)之上。第二載體基板可為承載帶框(carrier tape frame)。之後，如第3C圖所示，根據一些實施例，形成導電元件132於曝露的導電部件106之上。第3C圖所示之導電元件132之材料及形成方法可與第1H圖所示之導電元件132之材料及形成方法相同或相似。
如第3D圖所示，根據一些實施例，相似於第1I圖所繪示之實施例，由上朝下倒裝第3C圖中所示的結構至封裝結構133。
如第3E圖所示，根據一些實施例，相似於第1J圖所繪示之實施例，藉由接合結構140接合封裝結構133與中介層基板112。之後，相似於第1K圖所繪示之實施例，如第3E圖所 示，根據一些實施例，形成底膠層142。
可對本揭露之實施例進行許多變化及/或改良。在一些其他實施例中，未形成保護層130。在一些實施例中，形成底膠層142以保護接合結構140。底膠層142可填充由中介層基板112之內部側壁124所圍繞之凹槽126。因此，底膠層142也可圍繞半導體晶粒108並且作為保護層。
第4A至4B圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。如第4A圖所示，形成相似於第3E圖所繪示之實施例之結構。在一些實施例中，中介層基板112包含形成於基座部分114中的多個導電部件116’。在一些實施例中，每一導電部件116’未穿過基座部分114之相反面。
在一些實施例中，底膠層128與接合結構110直接接觸。在一些實施例中，底膠層128未直接接觸接合結構122。在一些實施例中，保護層130與接合結構122直接接觸。在一些實施例中，保護層130未直接接觸接合結構110。
在一些實施例中，半導體晶粒108高於中介層基板112。設置半導體晶粒108之頂面在高於中介層基板112的高度。如第4A圖所示，封裝結構133之互連結構136包含多個導電部件137。電性連接一些導電部件137至接合結構140。
如第4B圖所示，相似於第2D圖所繪示之實施例，根據一些實施例，藉由接合結構206接合第4A圖中所示之結構至基板204。在一些實施例中，形成底膠層208以保護接合結構206。
第5A至5F圖係根據一些實施例繪示出形成晶片封 裝之製程的各種階段之剖面圖。如第5A圖所示，接收或提供相似於第1E圖中所示之結構。在一些實施例中，半導體晶粒108等高於中介層基板112。然而，本揭露之實施例並不限定於此。在一些其他實施例中，相似於第2A圖所繪示之實施例，半導體晶粒108高於中介層基板112。
之後，如第5A圖所示，根據一些實施例，形成開口於保護層130中以部分曝露導電部件116。相似於開口302，可使用能量束鑽孔(energy beam drilling)製程、機械鑽孔製程、光微影(photolithography)製程、蝕刻製程、一或多種其他可應用的製程、或前述之組合來形成開口。
之後，如第5A圖所示，根據一些實施例，形成導電元件502於曝露的導電部件116之上以填充形成於保護層130中的開口。在一些實施例中，導電元件502係為導電柱。在一些實施例中，導電元件502之頂面與保護層130之頂面大致上為共平面。在一些實施例中，可使用平坦化製程以確保導電元件502之頂面與保護層130之頂面大致上為共平面。平坦化製程可包含機械研磨製程、化學機械研磨(Chemical Mechanical Polish，CMP)、一或多種其他可應用的製程、或前述之組合。
導電元件502可由或包含銅、金、鈷、鋁、鉑、石墨烯、一或多種其他適合的導電材料、或前述之組合所形成。可使用電鍍(electroplating)製程、無電鍍(electroless plating)製程、化學氣相沉積(CVD)製程、物理氣相沉積(PVD)製程、印刷(printing)製程、一或多種其他可應用的製程、或前述之組合來形成導電元件502。
如第5B圖所示，根據一些實施例，形成互連結構504於保護層130及導電元件502之上。互連結構504可包含絕緣層506及多個導電部件508。絕緣層506可包含多層的子層(sub-layer)。互連結構504之材料及形成方法可與互連結構102之材料及形成方法相同或相似。
之後，如第5B圖所示，根據一些實施例，形成導電元件510於互連結構504之一些導電部件508之上。導電元件510之材料及形成方法可與第1F圖中所繪示之導電元件131之材料及形成方法相同或相似。在一些實施例中，互連結構504之底面之大部分係與相同材料的膜層(即保護層130)直接接觸。在一些實施例中，保護層130及絕緣層506兩者皆由相同或相似的高分子材料所形成。因此，保護層130及絕緣層506具有相似的熱膨脹係數(thermal expansion coefficient)。因此，互連結構504在後續的熱製程過程中可承受較少的熱應力(thermal stress)。可確保互連結構504之品質與可靠度。
如第5C圖所示，根據一些實施例，由上朝下倒裝第5B圖中所示的結構，並且移除載體基板100以曝露出一些導電部件106。在一些實施例中，在移除載體基板100之前，由上朝下倒裝第5B圖中所示的結構至第二載體基板(未繪示)之上。第二載體基板可為承載帶框(carrier tape frame)。
之後，如第5D圖所示，根據一些實施例，形成導電元件132於曝露的導電部件106之上。第5D圖所示之導電元件132之材料及形成方法可與第1H圖所示之導電元件132之材料及形成方法相同或相似。
如第5E圖所示，相似於第1I圖所繪示之實施例，根據一些實施例，由上朝下倒裝第5D圖中所示的結構以接合至封裝結構133之上。
如第5F圖所示，相似於第1J圖所繪示之實施例，根據一些實施例，藉由接合結構540接合封裝結構133與中介層基板112。在一些實施例中，可使用回焊(reflow)製程將對準的導電元件138及510熔融在一起。因此，形成了接合結構540。接合結構540之材料及形成方法可與第1J圖所示之接合結構140之材料及形成方法相同或相似。
之後，相似於第1K圖所繪示之實施例，如第5F圖所示，根據一些實施例，形成底膠層542以保護接合結構540。底膠層542之材料及形成方法可與第1K圖所示之底膠層142之材料及形成方法相同或相似。
第6A至6B圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。如第6A圖所示，形成相似於第5F圖中所繪示之實施例之結構。在一些實施例中，中介層基板112包含形成於基座部分114中的多個導電部件116’。在一些實施例中，中介層基板112也包含導電元件502。導電元件502可為導電通孔。在一些實施例中，每一導電部件116’未穿透基座部分114之相反面。
在一些實施例中，底膠層128與接合結構110直接接觸。在一些實施例中，底膠層128未直接接觸接合結構122。在一些實施例中，保護層130與接合結構122直接接觸。在一些實施例中，保護層130未直接接觸接合結構110。
在一些實施例中，半導體晶粒108高於中介層基板112。設置半導體晶粒108之頂面在高於中介層基板112的高度。如第6A圖所示，封裝結構133之互連結構136包含多個導電部件137。電性連接一些導電部件137至接合結構540。
在一些實施例中，保護層130覆蓋中介層基板112與半導體晶粒108之頂面，並且形成互連結構504於保護層130之上。避免互連結構504與半導體晶粒108及保護層130之間可能具有較高應力的界面直接接觸。因此，互連結構504可具有較佳的可靠度。避免導電部件506之佈線(routing)受到限制。
在一些其他實施例中，互連結構與半導體晶粒及保護層之間的界面直接接觸。在一些情況中，互連結構之部分延伸越過此界面可能會承受較高的應力。可能需要遠離這些高應力部分(即排除區(kick-out zone))來形成導電部件，以確保可靠的電性連接。導電部件的佈線(routing)因而受到限制。
如第6B圖所示，相似於第2D圖所繪示之實施例，根據一些實施例藉由接合結構206接合第6A圖中所示的結構至基板204。在一些實施例中，形成底膠層208以保護接合結構206。
第7A至7I圖係根據一些實施例繪示出形成晶片封裝之製程的各種階段之剖面圖。如第7A所示，接收或形成相似與第1A圖中所示的結構。
如第7B圖所示，根據一些實施例，形成阻隔元件702於互連結構102之上。在一些實施例中，阻隔元件702係為環型(ring)結構，其連續圍繞接合結構110及半導體晶粒108。 阻隔元件702可由絕緣材料、導電材料、半導體材料、或前述之組合所形成。在一些實施例中，阻隔元件702係由或包含感光高分子材料所形成。在一些實施例中，形成感光高分子材料於互連結構102之上。之後，使用光微影(photolithography)製程以圖案化此感光高分子材料層。因此，形成了具有所期望的圖案之阻隔元件702。
之後，相似於第1B圖所繪示之實施例，如第7B圖所示，係根據一些實施例挑揀及放置半導體晶粒108於互連結構102之上。在一些實施例中，藉由接合結構110接合半導體晶粒108至互連結構102。
如第7C圖所示，根據一些實施例，形成底膠層128’於半導體晶粒108與互連結構102之間以保護接合結構110。底膠層128’之材料及形成方法可與第1D圖所示之底膠層128之材料及形成方法相同或相似。在一些實施例中，因阻隔元件702的緣故，限制了使用於形成底膠層128’的材料(例如：液態高分子材料)在所圍繞的區域中。避免一些導電部件106被底膠層128’覆蓋，其有利於後續的接合製程。
如第7D圖所示，相似於第1C圖所繪示之實施例，根據一些實施例，設置中介層基板112於互連結構102之上。藉由接合結構122接合中介層基板112至互連結構102。因為藉由阻隔元件702來阻隔底膠層128’而不會覆蓋曝露的導電部件106，所以更容易執行接合結構122之形成。
第9圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。在一些實施例中，第9圖繪示出第7D圖中 所示之結構的上視圖。中介層基板112之內部側壁124圍繞凹槽126。凹槽126圍繞半導體晶粒108。凹槽126也曝露了底膠層128’、阻隔元件702、及互連結構102。如第9圖所示，阻隔元件702係為環型結構，其圍繞半導體晶粒108。將底膠層128’限制在阻隔元件702所圍繞的區域中。也可形成阻隔元件702於第1、2、3、4、5、及/或6圖所繪示的實施例中。
如第7E圖所示，相似於第1E圖所繪示之實施例，根據一些實施例，形成保護層130。之後，相似於第1F圖所繪示之實施例，如第7F圖所示，根據一些實施例，薄化保護層130以曝露出導電部件116。在一些其他實施例中，使用曝露的成型製程(molding process)或灌膠製程(dispensing process)來形成保護層130。在曝露的成型製程中，在射出成型複合材料以形成保護層130之過程中藉由模具(mold)來保護導電部件116。保護層130不會覆蓋導電部件116。在這些情況中，因為已經曝露出導電部件116，可不需要薄化製程。接著形成導電元件131於曝露的導電部件116之上。
如第7G圖所示，相似於第1G-1H圖所繪示之實施例，根據一些實施例，移除載體基板100，並且形成導電元件132。
如第7H圖所示，相似於第1I及1J圖所繪示之實施例，根據一些實施例，藉由接合結構140接合封裝結構133至中介層基板112。在一些實施例中，相似於第2C圖所繪示之實施例，形成黏合層202以改善半導體晶粒108與封裝結構133之間的黏著力(adhesion)。在一些實施例中，黏合層202係由或包含 一或多種具有高熱傳導性(thermal conductivity)的材料所形成。在一些實施例中，具有高熱傳導性的黏合層202具有與半導體晶粒108之頂面相同大小的面積。因此，可更有效率的散出在半導體晶粒108中的裝置元件之運作過程中所產生的熱。在一些實施例中，具有高熱傳導性的黏合層202的面積大於半導體晶粒108之頂面。因此，可確保半導體晶粒108之頂面被黏合層202完全地覆蓋。
然而，本揭露之實施例並不限定於此，在一些實施例中，未形成黏合層202。
如第7I圖所示，相似於第1K圖所繪示之實施例，形成底膠層142以保護接合結構140。
可對本揭露之實施例進行許多變化及/或改良。在一些實施例中，可挑揀及放置多個半導體晶粒至由相同的凹槽126曝露出的導電部件106之上。
第10圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。在一些實施例中，第10圖繪示出在第1、2、3、4、5、6、及/或7圖中所繪示之實施例的上視圖。在一些實施例中，二或多個半導體晶粒(例如：半導體晶粒108A及108B)係由中介層基板112之內部側壁所圍繞。在一些其他實施例中，元件108A及108B之一或每一個係為半導體裝置，其包含一個晶片、多個晶片、或系統積體電路(system-on-integrated-circuit，SoIC)晶片裝置。因此，參考符號「108A及108B」也可用來表示半導體裝置。
可對本揭露之實施例進行許多變化及/或改良。第 11圖係根據一些實施例繪示出形成晶片封裝之製程階段的上視圖。在一些實施例中，中介層基板112之內部側壁124圍繞一橢圓區域。在一些其他實施例中，由中介層基板112之內部側壁124所圍繞之區域可為方形、圓形、或其他類似的形狀。在一些實施例中，第11圖繪示出在第1、2、3、4、5、6、及/或7圖中所繪示之實施例的上視圖。
可對本揭露之實施例進行許多變化及/或改良。舉例來說，中介層基板112之內部側壁124可為傾斜(inclined)的側壁。
第12圖係根據一些實施例繪示出晶片封裝之剖面圖。如第12圖所示，形成相似於第4B圖中所示之結構。在一些實施例中，如第12圖所示，內部側壁124係為傾斜的側壁。凹槽126沿著從中介層基板112之底部朝向頂部的方向變寬。在第1至7圖中所繪示之每一實施例之內部側壁124可改良為傾斜的側壁。
第13圖係根據一些實施例繪示出晶片封裝之剖面圖。如第13圖所示，形成相似於第4B圖中所示之結構。在一些實施例中，如第13圖所示，內部側壁124係為傾斜的側壁。凹槽126沿著從中介層基板112之底部朝向頂部的方向變窄。
本揭露之實施例形成具有中介層基板的晶片封裝。接合中介層基板及半導體晶粒至重佈結構(redistribution structure)之上。中介層基板係為一環型結構，其圍繞半導體晶粒。半導體晶粒等高於或高於中介層基板。未堆疊半導體晶粒於中介層基板之上，並且半導體晶粒被中介層基板部分圍繞。 減少晶片封裝之總高度，其可利於後續與其他封裝結構之接合。
根據一些實施例提供一種晶片封裝之形成方法。此方法包含：設置半導體晶粒於載體基板之上。此方法也包含設置中介層基板於此載體基板之上。此中介層基板具有凹槽，此凹槽穿過該中介層基板之相反面。此中介層基板具有圍繞半導體晶粒之內部側壁，並且此半導體晶粒等高於或高於此中介層基板。此方法更包含在中介層基板之凹槽中形成保護層，以圍繞半導體晶粒。另外，此方法包含移除載體基板以及堆疊封裝結構於該中介層基板之上。在一些實施例中，其中此保護層覆蓋此中介層基板以及此半導體晶粒，且此方法更包含：形成開口於此保護層中，以曝露出此中介層基板之導電部件；以及形成導電元件於此中介層基板之此導電部件之上。在一些實施例中，此方法更包含：在設置此半導體晶粒以及此中介層基板於此載體基板之上之前，形成互連結構於此載體基板之上。在一些實施例中，其中此保護層過度填充此凹槽以覆蓋此半導體晶粒，且此方法更包含：在堆疊此封裝結構於此中介層基板之上之前，形成第二互連結構於此保護層之上；以及接合此封裝結構至此第二互連結構。在一些實施例中，其中此第二互連結構未直接接觸在此半導體晶粒與此保護層之間之界面。在一些實施例中，其中在設置此中介層基板於此互連結構之上之前，設置此半導體晶粒於此互連結構之上。在一些實施例中，此方法更包含：在移除此載體基板之後，形成複數導電凸塊於此互連結構之表面之上，其中此互連結構之此表面起初(originally) 面向此載體基板。在一些實施例中，其中此封裝結構延伸越過此半導體晶粒。在一些實施例中，此方法更包含設置第二半導體晶粒於此載體基板之上，其中此中介層基板之內部側壁圍繞此第二半導體晶粒。在一些實施例中，其中此中介層基板係為印刷電路板。
根據一些實施例提供一種晶片封裝之形成方法。此方法包含：形成第一重佈結構於載體基板之上，並且接合一半導體晶粒與此第一重佈結構。此方法也包含接合中介層基板與此第一重佈結構。此中介層基板具有圍繞此半導體晶粒之環型結構，並且此半導體晶粒等高於或高於此中介層基板。此方法更包含形成保護層以圍繞此半導體晶粒。此保護層之一部分在此中介層基板與此半導體晶粒之間。另外，此方法包含移除此載體基板，以及接合封裝結構於此中介層基板之上。此半導體晶粒在此封裝結構與此第一重佈結構之間。在一些實施例中，此方法更包含：在移除此載體基板之後且在接合此封裝結構於此中介層基板之上之前，形成複數導電凸塊於此第一重佈結構之上，其中此第一重佈結構在此些導電凸塊與此半導體晶粒之間。在一些實施例中，此方法更包含：在接合此封裝結構於此中介層基板之上之前，薄化此保護層以曝露此中介層基板。在一些實施例中，此方法更包含：形成導電元件於此保護層中，其中此導電元件電性連接至此中介層基板之導電部件。在一些實施例中，此方法更包含：形成第二重佈結構於此保護層之上，其中此保護層之一部分在此第二重佈結構與此半導體晶粒之間。
根據一些實施例提供晶片封裝。此晶片封裝包含：第一重佈結構，以及接合於此第一重佈結構之上的半導體裝置。此晶片封裝也包含接合於此第一重佈結構之上的中介層基板。此中介層基板具有圍繞此半導體裝置之內部側壁，並且此半導體裝置等高於或高於此中介層基板。此晶片封裝更包含圍繞此半導體裝置的保護層。另外，此晶片封裝包含第二重佈結構於此保護層之上。此第二重佈結構之第一導電部件電性連接至此中介層基板之第二導電部件。在一些實施例中，其中此保護層之一部分位於此第二重佈結構與此半導體裝置之間。在一些實施例中，此晶片封裝更包含：第二半導體裝置，接合於此第一重佈結構之上，其中此中介層基板之內部側壁圍繞此第二半導體裝置。在一些實施例中，此晶片封裝更包含：封裝結構，接合至此第二重佈結構。在一些實施例中，其中此中介層結構之內部側壁為傾斜的側壁。
根據一些實施例提供晶片封裝。此晶片封裝包含：第一重佈結構，以及接合於此第一重佈結構之上的半導體裝置。晶片封裝也包含接合於此第一重佈結構之上的中介層基板。此中介層基板具有圍繞此半導體裝置之內部側壁，並且此半導體裝置等高於或高於此中介層基板。此晶片封裝更包含圍繞此半導體裝置及在保護層之上的第二重佈結構的保護層。此第二重佈結構之第一導電部件電性連接至此中介層基板之第二導電部件。
前述概述了一些實施例的部件，使得本揭露所屬技術領域中具有通常知識者可以更加理解本揭露實施例的觀 點。本揭露所屬技術領域中具有通常知識者應可理解，他們可以輕易使用本揭露實施例作為基礎，設計或修改其他的製程或是結構，以達到與在此介紹的實施例相同的目的及/或優點。本揭露所屬技術領域中具有通常知識者也應理解，此類等效的結構並不悖離本揭露實施例的精神與範疇，並且在不悖離本揭露實施例的精神與範疇的情況下，在此可以做各種的改變、取代和替換。因此，本揭露之保護範圍當視後附之申請專利範圍所界定為準。
102、136‧‧‧互連結構
104‧‧‧絕緣層
106、116’、137‧‧‧導電部件
108‧‧‧半導體晶粒
110、140、206‧‧‧接合結構
112‧‧‧中介層基板
114‧‧‧基座部分
122‧‧‧接合結構
124‧‧‧內部側壁
126‧‧‧凹槽
128、208‧‧‧底膠層
130‧‧‧保護層
133‧‧‧封裝結構
134‧‧‧元件
204‧‧‧基板

Claims (12)

  1. 一種晶片封裝之形成方法，包括：形成一互連結構於一載體基板之上；在形成該互連結構於該載體基板之上之後，設置一半導體晶粒於該載體基板之上；在形成該互連結構於該載體基板之上之後，設置一中介層基板於該載體基板之上，其中該中介層基板具有一凹槽，該凹槽穿過該中介層基板之相反面，該中介層基板具有圍繞該半導體晶粒之內部側壁，並且該半導體晶粒等高於或高於該中介層基板；在該中介層基板之該凹槽中形成一保護層，以圍繞該半導體晶片，其中該保護層之一部分在該中介層基板與該半導體晶粒之間，且該保護層完全填充並過度填充該凹槽，以覆蓋該半導體晶粒；移除該載體基板；形成一第二互連結構於該保護層之上，其中該第二互連結構未直接接觸在該半導體晶粒與該保護層之間之一界面；於形成該第二互連結構於該保護層之上之後，堆疊一封裝結構於該中介層基板之上；以及接合該封裝結構至該第二互連結構。
  2. 如申請專利範圍第1項所述之晶片封裝之形成方法，其中該保護層覆蓋該中介層基板以及該半導體晶粒，且該方法更包括：形成一開口於該保護層中，以曝露出該中介層基板之一導 電部件；以及形成一導電元件於該中介層基板之該導電部件之上。
  3. 如申請專利範圍第1項所述之晶片封裝之形成方法，其中在設置該中介層基板於該載體基板之上之前，設置該半導體晶粒於該互連結構之上。
  4. 如申請專利範圍第1項所述之晶片封裝之形成方法，其中該封裝結構延伸越過該半導體晶粒。
  5. 如申請專利範圍第1至4項中任一項所述之晶片封裝之形成方法，更包括設置一第二半導體晶粒於該載體基板之上，其中該中介層基板之內部側壁圍繞該第二半導體晶粒。
  6. 一種晶片封裝之形成方法，包括：形成一第一重佈結構於一載體基板之上；接合一半導體晶粒與該第一重佈結構；接合一中介層基板與該第一重佈結構，其中該中介層基板具有圍繞該半導體晶粒之一環型結構以及穿過該中介層基板之相反面之一凹槽，以及圍繞該半導體晶粒之複數個內部側壁，並且該半導體晶粒等高於或高於該中介層基板，該中介層基板之該等內部側壁為傾斜的側壁；形成一保護層以圍繞該半導體晶粒，其中該保護層之一部分在該中介層基板與該半導體晶粒之間，且該保護層完全填充該凹槽；移除該載體基板；以及接合一封裝結構於該中介層基板之上，其中該半導體晶粒在該封裝結構與該第一重佈結構之間。
  7. 如申請專利範圍第6項所述之晶片封裝之形成方法，更包括在移除該載體基板之後且在接合該封裝結構於該中介層基板之上之前，形成複數導電凸塊於該第一重佈結構之上，其中該第一重佈結構在該些導電凸塊與該半導體晶粒之間。
  8. 如申請專利範圍第6項所述之晶片封裝之形成方法，更包括在接合該封裝結構於該中介層基板之上之前，薄化該保護層以曝露該中介層基板。
  9. 如申請專利範圍第6項所述之晶片封裝之形成方法，更包括形成一導電元件於該保護層中，其中該導電元件電性連接至該中介層基板之一導電部件。
  10. 如申請專利範圍第6至9項中任一項所述之晶片封裝之形成方法，更包括形成一第二重佈結構於該保護層之上，其中該保護層之一部分在該第二重佈結構與該半導體晶粒之間。
  11. 一種晶片封裝，包括：一第一重佈結構；一半導體裝置，接合於該第一重佈結構之上；一中介層基板，接合於該第一重佈結構之上，其中該中介層基板具有圍繞該半導體裝置之複數個內部側壁，並且該半導體裝置等高於或高於該中介層基板，該中介層基板之該等內部側壁為傾斜的側壁；一保護層，圍繞該半導體裝置，設置在該第一重佈結構與該中介層基板之間，完全覆蓋該等內部側壁；以及 一第二重佈結構，於該保護層之上，其中該第二重佈結構之一第一導電部件電性連接至該中介層基板之一第二導電部件。
  12. 如申請專利範圍第11項所述之晶片封裝，更包括一封裝結構，接合至該第二重佈結構。
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