TWI689999B - 半導體裝置 - Google Patents

半導體裝置 Download PDF

Info

Publication number
TWI689999B
TWI689999B TW107124450A TW107124450A TWI689999B TW I689999 B TWI689999 B TW I689999B TW 107124450 A TW107124450 A TW 107124450A TW 107124450 A TW107124450 A TW 107124450A TW I689999 B TWI689999 B TW I689999B
Authority
TW
Taiwan
Prior art keywords
wafer
semiconductor
group
semiconductor wafer
metal wire
Prior art date
Application number
TW107124450A
Other languages
English (en)
Other versions
TW201939626A (zh
Inventor
下川一生
内田雅之
東條啓
田辺成俊
伊藤宜司
Original Assignee
日商東芝記憶體股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日商東芝記憶體股份有限公司 filed Critical 日商東芝記憶體股份有限公司
Publication of TW201939626A publication Critical patent/TW201939626A/zh
Application granted granted Critical
Publication of TWI689999B publication Critical patent/TWI689999B/zh

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/11—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/117—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04026—Bonding areas specifically adapted for layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331—Disposition
    • H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92147—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06506—Wire or wire-like electrical connections between devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/1015—Shape
    • H01L2924/10155—Shape being other than a cuboid
    • H01L2924/10156—Shape being other than a cuboid at the periphery
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

實施形態提供一種能夠兼顧整體之薄化與提高線接合性之半導體裝置。 於實施形態之半導體裝置中，複數個第1半導體晶片各者具有：第1端部，其越下段之第1半導體晶片越較上段之第1半導體晶片更朝第1方向突出；以及第1電極墊，其設置於第1端部，且接合有第1金屬線。複數個第2半導體晶片之各者具有：第2端部，其越下段之第2半導體晶片越較上段之第2半導體晶片更朝第2方向突出；以及第2電極墊，其設置於第2端部，且接合有第2金屬線。第3半導體晶片具有：第1部分，其重疊於第1晶片群之上；第2部分，其較第1晶片群及第2晶片群更朝第2方向突出，且較第1部分更厚；以及第3電極墊，其設置於第2部分，且接合有第3金屬線。

Description

半導體裝置
本發明之實施形態係關於一種半導體裝置。
已知有一種半導體裝置，其具備配線基板、積層於配線基板上之第1元件群、以及積層於第1元件群上之第2元件群。第1元件群之複數個晶片係以使各自之墊排列邊朝相同方向、且電極墊不相互重疊之方式呈階梯狀積層。第2元件群之複數個晶片係以使各自之墊排列邊朝相同方向、且電極墊不相互重疊之方式，朝與第1元件群之階梯部相反之方向呈階梯狀積層。於此種半導體裝置中，提出使第2元件群之複數個晶片中最下段之晶片之厚度較其他晶片之厚度厚。
本發明之實施形態提供一種能夠兼顧整體之薄化與線接合性之提高之半導體裝置。
根據本發明之實施形態，半導體裝置具備：配線基板；第1晶片群，其具有於上述配線基板之上階梯狀積層之複數個第1半導體晶片；第2晶片群，其具有於上述第1晶片群之上階梯狀積層之複數個第2半導體晶片；第3半導體晶片，其設置於上述第1晶片群與上述第2晶片群之間；第1金屬線，其將上述第1晶片群與上述配線基板連接；第2金屬線，其將上述第2晶片群與上述配線基板連接；以及第3金屬線，其將上述第3半導體晶片與上述配線基板連接。上述複數個第1半導體晶片之各者具 有：第1端部，其越下段之第1半導體晶片越較上段之第1半導體晶片更朝第1方向突出；以及第1電極墊，其設置於上述第1端部，且接合有上述第1金屬線。上述複數個第2半導體晶片之各者具有：第2端部，其越下段之第2半導體晶片越較上段之第2半導體晶片更朝與上述第1方向相反之第2方向突出；以及第2電極墊，其設置於上述第2端部，且接合有上述第2金屬線。上述第3半導體晶片具有：第1部分，其重疊於上述第1晶片群之上；第2部分，其較上述第1晶片群及上述第2晶片群更朝上述第2方向突出，且較上述第1部分更厚；以及第3電極墊，其設置於上述第2部分，且接合有上述第3金屬線。
1:半導體裝置
2:半導體裝置
5:金屬線
8:槽
10:第1晶片群
11:半導體晶片
11a:側面
13:電極墊
20:第2晶片群
21:半導體晶片
23:電極墊
30:第3晶片群
31:半導體晶片
33:電極墊
40:第4晶片群
41:半導體晶片
43:電極墊
50:半導體晶片
51:第1部分
52:第2部分
52a:側面
53:電極墊
60:半導體晶片
61:第1部分
62:第2部分
63:電極墊
70:半導體晶片
71:第1部分
72:第2部分
73:電極墊
81:半導體晶片
82:電極墊
100:配線基板
110:控制層
111:控制元件
112:樹脂層
113:電極墊
150:樹脂部
200:記憶體元件
300:樹脂層
500:切割保護膠帶
W:晶圓
圖1係本發明之實施形態之半導體裝置之模式剖視圖。
圖2係本發明之實施形態之半導體裝置之一部分之模式放大剖視圖。
圖3係本發明之實施形態之半導體裝置之一部分之模式放大俯視圖。
圖4(a)及(b)係表示本發明之實施形態之半導體裝置之製造方法的模式剖視圖。
圖5(a)及(b)係表示本發明之實施形態之半導體裝置之製造方法的模式剖視圖。
圖6(a)及(b)係表示本發明之實施形態之半導體裝置之製造方法的模式剖視圖。
圖7(a)及(b)係表示本發明之實施形態之半導體裝置之製造方法的模式剖視圖。
圖8(a)~(c)係表示本發明之實施形態之半導體裝置之製造方法的模 式剖視圖。
圖9係本發明之實施形態之半導體裝置之一部分之模式放大剖視圖。
圖10係比較例之半導體裝置之模式剖視圖。
[相關申請案]
本申請案享有以日本專利申請案2018-48046號(申請日：2018年3月15日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
以下，參照圖式，對本發明之實施形態進行說明。於各圖中，對相同要素標註相同符號，並適當省略詳細之說明。再者，圖式係模式性之圖，各部分之厚度與寬度之關係、部分間之大小之比率等未必與實際情況相同。又，即便於表示相同部分之情形時，亦存在彼此之尺寸或比率根據圖式而不同地表達之情況。
圖1係本發明之實施形態之半導體裝置1之模式剖視圖。
半導體裝置1具有：配線基板100；晶片群10、20、30、40，其等包含積層於配線基板100之上之複數個半導體晶片；金屬線5，其將半導體晶片與配線基板100連接；以及樹脂部150，其將複數個半導體晶片及金屬線5密封。
於圖1所示之例中，將4個晶片群(第1晶片群10、第2晶片群20、第3晶片群30、以及第4晶片群40)積層於配線基板100之上。
第1晶片群10具有於配線基板100之上呈階梯狀積層之複數個半導體晶片11。第2晶片群20具有於第1晶片群10之上呈階梯狀積層之 複數個半導體晶片21。第3晶片群30具有於第2晶片群20之上呈階梯狀積層之複數個半導體晶片31。第4晶片群40具有於第3晶片群30之上呈階梯狀積層之複數個半導體晶片41。
第1晶片群10之複數個半導體晶片11之各者具有接合有金屬線5之端部(圖1中為右側之端部)。該等複數個半導體晶片11之複數個端部形成階差而呈階梯狀排列。越靠下段之半導體晶片11之端部，較上段之半導體晶片11之端部更朝第1方向(圖1中為右方向)突出。
於各個半導體晶片11之端部設置有電極墊13。各個電極墊13未被其他半導體晶片覆蓋。半導體晶片11具有帶4條邊之四邊形狀之平面形狀。沿著該半導體晶片11之1邊排列有複數個電極墊13。
金屬線5接合於電極墊13。金屬線5將電極墊13與配線基板100之未圖示之配線連接，又，將電極墊13彼此連接。
第2晶片群20之複數個半導體晶片21之各者具有接合有金屬線5之端部(圖1中為左側之端部)。該等複數個半導體晶片21之複數個端部形成階差而呈階梯狀排列。越靠下段之半導體晶片21之端部，較上段之半導體晶片21之端部更朝與第1方向相反之第2方向(圖1中為左方向)突出。
於各個半導體晶片21之端部設置有電極墊23。各個電極墊23未被其他半導體晶片覆蓋。半導體晶片21具有帶4條邊之四邊形狀之平面形狀。沿著該半導體晶片21之1邊排列有複數個電極墊23。
金屬線5接合於電極墊23。金屬線5將電極墊23與配線基板100之未圖示之配線連接，又，將電極墊23彼此連接。
第3晶片群30之複數個半導體晶片31之各者具有接合有金 屬線5之端部(圖1中為右側之端部)。該等複數個半導體晶片31之複數個端部形成階差而呈階梯狀排列。越靠下段之半導體晶片31之端部，較上段之半導體晶片31之端部更朝第1方向(圖1中為右方向)突出。
於各個半導體晶片31之端部設置有電極墊33。各個電極墊33未被其他半導體晶片覆蓋。半導體晶片31具有帶4條邊之四邊形狀之平面形狀。沿著該半導體晶片31之1邊排列有複數個電極墊33。
金屬線5接合於電極墊33。金屬線5將電極墊33與配線基板100之未圖示之配線連接，又，將電極墊33彼此連接。
第4晶片群40之複數個半導體晶片41之各者具有接合有金屬線5之端部(圖1中為左側之端部)。該等複數個半導體晶片41之複數個端部形成階差而呈階梯狀排列。越靠下段之半導體晶片41之端部，較上段之半導體晶片41之端部更朝第2方向(圖1中為左方向)突出。
於各個半導體晶片41之端部設置有電極墊43。各個電極墊43未被其他半導體晶片覆蓋。半導體晶片41具有帶4條邊之四邊形狀之平面形狀。沿著該半導體晶片41之1邊排列有複數個電極墊43。
金屬線5接合於電極墊43。金屬線5將電極墊43與配線基板100之未圖示之配線連接，又，將電極墊43彼此連接。
第1晶片群10、第2晶片群20、第3晶片群30、及第4晶片群40之半導體晶片11、21、31、41於面方向之所有區域厚度實質上均勻。
在第1晶片群10與第2晶片群20之間，設置有半導體晶片50。
圖2係該半導體晶片50之一部分之模式放大剖視圖。
圖3係半導體晶片50之一部分之模式放大俯視圖。
半導體晶片50具有第1部分51與第2部分52。第1部分51重疊於第1晶片群10之上。第2部分52較第1晶片群10及第2晶片群20更朝第2方向(圖1、2中為左方向)突出，未重疊於第1晶片群10之上，且未重疊於第2晶片群20之下。
第2部分52之厚度較第1部分51之厚度厚。又，第2部分52之厚度較1個半導體晶片11、21、31、41之厚度厚。半導體晶片50之第2部分52之厚度較第1晶片群10之總厚度薄，第2部分52未與配線基板100相接。
於第2部分52設置有電極墊53。電極墊53未被其他半導體晶片覆蓋。半導體晶片50具有帶4條邊之四邊形狀之平面形狀。如圖3所示，沿著該半導體晶片50之1邊排列有複數個電極墊53。第2部分52沿著複數個電極墊53之排列方向延伸。
如圖1所示，金屬線5接合於電極墊53。金屬線5將電極墊53與配線基板100之未圖示之配線連接。又，於電極墊53接合有與其他半導體晶片21之電極墊23接合之金屬線5。
如圖1所示，在第2晶片群20與第3晶片群30之間，設置有半導體晶片60。
半導體晶片60具有第1部分61與第2部分62。第1部分61重疊於第2晶片群20之上。第2部分62較第2晶片群20及第3晶片群30更朝第1方向(圖1中為右方向)突出，未重疊於第2晶片群20之上，且未重疊於第3晶片群30之下。
第2部分62之厚度較第1部分61之厚度更厚。又，第2部分62之厚度較1個半導體晶片11、21、31、41之厚度更厚。半導體晶片60之 第2部分62之厚度較第2晶片群20之總厚度更薄。
於第2部分62設置有電極墊63。電極墊63未被其他半導體晶片覆蓋。半導體晶片60具有帶4條邊之四邊形狀之平面形狀。沿著該半導體晶片60之1邊排列有複數個電極墊63。
金屬線5接合於電極墊63。金屬線5將電極墊63與配線基板100之未圖示之配線連接。又，於電極墊63接合與其他半導體晶片31之電極墊33接合之金屬線5。
如圖1所示，在第3晶片群30與第4晶片群40之間，設置有半導體晶片70。
半導體晶片70具有第1部分71與第2部分72。第1部分71重疊於第3晶片群30之上。第2部分72較第3晶片群30及第4晶片群40更朝第2方向(圖1中為左方向)突出，未重疊於第3晶片群30之上，且未重疊於第4晶片群40之下。
第2部分72之厚度較第1部分71之厚度更厚。又，第2部分72之厚度較1個半導體晶片11、21、31、41之厚度更厚。半導體晶片70之第2部分72之厚度較第3晶片群30之總厚度更薄。
於第2部分72設置有電極墊73。電極墊73未被其他半導體晶片覆蓋。半導體晶片70具有帶4條邊之四邊形狀之平面形狀。沿著該半導體晶片70之1邊排列有複數個電極墊73。
金屬線5接合於電極墊73。金屬線5將電極墊73與配線基板100之未圖示之配線連接。又，於電極墊73接合與其他半導體晶片41之電極墊43接合之金屬線5。
於半導體晶片11彼此之間、半導體晶片21彼此之間、半導 體晶片31彼此之間、以及半導體晶片41彼此之間，設置有樹脂層300(於圖2中示出一部分樹脂層300)。樹脂層300例如為DAF(die attach film，晶片貼裝膜)。
樹脂層300亦設置於第1晶片群10之最上層之半導體晶片11與半導體晶片50之間、半導體晶片50與第2晶片群20之最下層之半導體晶片21之間、第2晶片群20之最上層之半導體晶片21與半導體晶片60之間、半導體晶片60與第3晶片群30之最下層之半導體晶片31之間、第3晶片群30之最上層之半導體晶片31與半導體晶片70之間、以及半導體晶片70與第4晶片群40之最下層之半導體晶片41之間。
如圖2所示，半導體晶片50之第2部分52中之與第1晶片群10對向之側面52a和第1晶片群10之最上層之半導體晶片11之側面11a分開。於第2部分52之側面52a、與第1晶片群10之最上層之半導體晶片11之側面11a之間形成有間隙。
第2晶片群20與第3晶片群30之間之半導體晶片60之第2部分62中之與第2晶片群20對向之側面亦和第2晶片群20之最上層之半導體晶片21之側面分開，於第2部分62之側面、與第2晶片群20之最上層之半導體晶片21之側面之間形成有間隙。
第3晶片群30與第4晶片群40之間之半導體晶片70之第2部分72中之與第3晶片群30對向之側面亦和第3晶片群30之最上層之半導體晶片31之側面分開，於第2部分72之側面、與第3晶片群30之最上層之半導體晶片31之側面之間形成有間隙。
如圖1所示，在配線基板100與第1晶片群10之間設置有控制層110。控制層110具有樹脂層112、設置於樹脂層112之中之控制元件 111、以及與控制元件111連接之電極墊113。於控制層110之電極墊113接合有金屬線5，該金屬線5將控制元件111與配線基板100之間、以及控制元件111與半導體晶片11之間連接。控制層110亦可設置於第4晶片群40之上。
於配線基板100上設置有樹脂部150。樹脂部150覆蓋控制層110、半導體晶片11、21、31、41、50、60、70、及金屬線5。
如圖2所示，半導體晶片50包含記憶體元件200。其他半導體晶片11、21、31、41、60、70亦包含記憶體元件。半導體晶片60、70之記憶體元件設置於第1部分61、71。
控制層110所包含之控制元件111控制記憶體元件200。
圖10係比較例之半導體裝置2之模式剖視圖。
該比較例之半導體裝置2係於第1晶片群10與第2晶片群20之間、第2晶片群20與第3晶片群30之間、以及第3晶片群30與第4晶片群40之間之半導體晶片81之面方向之所有區域之厚度實質上均勻，在該方面與實施形態之半導體裝置1不同。
藉由將複數個半導體晶片呈階梯狀積層，能夠對各個半導體晶片進行打線接合。為了抑制呈階梯狀積層之複數個半導體晶片之面方向之專有面積之增大，而使設置有電極墊且呈階梯狀排列之端部於第1晶片群10與第2晶片群20之間朝相反方向，於第2晶片群20與第3晶片群30之間朝相反方向，進而於第3晶片群30與第4晶片群40之間朝相反方向。
此種構成中，設置於晶片群10、20、30、40之間之半導體晶片81之設置有電極墊82之端部成為相對於下方之晶片群懸突、且於電極墊82之下無其他半導體晶片支撐之狀態。若對此種電極墊82實施打線 接合，則因接合時之負荷而導致半導體晶片81撓曲，從而金屬線5可能產生接合不良。尤其是半導體晶片81之設置有電極墊82之邊之延伸方向(圖10中為深度方向)之端區域相較於中央區域而言更易撓曲，對形成於該端區域之電極墊82實施之打線接合之不良率易變高。
材料之剛性與厚度之三次方成比例，因此，如圖10所示，可藉由使半導體晶片81較其他半導體晶片11、21、31、41厚而減少撓曲量。然而，如此會妨礙半導體裝置整體(封裝)之薄型化，與產品之發展趨勢背道而馳。
根據實施形態，使具有相對於在下方無其他半導體晶片支撐之下方之晶片群懸突之端部的半導體晶片50、60、70中之懸突部分即第2部分52、62、72之厚度較積層於下方之半導體晶片之第1部分51、61、71之厚度增厚。因此，能夠提高第2部分52、62、72之剛性，且能夠抑制對設置於該第2部分52、62、72之電極墊53、63、73進行打線接合時之半導體晶片50、60、70之變形(撓曲)，從而使線接合性提高。
增厚之第2部分52、62、72係不重疊於晶片群10、20、30、40之上及之下之部分，不會對複數個半導體晶片之總積層厚度造成影響。相對於此，重疊於晶片群10、20、30、40之上及之下之部分即第1部分51、61、71之厚度由於較第2部分52、62、72薄，故而可抑制積層複數個半導體晶片而成之積層體之總厚度增大，不會妨礙半導體裝置1之薄化。因此，根據實施形態，能夠兼顧半導體裝置整體之薄化與線接合良率之提高。
其次，參照圖4(a)~圖8(c)，對本發明之實施形態之半導體裝置1之製造方法進行說明。
如圖4(a)所示，於配線基板100上安裝控制層110，且於該控制層110上呈階梯狀積層第1晶片群10之複數個半導體晶片11。於最下層之半導體晶片11與控制層110之間，設置負責該等兩者之接著之樹脂層300。於半導體晶片11彼此之間亦設置負責該等兩者之接著之樹脂層300。
例如，於半導體晶片11之下表面貼附樹脂層300之後，將半導體晶片11連同樹脂層300一併安裝於控制層110或其他半導體晶片11上。
如圖6(a)所示，於切割保護膠帶500之表面形成樹脂層(例如DAF)300，於該樹脂層300之上貼附晶圓W，例如使用刀片於晶圓W形成槽8，從而晶圓W被單片化為複數個半導體晶片11。
其後，如圖6(b)所示，例如利用雷射將槽8之下之樹脂層300切斷。然後，附樹脂層300之半導體晶片11自切割保護膠帶500剝離，並安裝至圖4(a)所示之控制層110或其他半導體晶片11上。
圖4(b)表示安裝第1晶片群10之最上層之半導體晶片11之步驟。於第1晶片群10之最上層之半導體晶片11之上表面及下表面之兩面貼附樹脂層300。
如圖7(a)所示，於貼附於切割保護膠帶500上之樹脂層300之半導體晶片11之上表面將樹脂層300圖案化。於設置於半導體晶片11之上表面之樹脂層300，以使設置於半導體晶片11之端部之電極墊13露出之方式形成開口。
其後，如圖7(b)所示，例如利用雷射將槽8之下之樹脂層300切斷。
如此於上表面及下表面設置有樹脂層300之最上層之半導體晶片11被自切割保護膠帶500剝離，如圖5(a)所示那般安裝至其他半導體晶片11之上。
圖8(a)~(c)係表示於半導體晶片50形成第1部分51與第2部分52之方法之模式剖視圖。
如圖8(a)所示，於晶圓W之切割區域自正面側形成槽8。於晶圓W之正面側，形成有記憶體元件200及電極墊53。槽8之深度設定為較晶圓W之厚度淺、且較要被單片化之半導體晶片50完成時之厚度深。
其次，如圖8(b)所示，對晶圓W之背面進行研磨而使晶圓W變薄。該研磨一直實施至自正面側形成之槽8自背面側露出為止。槽8到達晶圓W之正面及背面，而將晶圓W單片化為複數個半導體晶片50。
其次，如圖8(c)所示，對晶圓W背面之一部分區域進行輪研磨，而形成較設置有電極墊53之第2部分52更薄之第1部分51。
如圖5(b)所示，將經實施此種階差加工之半導體晶片50安裝於第1晶片群10之最上層之半導體晶片11之上。半導體晶片50之第1部分51接著於設置在最上層之半導體晶片11之上表面的樹脂層300。半導體晶片50之第2部分52自第1晶片群10朝第2方向(圖5(b)中之左方向)懸突。
由於在半導體晶片50之背面形成階差，故而無法於其背面貼附樹脂層300。然而，由於預先在第1晶片群10之最上層之半導體晶片11之上表面貼附有樹脂層300，故而可藉由該樹脂層300將半導體晶片50與半導體晶片11接著。
半導體晶片50之第2部分52之厚度或朝下方之突出量小於第1晶片群10之總厚度，於安裝半導體晶片50時，第2部分52不會觸碰到 配線基板100。如此防止半導體晶片50破損。
又，如圖2所示，由於半導體晶片50之第2部分52中之與第1晶片群10對向之側面52a與半導體晶片11之側面11a分開，故而於安裝半導體晶片50時，第2部分52不會觸碰到半導體晶片11。如此防止半導體晶片50及半導體晶片11破損。
之後以同樣之方式，於半導體晶片50上積層第2晶片群20之複數個半導體晶片21，於最上層之半導體晶片21上積層半導體晶片60，於半導體晶片60上積層第3晶片群30之複數個半導體晶片31，於最上層之半導體晶片31上積層半導體晶片70，且於半導體晶片70上積層第4晶片群40之複數個半導體晶片41。對半導體晶片60及半導體晶片70進行與半導體晶片50相同之階差加工。
圖9係表示實施形態之半導體裝置之另一例之與圖2相同之剖視圖。
藉由適當地控制貼附於第1晶片群10之最上層之半導體晶片11之上表面的樹脂層300之厚度、或安裝半導體晶片50時之負荷，使夾在半導體晶片50之第1部分51與半導體晶片11之間之樹脂層300向第2部分52之側面52a與半導體晶片11之側面11a之間之間隙伸出，可將樹脂層300之一部分設置於該間隙。第2部分52之側面52a經由樹脂層300而受支撐於半導體晶片11之側面11a，能夠進一步提高對電極墊53進行打線接合時之第2部分52之剛性。又，亦可使樹脂層300伸出至半導體晶片50之第2部分52之側面52a之所有區域。藉由將第2部分52之側面52a全部由樹脂層300覆蓋，則剛性進一步變高。
於圖1所示之例中，例示出4個晶片群10、20、30、40與3 個經階差加工之半導體晶片50、60、70之組合，但亦可為2個晶片群與1個經階差加工之半導體晶片之組合、3個晶片群與2個經階差加工之半導體晶片之組合、或5個以上之晶片群與4個以上之經階差加工之半導體晶片之組合。
半導體晶片11之厚度、半導體晶片21之厚度、半導體晶片31之厚度、以及半導體晶片41之厚度為大致相同之厚度。又，半導體晶片50之第1部分51之厚度、半導體晶片60之第1部分61之厚度、以及半導體晶片70之第1部分71之厚度為大致相同之厚度。
或者，亦可使半導體晶片11、21、31、41中越靠上層之半導體晶片越厚。於將所有半導體晶片積層之後，使樹脂層(DAF)300正式固化。因此，半導體晶片之積層數越多，柔軟狀態之樹脂層300之層數、即複數個樹脂層300之總厚度越厚，可能會引起積層體變得不穩定。因此，藉由使半導體晶片11、21、31、41中越靠上層之半導體晶片越厚，而能夠維持複數個半導體晶片穩定之積層狀態。
同樣地，亦可使半導體晶片50之第1部分51、半導體晶片60之第1部分61、及半導體晶片70之第1部分71中越靠上層之半導體晶片之第1部分越厚。
已對本發明之若干個實施形態進行了說明，但該等實施形態係作為示例而提出者，並非意圖限定發明之範圍。該等新穎之實施形態能以其他各種形態加以實施，且能夠於不脫離發明主旨之範圍內進行各種省略、置換、變更。該等實施形態或其變化包含於發明之範圍及主旨中，並且包含於申請專利範圍所記載之發明及其均等之範圍內。
1‧‧‧半導體裝置
5‧‧‧金屬線
10‧‧‧第1晶片群
11‧‧‧半導體晶片
13‧‧‧電極墊
20‧‧‧第2晶片群
21‧‧‧半導體晶片
23‧‧‧電極墊
30‧‧‧第3晶片群
31‧‧‧半導體晶片
33‧‧‧電極墊
40‧‧‧第4晶片群
41‧‧‧半導體晶片
43‧‧‧電極墊
50‧‧‧半導體晶片
51‧‧‧第1部分
52‧‧‧第2部分
53‧‧‧電極墊
60‧‧‧半導體晶片
61‧‧‧第1部分
62‧‧‧第2部分
63‧‧‧電極墊
70‧‧‧半導體晶片
71‧‧‧第1部分
72‧‧‧第2部分
73‧‧‧電極墊
100‧‧‧配線基板
110‧‧‧控制層
111‧‧‧控制元件
112‧‧‧樹脂層
113‧‧‧電極墊
150‧‧‧樹脂部

Claims (9)

  1. 一種半導體裝置，其具備： 配線基板； 第1晶片群，其具有於上述配線基板之上階梯狀積層之複數個第1半導體晶片； 第2晶片群，其具有於上述第1晶片群之上階梯狀積層之複數個第2半導體晶片； 第3半導體晶片，其設置於上述第1晶片群與上述第2晶片群之間； 第1金屬線，其將上述第1晶片群與上述配線基板連接； 第2金屬線，其將上述第2晶片群與上述配線基板連接；以及 第3金屬線，其將上述第3半導體晶片與上述配線基板連接；且 上述複數個第1半導體晶片各者具有：第1端部，其越下段之第1半導體晶片越較上段之第1半導體晶片更朝第1方向突出；以及第1電極墊，其設置於上述第1端部，且接合有上述第1金屬線； 上述複數個第2半導體晶片之各者具有：第2端部，其越下段之第2半導體晶片越較上段之第2半導體晶片更朝與上述第1方向相反之第2方向突出；以及第2電極墊，其設置於上述第2端部，且接合有上述第2金屬線； 上述第3半導體晶片具有：第1部分，其重疊於上述第1晶片群之上；第2部分，其較上述第1晶片群及上述第2晶片群更朝上述第2方向突出，且較上述第1部分更厚；以及第3電極墊，其設置於上述第2部分，且接合有上述第3金屬線。
  2. 如請求項1之半導體裝置，其中上述第3半導體晶片之上述第2部分之厚度，較1個上述第1半導體晶片之厚度、以及1個上述第2半導體晶片之厚度更厚。
  3. 如請求項1或2之半導體裝置，其中上述第3半導體晶片之上述第2部分之厚度較上述第1晶片群之厚度更薄，且上述第2部分未與上述配線基板相接。
  4. 如請求項1或2之半導體裝置，其中上述第3半導體晶片之上述第2部分中之與上述第1晶片群對向之側面，與上述第1晶片群之最上層之第1半導體晶片之側面分開。
  5. 如請求項1或2之半導體裝置，其進而具備樹脂層，該樹脂層設置於上述複數個第1半導體晶片之間、上述複數個第2半導體晶片之間、上述第1晶片群之最上層之第1半導體晶片與上述第3半導體晶片之間、以及上述第2晶片群之最下層之第2半導體晶片與上述第3半導體晶片之間。
  6. 如請求項5之半導體裝置，其中上述第3半導體晶片之上述第2部分中之與上述第1晶片群對向之側面，與上述最上層之第1半導體晶片之側面分開， 於上述第3半導體晶片之上述第2部分之上述側面、與上述最上層之上述第1半導體晶片之上述側面之間，設置有上述樹脂層之一部分。
  7. 如請求項1或2之半導體裝置，其進而具備樹脂部，該樹脂部設置於上述配線基板上，且覆蓋上述第1晶片群、上述第2晶片群、上述第3半導體晶片、上述第1金屬線、上述第2金屬線、以及上述第3金屬線。
  8. 如請求項1或2之半導體裝置，其中上述第3半導體晶片包含設置於上述第1部分之記憶體元件。
  9. 如請求項1或2之半導體裝置，其進而具備： 第3晶片群，其具有於上述第2晶片群之上階梯狀積層之複數個第4半導體晶片； 第5半導體晶片，其設置於上述第2晶片群與上述第3晶片群之間； 第4金屬線，其將上述第3晶片群與上述配線基板連接；以及 第5金屬線，其將上述第5半導體晶片與上述配線基板連接；且 上述複數個第4半導體晶片之各者具有：第4端部，其越下段之第4半導體晶片越較上段之第4半導體晶片更朝上述第1方向突出；以及第4電極墊，其設置於上述第4端部，且接合有上述第4金屬線； 上述第5半導體晶片具有：第3部分，其重疊於上述第2晶片群之上；第4部分，其較上述第2晶片群及上述第3晶片群更朝上述第1方向突出，且較上述第3部分更厚；以及第5電極墊，其設置於上述第4部分，且接合有上述第5金屬線。
TW107124450A 2018-03-15 2018-07-16 半導體裝置 TWI689999B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2018-048046 2018-03-15
JP2018048046A JP2019161095A (ja) 2018-03-15 2018-03-15 半導体装置

Publications (2)

Publication Number Publication Date
TW201939626A TW201939626A (zh) 2019-10-01
TWI689999B true TWI689999B (zh) 2020-04-01

Family

ID=67906098

Family Applications (1)

Application Number Title Priority Date Filing Date
TW107124450A TWI689999B (zh) 2018-03-15 2018-07-16 半導體裝置

Country Status (4)

Country Link
US (1) US10438935B1 (zh)
JP (1) JP2019161095A (zh)
CN (1) CN110289249A (zh)
TW (1) TWI689999B (zh)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180005974A1 (en) * 2016-07-04 2018-01-04 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including interconnected package on package

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5178213A (ja) 1974-12-27 1976-07-07 Matsushita Electric Ind Co Ltd Shokyohetsudo
US6376904B1 (en) * 1999-12-23 2002-04-23 Rambus Inc. Redistributed bond pads in stacked integrated circuit die package
US8242607B2 (en) * 2006-12-20 2012-08-14 Stats Chippac Ltd. Integrated circuit package system with offset stacked die and method of manufacture thereof
JP4498403B2 (ja) 2007-09-28 2010-07-07 株式会社東芝 半導体装置と半導体記憶装置
KR100886717B1 (ko) * 2007-10-16 2009-03-04 주식회사 하이닉스반도체 적층 반도체 패키지 및 이의 제조 방법
US7952183B2 (en) 2007-10-29 2011-05-31 Kabushiki Kaisha Toshiba High capacity memory with stacked layers
JP5178213B2 (ja) 2008-01-23 2013-04-10 株式会社東芝 積層型半導体装置と半導体記憶装置
JP5150243B2 (ja) 2007-12-27 2013-02-20 株式会社東芝 半導体記憶装置
US8004071B2 (en) 2007-12-27 2011-08-23 Kabushiki Kaisha Toshiba Semiconductor memory device
KR101053140B1 (ko) * 2009-04-10 2011-08-02 주식회사 하이닉스반도체 적층 반도체 패키지
KR20100121231A (ko) * 2009-05-08 2010-11-17 삼성전자주식회사 회로패턴 들뜸 현상을 억제하는 패키지 온 패키지 및 그 제조방법
KR20110133772A (ko) * 2010-06-07 2011-12-14 주식회사 하이닉스반도체 반도체 칩 및 이를 포함하는 스택 패키지
JP5665511B2 (ja) * 2010-12-10 2015-02-04 株式会社東芝 半導体装置の製造方法、製造プログラム、および製造装置
KR20140081544A (ko) * 2012-12-21 2014-07-01 에스케이하이닉스 주식회사 돌출부를 구비하는 반도체 칩, 이의 적층 패키지 및 적층 패키지의 제조 방법

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20180005974A1 (en) * 2016-07-04 2018-01-04 Sandisk Information Technology (Shanghai) Co., Ltd. Semiconductor device including interconnected package on package

Also Published As

Publication number Publication date
JP2019161095A (ja) 2019-09-19
TW201939626A (zh) 2019-10-01
US20190287952A1 (en) 2019-09-19
CN110289249A (zh) 2019-09-27
US10438935B1 (en) 2019-10-08

Similar Documents

Publication Publication Date Title
US6909168B2 (en) Resin encapsulation semiconductor device utilizing grooved leads and die pad
TWI695492B (zh) 半導體裝置及其製造方法
US7208821B2 (en) Multichip leadframe package
US7582953B2 (en) Package structure with leadframe on offset chip-stacked structure
TWI668827B (zh) 半導體裝置、半導體裝置之製造方法及半導體封裝之製造方法
JP2007201478A (ja) 半導体チップの積層
JP2011029581A5 (zh)
TW201921520A (zh) 半導體裝置之製造方法及半導體裝置
JP5557439B2 (ja) 半導体装置及びその製造方法
JP2006344898A (ja) 半導体装置及びその製造方法
TWI689999B (zh) 半導體裝置
TWI720394B (zh) 半導體裝置及其製造方法
US9768098B2 (en) Packaged semiconductor device having stacked attached chips overhanging the assembly pad
JP5361426B2 (ja) 半導体デバイス
KR20080025001A (ko) 반도체 장치의 제조 방법 및 반도체 장치
US20190088632A1 (en) Semiconductor device
JP5215980B2 (ja) 半導体装置の製造方法
US20060197203A1 (en) Die structure of package and method of manufacturing the same
TWI677960B (zh) 半導體裝置及其製造方法
US11535513B2 (en) Method of manufacturing physical quantity detection sensor, and physical quantity detection sensor
US11011505B2 (en) Semiconductor memory and manufacturing method thereof
JP2007081232A (ja) 半導体装置の製造方法
TW202213731A (zh) 半導體記憶裝置
JP5911615B2 (ja) リードフレーム
TW202022999A (zh) 半導體封裝結構