TWI658539B - 使用共晶會合互連的三維整合 - Google Patents

使用共晶會合互連的三維整合 Download PDF

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TWI658539B
TWI658539B TW105104311A TW105104311A TWI658539B TW I658539 B TWI658539 B TW I658539B TW 105104311 A TW105104311 A TW 105104311A TW 105104311 A TW105104311 A TW 105104311A TW I658539 B TWI658539 B TW I658539B
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eutectic
germanium
aluminum
feature
cmos wafer
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TW105104311A
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TW201642393A (zh
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彼得 史梅斯
莫札法 馬格搜尼亞
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美商伊凡聖斯股份有限公司
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Pressure Welding/Diffusion-Bonding (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

於此提供設備，其包含第一CMOS晶圓及第二CMOS晶圓。若干共晶會合連接第一CMOS晶圓至第二CMOS晶圓。共晶會合包含結合，其中，共晶會合溫度低於處理期間CMOS電路可以承受而不會受損之最大溫度。

Description

使用共晶會合互連的三維整合
本發明係關於使用鋁-鍺共晶會合互連的三維整合。
對於晶圓級封裝，CMOS(互補金屬氧化物半導體)共容的晶圓對晶圓接合是所需的。其用途已展現於各式各樣不同的技術中，但是，解決之道受限於大接合尺寸及高寄生電容。舉例而言，例如微凸塊等較大的接合會佔據大量的空間。結果，對於直接的晶圓對晶圓堆疊，晶圓之間連接的數目會受限。因此，需要維持堅強的晶圓級整合，而允許同時的晶圓級封裝及高密度電互連，以最佳化堆疊解決之道的功率、性能、及大小。
此處，提供裝置，其包含第一CMOS晶圓及第二CMOS晶圓。共晶會合將第一CMOS晶圓連接至第二CMOS晶圓。共晶會合包含鋁及鍺，以及，共晶會合溫度低於CMOS電路在處理期間能承受的最大溫度(例如 <430℃)。
參考下述附圖、說明、及後附的申請專利範圍，可以更佳地瞭解此處所述的概念的這些及其它特點和態樣。
102‧‧‧第一CMOS晶圓
104‧‧‧基底
106‧‧‧層間介電質中間層
108‧‧‧鈍化底層
110‧‧‧鋁間隙器
112‧‧‧鍺層
114‧‧‧金屬連接器
116‧‧‧鎢通路
120‧‧‧第二CMOS晶圓
122‧‧‧基底底層
124‧‧‧層間介電質中間層
126‧‧‧鈍化頂層
128‧‧‧鋁井
130‧‧‧鎢通路
340‧‧‧共晶會合
402‧‧‧第一CMOS晶圓
410‧‧‧間隙器
420‧‧‧第二CMOS晶圓
428‧‧‧井
440‧‧‧鋁-鍺共晶會合
441‧‧‧互連
442‧‧‧矽穿孔通路
444‧‧‧銲接凸塊
502‧‧‧第一CMOS晶圓
508‧‧‧鈍化底層
510‧‧‧間隙器
520‧‧‧第二CMOS晶圓
526‧‧‧鈍化頂層
528‧‧‧井
540‧‧‧共晶會合
602‧‧‧第一CMOS晶圓
610‧‧‧間隙器
620‧‧‧第二CMOS晶圓
628‧‧‧墊
640‧‧‧共晶會合
702‧‧‧第一CMOS晶圓
710‧‧‧第一間隙器
720‧‧‧第二CMOS晶圓
728‧‧‧第二間隙器
740‧‧‧共晶會合
圖1顯示根據本實施例的一態樣之對齊用於接合的二CMOS晶圓。
圖2顯示根據本實施例的一態樣之在鍺層與鋁井之間設有接點之二CMOS晶圓。
圖3顯示根據本實施例的一態樣之設有Al-Ge共晶會合的二CMOS晶圓。
圖4顯示根據本實施例的一態樣之具有多個互連的二CMOS晶圓。
圖5顯示根據本實施例的一態樣之以縮短的間隙接合在一起的二CMOS晶圓。
圖6顯示根據本實施例的一態樣之以間隙及表面墊接合在一起的二CMOS晶圓。
圖7顯示根據本實施例的一態樣之以二對立的間隙接合在一起的二CMOS晶圓。
圖8顯示根據本實施例的一態樣之形成二CMOS晶圓之間的共晶會合之舉例說明的流程圖。
在更詳細說明各式各樣的實施例之前，具有此技藝的 一般技術者應瞭解，由於實施例中的元件會變化，所以，實施例並非限定的。也應類似地瞭解，此處所述及/或說明的特定實施例具有元件，這些元件易於與特定實施例分開的且與數個任何其它實施例中的任何實施何選擇性地結合、或是替代此處所述的數個其它實施例中的任何實施例中的元件。
具有此技藝的一般技術者也應瞭解，此處所使用的術語是為了說明某些概念，且術語並非限定性的。除非另外指明，否則，如同此處所使用般，使用次序(例如第一、第二、第三、等等)以區別或識別元件或步驟組中的不同的元件或步驟，而未對其實施例的元件或步驟提供序列或數值的限定。舉例而言，「第一」、「第二」、及「第三」元件或步驟不必依該次序出現，且其實施例無需一定受限於三個元件或步驟。也應瞭解，除非另外指明，否則，例如「左」、「右」、「前」、「後」、「頂部」、「中間」、「底部」、「前向」、「逆向」、「順時針」、「逆時針」、「上」、「下」等標示、或是例如「上方」、「下方」、「之上」、「之下」、「垂直」、「水平」、「近端」、「遠端」等等其它類似的詞語是為了方便而使用的，而非要意指例如任何特定的固定位置、取向、或方向。替代地，這些標示係被用以反應例如相對位置、取向、或方向。也應瞭解，除非內容清楚標示，否則，單數形式的「一(a或an)」、及「定冠詞(the)」包含複數含意。
除非另外指明，否則，此處所使用的所有的技術及科學名詞與具有實施例相關技藝的一般技術者通常所瞭解的意思是相同的。
CMOS晶圓可以垂直堆疊(例如3D整合)，第一晶圓在第二晶圓的頂部上。使用TSV(「矽穿孔通路」)或微凸塊連接，CMOS晶圓可以彼此電連接。但是，TSV及微凸塊連接因大尺寸及高寄生元件(例如電阻、電容、等等)而受限。因此，於此提供的實施方式使用鋁-鍺(Al-Ge)共晶會合互連之CMOS晶圓對晶圓接合的3D整合。相對於TSV及微凸塊，小尺寸的共晶會合能夠在堆疊的CMOS之間造成具有低寄生電容之高密度互連。結果，A1-Ge共晶會合互連能夠最佳化堆疊的CMOS之功率、性能、及尺寸。
現在參考圖1，顯示根據本實施例的一態樣之對齊用於接合的二CMOS晶圓。第一CMOS晶圓102包含基底104上層、層間介電質(ILD)中間層106、及鈍化底層108。第一CMOS晶圓102也包含位於鈍化底層108之下的鋁間隙器110。鋁間隙器110包含鍺層112。
第一CMOS晶圓102的功能未限定。舉例而言，各式各樣未限定的實施例包含進階的CMOS SOC(「系統晶片」)、類比(例如SERDES(串聯器/解串器))晶片、記憶體晶片、FPGA(「現場可編程閘陣列」)、FPGA配置記憶體、LUTS(「查詢表」)、等等。
ILD中間層106含有包含例如金屬連接器114之一或 更多結構。在各式各樣的實施例中，鎢通路116使金屬連接器114彼此連接及/或連接至鋁間隙器110。須瞭解，在各式各樣的實施例中，鎢通路116可以是任何金屬、合金、或導電材料。又瞭解，在各式各樣的實施例中，互連不侷限於鋁及包含其它金屬(例如銅)。此外，本發明的實施例不侷限於包含通路(例如鎢通路116)。
鈍化底層108包含一或更多層。舉例而言，鈍化底層108包含SiO2層及SiN層。在各式各樣的實施例中，SiO2層設置於ILD中間層106與SiN層之間。須瞭解，SiO2層及SiN層僅為舉例說明，且鈍化底層108包含其它化合物、結合、或層數。
第二CMOS晶圓120包含基底底層122、ILD中間層124、鈍化頂層126。第二CMOS晶圓120也包含鈍化頂層126內的鋁井128。在本實施例中，鋁井128是在鈍化頂層126內的凹陷，其中，凹陷包含鋁部(例如鋁表面)，用於電連接至第二CMOS晶圓120之元件。在各式各樣的實施例中，藉由打開鈍化頂層126，產生鋁井128。鋁層128包含鋁部份，用於電導通至第二CMOS晶圓120的元件。如同稍後將說明般，鋁部也可由鍺取代或是由鍺塗著。
第二CMOS晶圓120的功能未限定。舉例而言，不同的非限定實施例包含進階的CMOS SOC、類比(例如SERDES)晶片、記憶體晶片、FPGA、FPGA配置記憶體、LUT、等等。
ILD中間層124含有包含例如金屬連接器128之一或更多結構。在各式各樣的實施例中，一或更多鎢通路130將金屬連接器128彼此連接(未顯示)及/或連接至鋁井128(例如，曝露的鋁表面)。須瞭解，在各式各樣的實施例中，鎢通路130可以是任何金屬、合金、或導電材料。
鈍化頂層126包含一或更多層。舉例而言，鈍化頂層126包含SiO2層及SiN層。在各式各樣的實施例中，SiO2層設置於ILD中間層124與SiN層之間。
現在參考圖2，顯示根據本實施例的一態樣，二CMOS晶圓在鍺層112與鋁井128(例如曝露的鋁表面)之間接觸。第一CMOS晶圓102與第二CMOS晶圓120相對齊，以致於設有鍺層112的鋁間隙器110接觸鋁井128。結果，鋁及鍺現在接觸並準備好共晶會合。
在本實施例中，設有鍺層112的鋁間隙器110是包含高度的第一特徵，鋁井128是包含深度的第二特徵。結果，為了第一CMOS晶圓102與第二CMOS晶圓120接合，本實施例包含具有高度(例如小於500Å)的第一特徵，所述高度大於或等於第二特徵的深度。另外的實施例包含具有高度和深度之不同組合的不同特徵。舉例而言，如下所述，晶圓包含對齊的間隙器。
雖然第一CMOS晶圓102包含具有鍺層112的鋁間隙器110，以及，第二CMOS晶圓120包含鋁井128，但是，不同的實施例可以包含其它組合。舉例而言，一實施例包含鍺間隙器及鋁井。另一實施例包含鋁間隙器及設有 鍺層的鋁井。又另外的實施例包含鍺間隙器、鍺井、及在鍺間隙器或鍺井上的鋁層。
另外的實施例包含間隙器取代井。舉例而言，第一CMOS晶圓包含設有鍺層的鋁間隙器。第二CMOS晶圓包含鋁間隙器(取代鋁井)。在另外的實例中，第一CMOS晶圓包含鍺間隙器及第二CMOS晶圓包含鋁間隙器。在仍然另外的實例中，第一CMOS晶圓包含鍺間隙器，第二CMOS晶圓包含鍺間隙器，以及，鋁層配置於任一鍺間隙器上。
因此，須瞭解，第一CMOS晶圓102與第二CMOS晶圓120之間的對齊及接觸會使任一結構的鍺特徵相接觸。如此，將第一CMOS晶圓102與第二CMOS晶圓120製備用於彼此共晶會合。如同下述參考圖式將說明般，可以調整鋁間隙器的高度以控制第一CMOS晶圓102與第二CMOS晶圓120之間的間隙距離132。舉例而言，間隙距離132從0至2000Å。但是，須瞭解，在各式各樣的實施例中，間隙距離132未限定且可以大幅地超過2000Å。
現在參考圖3，顯示根據本實施例的一態樣，設有Al-Ge共晶會合340之二CMOS晶圓。在會合處理期間，施加熱以使溫度上升至至少共晶熔點及形成Al-Ge共晶會合。須瞭解，共晶熔點低於鋁的熔點及低於鍺的熔點。此外，施加壓力至第一CMOS晶圓102及第二CMOS晶圓120,以使鋁及鍺特徵一起受壓。在本實施例中，將具有 鍺層112的鋁間隙器110壓至鋁井128。
施加足夠的壓力以助於共晶會合處理，但是，太多的壓力會使得熔化的Al-Ge溢出井128且至鈍化頂層126。因此，控制壓力以使Al-Ge共晶會合340維持實質上在第一CMOS晶圓102及第二CMOS晶圓120之間的接點。舉例而言，在本實施例中，Al-Ge共晶會合340侷限於鋁井128。在另外的實例中，共晶會合340的寬度比第一特徵(例如鋁間隙器110)的寬度還窄且比第二特徵(例如鋁井128)的寬度還窄。
各式各樣的實施例可以使用不同的方法以達到Al-Ge共晶熔點。舉例而言，在某些實施例中，溫度以步進方式升高至共晶熔點之下，使表面接觸，然後，溫度再度升度。須瞭解，上述實例僅為說明，不應是限定的。
在熔化之後，Al-Ge共晶會合340形成於第一CMOS晶圓102上的第一特徵與第二CMOS晶圓120上的第二特徵。如同先前所述般，第一及第二特徵之某些非限定的實例包含：鋁間隙器、鍺間隙器、設有鍺層的鋁間隙器、設有鋁層的鍺間隙器、鋁井、鍺井、設有鍺層的鋁井、設有鋁層的鍺井、等等。結果，Al-Ge共晶會合340包含鋁及鍺特徵的任何結合。
另外的實施例也使用鋁及鍺以外的元素。可以使用形成共晶會合的任何元素。舉例而言，CMOS晶圓可以與黃金特徵及矽特徵形成共晶會合。在另外的實例中，CMOS晶圓可以與銅特徵及錫特徵形成共晶會合。在各式各樣的 實例中，CMOS晶圓包含多種用於在二CMOS晶圓之間形成不同的共晶互連之不同的共晶組合。在某些實施例中，共晶會合溫度低於處理期間CMOS電路可以承受而不受損之最大溫度(例如<430℃)。
現在參考圖4，顯示根據本實施例的一特點，設有多個互連441的二CMOS晶圓。在本實施例中，互連441包含間隙器410、Al-Ge共晶會合440、及井428。各式各樣的實施例包含各式各樣的結構及形狀之互連，這些互連經由Al-Ge共晶會合而彼此電互連。
第一CMOS晶圓402及第二CMOS晶圓420藉由眾多Al-Ge共晶會合440而接合在一起。此外，TSV 442及銲接凸塊444經由第二CMOS晶圓420而電連接至Al-Ge共晶會合440。
須瞭解，在各式各樣的實施例中，CMOS晶圓包含機械缺陷。舉例而言，CMOS晶圓不是平坦的且包含捲曲、不均勻性、及需要被穿透的原生氧化物。因此，在各式各樣的實施例中，施加足以克服一或更多CMOS晶圓的機械缺陷之力量。
舉例而言，在捲曲的情形中，一或更多間隙器410及井428可以在其它間隙器410和井428彼此接觸，藉以防止其它間隙器410和井428接觸。因此，施加附加的壓力(例如力)至第一CMOS晶圓402及第二CMOS晶圓420以使所有的間隙器410及井428接觸。但是，壓力也會被控制以減輕過度散佈Al-Ge共晶會合440(如先前所述 般)。
象徵性地顯示TSV 442、銲接凸塊444、及互連441。但是，須瞭解，互連441遠小於TSV 442及銲接凸塊444。結果，互連441的密度遠大於TSV或銲接凸塊的可能密度。如同所示，多個互連441適配於單一TSV或微凸塊區域內。舉例而言，在一非限定的實施例中，TSV或微凸塊範圍在數十微米中(例如從10至50微米或更多)，而共晶互連範圍從1至2微米，甚至是次微米。各式各樣的實施例也包含不同互連的組合。舉例而言，CMOS晶圓包含任何組合互連(例如共晶會合、TSV、微凸塊、線接合、等等)。
互連441的小尺寸及高密度具有很多優點。舉例而言，互連441的寄生電容從TSV或微凸塊大幅減少。此外，互連441的小尺寸能夠造成堆疊晶粒之新整合方法(例如，多晶粒之間的IP區塊與互連的分割以使堆疊解決之道的功率、性能、及尺寸最佳化)。在各式各樣的實施例中，異質整合使用成本最佳化技術而能夠分割互連與IP(「智慧財產權」)區塊。舉例而言，14nm的微處理器SOC可以接合至65nm的記憶體、40nm的SERDES、或是28nm的SERDES。在另外的實例中，FPGA配置記憶體區塊可以與LUT分離。
現在參考圖5，顯示根據本實施例的態樣之以縮短的間隙器接合在一起的二CMOS晶圓。在本實施例中，選取間隙器510的高度以在共晶會合後將第一CMOS晶圓502 與第二CMOS晶圓520之間的間隙高度532降至零。因此，在形成共晶會合540之後，第一CMOS晶圓502與第二CMOS晶圓520的面對層彼此接觸。在本實施例中，第一CMOS晶圓502的鈍化底層508接觸第二CMOS晶圓520的鈍化頂部層526。但是，須瞭解，其它實施例包含彼此接觸之二CMOS晶圓的不同層。
可以選取間隙器510的高度以達成第一CMOS晶圓502與第二CMOS晶圓520之間的預定間隙高度532。在一實施例中，間隙器510的高度可以實質地增加(未顯示)以在第一CMOS晶圓502與第二CMOS晶圓520之間產生更大的間隙高度532。在另一實施例中，間隙器510的高度僅稍微增加(未顯示)以在第一CMOS晶圓502與第二CMOS晶圓520之間產生很小的間隙高度532。因此，間隙器510的高度可以調整以取得所需的間隙高度532。
此外，可以選取井528的深度以達成第一CMOS晶圓502與第二CMOS晶圓520之間預定的間隙高度532。在一實施例中，井528的深度可以實質地增加(未顯示)以在第一CMOS晶圓502與第二CMOS晶圓520之間產生更大的間隙高度532。在另一實施例中，井528的深度僅稍微降低(未顯示)以在第一CMOS晶圓502與第二CMOS晶圓520之間產生很小的間隙高度532。因此，井528的深度可以調整以產生所需的間隙高度532。
現在參考圖6，顯示根據本實施例的一態樣之以間隙 器及表面墊接合在一起的二CMOS晶圓。第一CMOS晶圓602包含間隙器610。第二CMOS晶圓620包含墊628或是與第二CMOS晶圓620的表面連續的(例如平坦的)表面。共晶會合640經由間隙器610及墊628而將第一CMOS晶圓602互連至第二CMOS晶圓620。在本實施例中，如先前有關間隙器的高度變化之說明所述般，間隙高度632由間隙器610的長度決定。
現在參考圖7，顯示根據本實施例的一態樣之以二相對立的間隙器接合在一起的二CMOS晶圓。第一CMOS晶圓702包含第一間隙器710。第二CMOS晶圓720包含第二間隙器728。共晶會合740經由第一間隙器710及第二間隙器728而將第一CMOS晶圓702互連至第二CMOS晶圓720。在本實施例中，如同上述有關間隙器高度的變化之說明所述般，間隙高度732由第一間隙器710的長度及第二間隙器728的長度決定。
圖8顯示根據本實施例的一態樣之二CMOS晶圓之間形成共晶會合的舉例說明的流程圖。在方塊802，在第一CMOS晶圓上的鍺特徵與在第二CMOS晶圓上的鋁特徵相對齊。舉例而言，在圖1中，第一CMOS晶圓的間隙器與第二CMOS晶圓的井相對齊。間隙器是設有面對鈍化層內的鋁井之鍺層的鋁。
在方塊804，使鋁特徵及鍺特徵一起受壓。舉例而言，在圖2中，第一CMOS晶圓與第二CMOS晶圓一起受壓，以致於設有鍺層的鋁間隙器接觸鋁井。
在某些實施例中，鍺特徵是在鋁間隙器上的鍺層。舉例而言，在圖1中，第一CMOS晶圓也包含位於鈍化底層之下的鋁間隙器，以及，鋁間隙器包含鍺層。在其它實施例中，鍺特徵是鍺間隙器。舉例而言，在圖2中，雖然第一CMOS晶圓包含設有鍺層的鋁間隙器，以及，第二CMOS晶圓包含鋁井，但是，各式各樣的實施例包含其它組合。因此，一實施例包含鍺間隙器及鋁井。另一實施例包含鋁間隙器及設有鍺層的鋁井。又另外的實施例包含鍺間隙器、鍺井、及在鍺間隙器或鍺井中任一上的鍺層。
在某些實施例中，鋁特徵是在鈍化層內的井。舉例而言，在圖1中，第二CMOS晶圓也包含在鈍化頂層內的鋁井。在某些實施例中，共晶會合當熔化時會被侷限於井。舉例而言，在圖3中，施加充份的壓力以助於共晶會合處理，但是，太多的壓力會造成熔化的Al-Ge溢出井及至鈍化層上。因此，控制壓力以將Al-Ge共晶會合實質上維持至第一CMOS晶圓與第二CMOS晶圓之間的接觸點，藉以將共晶會合侷限於鋁井。
在方塊806，形成共晶會合，連接鋁特徵至鍺特徵，其中，共晶會合具有低於鋁的熔點及鍺的熔點之熔點。舉例而言，在圖3中，施加熱及壓力以使溫度上升到至少共晶熔點及形成Al-Ge會合。
在某些實施例中，鋁特徵及鍺特徵加熱至在共晶會合的熔點之下的點，以及，在加壓之後，將鋁特徵及鍺特徵加熱到至少共晶會合的熔點。舉例而言，在圖3中，以逐 步方式，升高溫度至在共晶熔點之下，以及，使表面接觸，然後再度升高溫度。
在某些實施例中，在第一CMOS晶圓上附加的多個鍺特徵會與第二CMOS晶圓上多個附加的鋁特徵相對齊，其中，在施壓之前，在多個附加的鋁特徵與多個附加的鍺特徵之間距離是不一致的，以及，其中，另外在施壓之後，多個附加的鋁特徵接觸多個附加的鍺特徵。舉例而言，在圖4中，CMOS晶圓並非總是完美的平坦。結果，一或更多間隙器及井會在其它間隙器與井之前彼此接觸，藉以防止其它間隙器及井接觸。因此，施加附加的壓力至第一CMOS晶圓及第二CMOS晶圓以使所有的間隙器及井接觸及形成Al-Ge共晶會合。
雖然藉由特定實例來說明及/或顯示實施例，且雖然相當詳細地說明這些實施例及/或實例，但是，申請人無意將實施例的範圍限制或以任何方式限定於這些細節。具有實施例有關的技藝之一般技術者容易知道實施例的其它的適應及/或修改，且依其較廣的態樣，實施例涵蓋這些修改及/或適應。因此，在不悖離此處所述的概念之下，可以對上述實施例及/或實例作修改。上述說明的實施及其它實施是在後附的申請專利範圍之範圍內。

Claims (16)

  1. 一種使用共晶會合互連的設備，包括：第一CMOS晶圓；第二CMOS晶圓；共晶會合，連接該第一CMOS晶圓至該第二CMOS晶圓，其中，該共晶會合包含鋁及鍺，以及，該共晶會合具有低於鋁的熔點及鍺的熔點的熔點，其中，該第一CMOS晶圓包含鋁間隙器或鍺間隙器以及在該鋁間隙器或該鍺間隙器上的鍺層，以及該共晶會合包含該鋁間隙器或該鍺間隙器，其中，該共晶會合的寬度比該鋁間隙器或該鍺間隙器的寬度還窄。
  2. 如申請專利範圍第1項之設備，又包括在該第二CMOS晶圓的表面內的凹部，其中，該凹部包含鋁表面，以及該共晶會合包含該鋁表面。
  3. 如申請專利範圍第1項之設備，又包括在該第二CMOS晶圓的表面內的凹部，其中，該凹部包含鍺表面，以及該共晶會合包含該鍺表面。
  4. 如申請專利範圍第1項之設備，又包括眾多共晶會合，連接該第一CMOS晶圓至該第二CMOS晶圓。
  5. 如申請專利範圍第1項之設備，又包括在該第一CMOS晶圓與該第二CMOS晶圓之間的間隙器高度，其中，該間隙器高度是在0與2000Å之間。
  6. 一種使用共晶會合互連的設備，包括：在第一CMOS晶圓上的第一特徵；在第二CMOS晶圓上的第二特徵；共晶會合，連接該第一特徵至該第二特徵，其中，該共晶會合具有低於該第一特徵的熔點及該第二特徵的熔點的熔點，其中，該第一特徵包含鋁，其中，該共晶會合的寬度比該第一特徵的寬度還窄。
  7. 如申請專利範圍第6項之設備，其中，該第二特徵包含鍺。
  8. 如申請專利範圍第6項之設備，其中，該第一特徵是包含高度的間隙器，該第二特徵是包含深度的凹部，以及，該高度大於該深度。
  9. 如申請專利範圍第6項之設備，其中，該共晶會合包含熔在一起的該第一特徵的部份及該第二特徵的部份。
  10. 如申請專利範圍第6項之設備，其中，該共晶會合的寬度比該第二特徵的寬度還窄。
  11. 如申請專利範圍第6項之設備，其中，該第一特徵包含小於500Å的高度。
  12. 一種用於使用共晶會合互連的設備之方法，包括：對齊第一CMOS晶圓上的鍺特徵與第二CMOS晶圓上的鋁特徵；使該鋁特徵與該鍺特徵一起受壓；形成連接該鋁特徵至該鍺特徵的共晶會合，其中，該共晶會合具有低於該鋁的熔點及該鍺的熔點的熔點；將該第一CMOS晶圓上眾多附加的鍺特徵與該第二CMOS晶圓上眾多附加的鋁特徵相對齊，其中，在該施壓之前，在該眾多附加的鋁特徵中的一些與該眾多附加的鍺特徵中的一些之間的距離是不一致的，以及，在該施壓之後，該眾多附加的鋁特徵接觸該眾多附加的鍺特徵，其中，該共晶會合的寬度比該鍺特徵的寬度還窄。
  13. 如申請專利範圍第12項之方法，又包括：將該鋁特徵及該鍺特徵加熱至在該共晶會合的熔點之下的點；以及，在該施壓之後，將該鋁特徵及該鍺特徵加熱到至少該共晶會合的熔點。
  14. 如申請專利範圍第12項之方法，其中，該鍺特徵是鍺間隙器。
  15. 如申請專利範圍第12項之方法，其中，該鋁特徵是在鈍化層內的井。
  16. 如申請專利範圍第15項之方法，又包括：當熔化時，將該共晶會合侷限於該井。
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