TWI629491B - Bonding area impedance detection method and bonding area impedance detection system - Google Patents
Bonding area impedance detection method and bonding area impedance detection system Download PDFInfo
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Abstract
一種接合處阻抗檢測之方法及接合處阻抗檢測系統。接合處阻抗檢測方法係確認電路迴路內連接之接合處是否具有不良區域。方法包括以下步驟：提供用以接合二電路元件之接合處，其中接合處具有複數接腳，該些接腳耦接二電路元件；電性連接該些接腳之至少二接腳以形成電路迴路，其中電路迴路具有第一量測接點及第二量測接點，第一量測接點、至少二接腳及第二量測接點之間係彼此串聯連接；透過第一量測接點及第二量測接點測量電路迴路之迴路阻抗值；判斷迴路阻抗值是否超過參考阻抗值；以及若是，判定電路迴路內連接之接合處具有不良區域。A joint impedance detection method and joint impedance detection system. The joint impedance detection method is to check whether there is a defective area in the joints connected in the circuit loop. The method includes the following steps: providing a joint for joining two circuit elements, wherein the joint has a plurality of pins, the pins are coupled to the two circuit elements; and at least two pins of the pins are electrically connected to form a circuit loop. The circuit loop has a first measurement contact and a second measurement contact, and the first measurement contact, at least two pins, and the second measurement contact are connected in series with each other; through the first measurement contact The point and the second measurement contact measure the circuit impedance value of the circuit circuit; determine whether the circuit impedance value exceeds the reference impedance value; and if so, determine that the joint in the circuit circuit connection has a bad area.
Description
本發明係關於一種接合處阻抗檢測之方法及其系統，特別是一種可以有效判斷接合處是否具有接合不良區域的接合處阻抗檢測之方法及其系統。The invention relates to a method and system for detecting impedance of a joint, and more particularly, to a method and system for detecting impedance of a joint that can effectively determine whether the joint has a poor joint area.
隨著科技的進步，現今的電路的製程已經發展出一種利用異方性導電膠(Anisotropic Conductive Film，ACF)進行貼合的製程。異方性導電膠是指在兩基材之間貼合的特殊材料，其特點在於利用導電粒子連接晶片與基板兩者之間的電極，讓電流只能從黏合方向導通流動，但又同時能避免相鄰兩電極間導通短路。因此於先前技術中利用異方性導電膠通過預壓將電路晶片、軟式排線或集成電路等接合(Bonding)在LCD玻璃基板上已經是常見的技術。With the advancement of science and technology, the current circuit manufacturing process has developed a bonding process using an anisotropic conductive adhesive (ACF). Anisotropic conductive adhesive refers to a special material bonded between two substrates. It is characterized by the use of conductive particles to connect the electrodes between the wafer and the substrate, so that current can flow only from the bonding direction, but at the same time it can Avoid conducting shorts between adjacent electrodes. Therefore, in the prior art, using anisotropic conductive adhesive to bond circuit wafers, flexible cables, or integrated circuits on LCD glass substrates by pre-pressing has been a common technique.
然而於先前技術中對於接合品質的檢測方式通常是用顯微鏡觀察導電粒子在接合後的破裂狀況以及有效壓著的導電粒子顆數是否足夠。例如會顯示如圖1的示意圖，圖1係先前技術中之接合處之示意圖。接合處90可能會觀察出優良區域91及不良區域92。但是只有當基板為透明材質(例如玻璃)時才可以用顯微鏡觀察。如果壓著基板非透明材質(例如印刷電路板)，顯微鏡就無法使用。再者，用顯微鏡觀察導電粒子破裂狀況的方式無法量化，只能以比較方式來判定。所以容易造成誤判，導致不良品流出。However, in the prior art, the method for detecting the bonding quality is usually to observe the fracture condition of the conductive particles after bonding and whether the number of the conductive particles that are effectively pressed is sufficient with a microscope. For example, a schematic diagram as shown in FIG. 1 is displayed, which is a schematic diagram of a joint in the prior art. A good area 91 and a bad area 92 may be observed at the joint 90. But only when the substrate is made of transparent material (such as glass) can it be observed with a microscope. If the substrate is pressed against a non-transparent material (such as a printed circuit board), the microscope cannot be used. Furthermore, the method of observing the rupture of conductive particles with a microscope cannot be quantified, and can only be determined by comparison. Therefore, it is easy to cause misjudgment and cause defective products to flow out.
因此，有必要發明一種新的接合處阻抗檢測之方法及其系統，以解決先前技術的缺失。Therefore, it is necessary to invent a new method and system for detecting impedance of a joint to solve the deficiency of the prior art.
本發明之主要目的係在於提供一種接合處阻抗檢測方法，其能夠有效判斷接合處是否具有接合不良區域。The main object of the present invention is to provide a method for detecting the impedance of a joint, which can effectively determine whether a joint has a poor joint area.
本發明之另一主要目的係在於提供一種使用上述方法的接合處阻抗檢測之系統。Another main object of the present invention is to provide a system for joint impedance detection using the above method.
為達成上述之目的，本發明之接合處阻抗檢測方法係用以確認電路迴路內連接之接合處是否具有不良區域。方法包括以下步驟：提供用以接合二電路元件之接合處，其中接合處具有複數接腳，該些接腳耦接二電路元件；電性連接該些接腳之至少二接腳以形成電路迴路，其中電路迴路具有第一量測接點及第二量測接點，第一量測接點、至少二接腳及第二量測接點之間係彼此串聯連接；透過第一量測接點及第二量測接點測量電路迴路之迴路阻抗值；判斷迴路阻抗值是否超過參考阻抗值；以及若是，判定電路迴路內連接之接合處具有不良區域。In order to achieve the above object, the joint impedance detection method of the present invention is used to confirm whether the joints connected in the circuit loop have a defective area. The method includes the following steps: providing a joint for joining two circuit elements, wherein the joint has a plurality of pins, the pins are coupled to the two circuit elements; and at least two pins of the pins are electrically connected to form a circuit loop. The circuit loop has a first measurement contact and a second measurement contact, and the first measurement contact, at least two pins, and the second measurement contact are connected in series with each other; through the first measurement contact The point and the second measurement contact measure the circuit impedance value of the circuit circuit; determine whether the circuit impedance value exceeds the reference impedance value; and if so, determine that the joint in the circuit circuit connection has a bad area.
本發明之接合處阻抗檢測系統包括：至少一接合處、電路迴路、量測模組以及處理模組。接合處用以接合二電路元件，且接合處包括複數接腳，該些接腳耦接二電路元件；電路迴路係由該些接腳之至少二接腳電性連接所形成，電路迴路具有第一量測接點及第二量測接點且電性連接至少二接腳，第一量測接點、至少二接腳及第二量測接點之間係彼此串聯連接；量測模組電性連接第一測量點及第二測量點以測量電路迴路之迴路阻抗值。處理模組電性連接量測模組，處理模組用以判斷迴路阻抗值是否超過參考阻抗值；若是，則判定電路迴路內連接之至少一接合處具有不良區域。The joint impedance detection system of the present invention includes: at least one joint, a circuit loop, a measurement module, and a processing module. The joint is used to join two circuit elements, and the joint includes a plurality of pins, the pins are coupled to the two circuit elements; the circuit loop is formed by electrically connecting at least two of the pins, and the circuit loop has a first A measuring contact and a second measuring contact are electrically connected to at least two pins, and the first measuring contact, the at least two pins and the second measuring contact are connected in series with each other; the measuring module The first measurement point and the second measurement point are electrically connected to measure the loop impedance value of the circuit loop. The processing module is electrically connected to the measurement module, and the processing module is used to determine whether the loop impedance value exceeds the reference impedance value; if so, it is determined that at least one joint connected in the circuit loop has a defective area.
藉由上述本發明提供之接合處阻抗檢測方法及接合處阻抗檢測系統，透過電性連接接合處的該些接腳之至少二接腳以形成電路迴路，並測量電路迴路之一迴路阻抗值以判斷迴路阻抗值是否超過一參考阻抗值，以藉此檢測二電路元件之間的接合處的接合品質。By using the joint impedance detection method and the joint impedance detection system provided by the present invention, a circuit loop is formed by electrically connecting at least two pins of the pins at the joint, and measuring a loop impedance value of one of the circuit loops to It is determined whether the loop impedance value exceeds a reference impedance value, thereby detecting the joint quality of the joint between the two circuit elements.
為能讓 貴審查委員能更瞭解本發明之技術內容，特舉較佳具體實施例說明如下。In order to make your reviewing committee better understand the technical content of the present invention, specific preferred embodiments are described below.
以下請先參考圖2係本發明之接合處阻抗檢測系統之第一實施例之架構示意圖。Please refer to FIG. 2 below for a schematic diagram of the first embodiment of the joint impedance detection system of the present invention.
於本發明之第一實施例中，接合處阻抗檢測系統1用以判斷電路迴路C1連接之接合處51是否具有一不良區域。接合處阻抗檢測系統1包括接合處51、電路迴路C1、量測模組20及處理模組30。接合處51用以接合二電路元件，且接合處51包含複數接腳41，該些接腳41耦接該二電路元件。電路迴路C1是由該些接腳41中的至少二接腳41電性連接所形成。電路迴路C1具有一第一量測接點11及一第二量測接點12，第一量測接點11、至少二接腳41及第二量測接點12之間係彼此串聯連接。於本發明之第一實施例中，二電路元件包括基板61及電路晶片62，接合處51係用以接合基板61及電路晶片62，例如利用異方性導電膠(Anisotropic Conductive Film，ACF)進行接合，但本發明並不限於此。電路迴路C1可以佈線的方式電性連接於耦接基板61及電路晶片62之該些接腳41中的至少二接腳41。In the first embodiment of the present invention, the joint impedance detection system 1 is used to determine whether the joint 51 connected to the circuit circuit C1 has a defective area. The joint impedance detection system 1 includes a joint 51, a circuit loop C1, a measurement module 20, and a processing module 30. The joint 51 is used for joining two circuit elements, and the joint 51 includes a plurality of pins 41, and the pins 41 are coupled to the two circuit elements. The circuit loop C1 is formed by electrically connecting at least two pins 41 of the pins 41. The circuit loop C1 has a first measurement contact 11 and a second measurement contact 12. The first measurement contact 11, at least two pins 41 and the second measurement contact 12 are connected in series with each other. In the first embodiment of the present invention, the two circuit elements include a substrate 61 and a circuit wafer 62, and the joint 51 is used to join the substrate 61 and the circuit wafer 62, for example, using an anisotropic conductive film (ACF). Bonded, but the invention is not limited to this. The circuit circuit C1 can be electrically connected to at least two pins 41 of the pins 41 of the coupling substrate 61 and the circuit chip 62 in a wiring manner.
於本發明之第一實施例中，各個電路元件包括一子電路迴路（圖未示出），而部份的接腳41可包含一連通部411，於本發明之第一實施例中，接腳41的連通部411設置於接腳41的中間位置，電路迴路C1能夠經由接腳41的連通部411電性連接電路元件（即基板61或電路晶片62）之子電路迴路。請參圖2，於本發明之第一實施例中，第一量測接點11係連接接腳41a，電路迴路C1係由接腳41a的連通部411連接到基板61的子電路迴路，再經由基板61的子電路迴路連接到接腳41a，並由接腳41a連接到接腳41b、41c之佈線設計所形成，而第二量測接點12係連接接腳41c，其中接腳41b、41c係透過電路晶片62的子電路迴路相互電性連接。也就是說，第一量測接點11及第二量測接點12與耦接基板61及電路晶片62的接合處51的接腳41a、接腳41b及接腳41c之間係彼此串聯連接。 In the first embodiment of the present invention, each circuit element includes a sub-circuit loop (not shown), and some of the pins 41 may include a communication portion 411. In the first embodiment of the present invention, The communication portion 411 of the pin 41 is disposed at an intermediate position of the pin 41, and the circuit circuit C1 can be electrically connected to a sub-circuit circuit of a circuit element (ie, the substrate 61 or the circuit chip 62) through the communication portion 411 of the pin 41. Please refer to FIG. 2. In the first embodiment of the present invention, the first measurement contact 11 is connected to the pin 41a, and the circuit loop C1 is connected to the sub-circuit loop of the substrate 61 by the connecting portion 411 of the pin 41a. It is connected to the pin 41a through the sub-circuit loop of the substrate 61, and is formed by the wiring design of the pin 41a connected to the pins 41b, 41c. The second measurement contact 12 is the connection pin 41c, of which the pins 41b, 41c is electrically connected to each other through the sub-circuit loops of the circuit chip 62. That is, the pins 41a, 41b, and 41c of the first measurement contact 11 and the second measurement contact 12 and the joint 51 of the coupling substrate 61 and the circuit chip 62 are connected in series with each other. .
量測模組20係電性連接第一量測接點11及第二量測接點12，量測模組20用以測量電路迴路C1之一迴路阻抗值。需注意的是，第一量測接點11及第二量測接點12之間相隔一特定數量之接腳41，例如相隔5至10個接腳，本發明並不限於此。但當第一量測接點11及第二量測接點12之間相隔的接腳數過多時，其測量得到的阻抗值就會有較大的誤差。 The measurement module 20 is electrically connected to the first measurement contact 11 and the second measurement contact 12. The measurement module 20 is used to measure a loop impedance value of a circuit loop C1. It should be noted that a specific number of pins 41 are separated between the first measurement contact 11 and the second measurement contact 12, for example, 5 to 10 pins are separated, and the present invention is not limited thereto. However, when there are too many pins separated between the first measurement contact 11 and the second measurement contact 12, the impedance value obtained by the measurement will have a large error.
處理模組30係電性連接該量測模組20，處理模組30用以判斷迴路阻抗值是否超過一參考阻抗值，如此處理模組能夠判斷接合處的接合品質，於本實施例中參考阻抗值為一基礎阻抗值之三倍，其中基礎阻抗值為在接合處不具有不良區域的情況下電路迴路應測得之阻抗值，例如在接合處不具有不良區域的情況下，量測模組20所量測得電路迴路C1的迴路阻抗值應不超過10歐姆，其中10歐姆作為基礎阻抗值，但在接合處具有不良區域的情況下，量測模組20所量測得電路迴路C1的迴路阻抗值卻超過30歐姆，即迴路阻抗值超過基礎阻抗值之三倍。如此即可判定電路迴路C1連接的接合處51具有該不良區域，才會讓迴路阻抗值大幅增加。因此若迴路阻抗值超過基礎阻抗值之三倍，則處理模組30判定該接合處51具有接合不良的區域（即所述不良區域）。The processing module 30 is electrically connected to the measurement module 20, and the processing module 30 is used to determine whether the loop impedance value exceeds a reference impedance value. In this way, the processing module can determine the joint quality of the joint. Refer to this embodiment for reference. The impedance value is three times the basic impedance value, where the basic impedance value is the impedance value that should be measured in the case where the joint has no bad area, for example, if the joint has no bad area, measure the mode The circuit impedance value of the circuit circuit C1 measured by the group 20 should not exceed 10 ohms, of which 10 ohms is used as the basic impedance value, but if the joint has a bad area, the circuit circuit C1 measured by the measurement module 20 The loop impedance value exceeds 30 ohms, that is, the loop impedance value exceeds three times the basic impedance value. In this way, it can be determined that the joint 51 connected to the circuit circuit C1 has the defective area, and the circuit impedance value can be greatly increased. Therefore, if the loop impedance value exceeds three times the basic impedance value, the processing module 30 determines that the joint 51 has a poorly bonded area (ie, the bad area).
接著，請參考圖3係本發明之接合處阻抗檢測方法之步驟流程圖。此處需注意的是，本發明之接合處阻抗檢測方法可搭配上述接合處阻抗檢測系統1為例說明，但本發明之接合處阻抗檢測方法並不以使用在上述相同結構的接合處阻抗檢測系統1為限。Next, please refer to FIG. 3 which is a flowchart of steps of the method for detecting impedance of a joint according to the present invention. It should be noted here that the joint impedance detection method of the present invention can be described with the joint impedance detection system 1 as an example, but the joint impedance detection method of the present invention does not use the joint impedance detection of the same structure as described above. System 1 is limited.
首先進行步驟301：提供用以接合二電路元件之一接合處，其中接合處包括複數接腳，該些接腳耦接二電路元件。First, step 301 is performed: a joint is provided for joining one of the two circuit elements, wherein the joint includes a plurality of pins, and the pins are coupled to the two circuit elements.
接著進行步驟302：電性連接該些接腳之至少二接腳以形成一電路迴路，其中電路迴路具有一第一量測接點及一第二量測接點，第一量測接點、至少二接腳及第二量測接點之間係彼此串聯連接。Then proceed to step 302: electrically connect at least two of the pins to form a circuit loop, wherein the circuit loop has a first measurement contact and a second measurement contact, the first measurement contact, The at least two pins and the second measurement contact are connected in series with each other.
再進行步驟303：透過第一量測接點及第二量測接點測量電路迴路之一迴路阻抗值。Then, step 303 is performed: a loop impedance value of a circuit loop is measured through the first measurement contact and the second measurement contact.
接著進行步驟304：判斷迴路阻抗值是否超過一參考阻抗值。Then proceed to step 304: determine whether the loop impedance value exceeds a reference impedance value.
最後，若迴路阻抗值超過一參考阻抗值，則進行步驟305：判定電路迴路連接之接合處具有一不良區域，反之，若迴路阻抗值未超過一參考阻抗值，則進行步驟306：判定電路迴路連接之接合處不具有一不良區域。Finally, if the loop impedance value exceeds a reference impedance value, proceed to step 305: determine that the junction of the circuit loop connection has a bad area; otherwise, if the loop impedance value does not exceed a reference impedance value, proceed to step 306: determine the circuit loop The joint joint does not have a defective area.
此處需注意的是，本發明之接合處阻抗檢測方法並不以上述之步驟次序為限，只要能達成本發明之目的，上述之步驟次序亦可加以改變。It should be noted here that the joint impedance detection method of the present invention is not limited to the above-mentioned sequence of steps. As long as the purpose of the invention is achieved, the above-mentioned sequence of steps may be changed.
本發明可以適用於多種不同的電路迴路。接著請參考圖4A係本發明之接合處阻抗檢測系統之第二實施例之架構示意圖，其中相同或相似元件使用相同或相似標號。The invention can be applied to many different circuit circuits. 4A is a schematic structural diagram of a second embodiment of the joint impedance detection system of the present invention, in which the same or similar components use the same or similar reference numerals.
於本發明之第二實施例中，二電路元件包括基板61及軟性電路板63，各個電路元件（即基板61或軟性電路板63）包括一子電路迴路（圖未示出），接合處阻抗檢測系統2包括接合處52、電路迴路C2、量測模組20及處理模組30。接合處阻抗檢測系統2係用以判斷電路迴路C2連接之接合處52是否具有一不良區域。接合處52係用以接合基板61及軟性電路板63，且接合處52包含複數接腳42，複數之接腳42耦接基板61及軟性電路板63，電路迴路C2是由該些接腳42中的至少二接腳42電性連接所形成。電路迴路C2具有一第一量測接點11及一第二量測接點12且包含電路迴路C2a、C2b、C2c，電路迴路C2a、C2b、C2c電性連接該些接腳42中的至少二接腳42，其中第一量測接點11、至少二接腳42及第二量測接點12之間係彼此串聯連接，且電路迴路C2可以佈線的方式電性連接於耦接基板61及軟性電路板63之該些接腳42中的至少二接腳42。In the second embodiment of the present invention, the two circuit elements include a substrate 61 and a flexible circuit board 63. Each circuit element (ie, the substrate 61 or the flexible circuit board 63) includes a sub-circuit loop (not shown in the figure), and the junction impedance is The detection system 2 includes a joint 52, a circuit circuit C2, a measurement module 20, and a processing module 30. The joint impedance detection system 2 is used to determine whether the joint 52 connected to the circuit circuit C2 has a defective area. The joint 52 is used to join the substrate 61 and the flexible circuit board 63, and the joint 52 includes a plurality of pins 42. The plurality of pins 42 are coupled to the substrate 61 and the flexible circuit board 63. The circuit circuit C2 is composed of these pins 42. At least two of the pins 42 are electrically connected. The circuit loop C2 has a first measurement contact 11 and a second measurement contact 12 and includes a circuit loop C2a, C2b, C2c. The circuit loop C2a, C2b, C2c is electrically connected to at least two of the pins 42. Pin 42, wherein the first measuring contact 11, the at least two pins 42 and the second measuring contact 12 are connected in series with each other, and the circuit loop C2 can be electrically connected to the coupling substrate 61 and At least two pins 42 of the pins 42 of the flexible circuit board 63.
於本發明之第二實施例中，部分的接腳42可包含一連通部421，其中接腳42a、42b、42c、42d分別包含一連通部421，且連通部421設置於接腳42a、42b、42c、42d的末端位置，電路迴路C2能夠經由接腳42a、42b、42c、42d的連通部421電性連接電路元件（即基板61或軟性電路板63）之子電路迴路。In the second embodiment of the present invention, part of the pins 42 may include a communication portion 421, wherein the pins 42a, 42b, 42c, and 42d respectively include a communication portion 421, and the communication portion 421 is disposed on the pins 42a, 42b. At the end positions of, 42c, 42d, the circuit loop C2 can be electrically connected to the sub-circuit loop of the circuit element (ie, the substrate 61 or the flexible circuit board 63) via the connecting portion 421 of the pins 42a, 42b, 42c, and 42d.
請參圖4A，於本發明之第二實施例中，第一量測接點11係連接接腳42a，電路迴路C2a為由接腳42a的連通部421連接到基板61的子電路迴路，再經由基板61的子電路迴路連接到接腳42b的連通部421之佈線設計所形成，電路迴路C2b為由接腳42b連接到接腳42c之佈線設計所形成，電路迴路C2c為由接腳42c的連通部421連接到基板61的子電路迴路，再經由基板61的子電路迴路連接到接腳42d的連通部421之佈線設計所形成，而第二量測接點12係連接接腳42d，透過量測模組20測量電路迴路C2之一迴路阻抗值，並由處理模組30判斷迴路阻抗值是否超過一參考阻抗值，如此處理模組30能夠判斷基板61及軟性電路板63的接合處的接合品質。其餘技術特徵與第一實施例相同之處於此不再贅述。Please refer to FIG. 4A. In the second embodiment of the present invention, the first measuring contact 11 is connected to the pin 42a, and the circuit loop C2a is a sub-circuit loop connected to the substrate 61 by the connecting portion 421 of the pin 42a. The wiring design of the communication portion 421 connected to the pin 42b via the sub-circuit loop of the substrate 61 is formed by the wiring design of the circuit loop C2b connected to the pin 42c, and the circuit loop C2c is formed by the pin 42c. The connecting portion 421 is connected to the sub-circuit circuit of the substrate 61, and is then formed by the wiring design of the connecting portion 421 connected to the pin 42d via the sub-circuit circuit of the substrate 61. The second measuring contact 12 is the connecting pin 42d, The measurement module 20 measures a circuit impedance value of one of the circuit circuits C2, and the processing module 30 determines whether the circuit impedance value exceeds a reference impedance value. In this way, the processing module 30 can determine the junction of the substrate 61 and the flexible circuit board 63. Joining quality. The rest of the technical features are the same as those of the first embodiment and will not be repeated here.
接著，請參考圖4B係本發明之接合處阻抗檢測系統之第三實施例之架構示意圖，其中相同或相似元件使用相同或相似標號。Next, please refer to FIG. 4B, which is a schematic structural diagram of a third embodiment of the joint impedance detection system of the present invention, in which the same or similar components use the same or similar reference numerals.
於本發明之第三實施例大致類似於第二實施例，以下將針對本實施例與第二實施例不同之處進行說明。接合處阻抗檢測系統3包括接合處53、電路迴路C3、量測模組20及處理模組30，接合處阻抗檢測系統3係用以判斷電路迴路C3連接之接合處53是否具有一不良區域。接合處53係用以接合基板61及軟性電路板63，且接合處53包含複數接腳43，複數之接腳43耦接基板61及軟性電路板63，電路迴路C3是由該些接腳43中的至少二接腳43電性連接所形成。電路迴路C3具有一第一量測接點11及一第二量測接點12且包含電路迴路C3a、C3b、C3c。The third embodiment of the present invention is substantially similar to the second embodiment, and differences between this embodiment and the second embodiment will be described below. The joint impedance detection system 3 includes a joint 53, a circuit loop C3, a measurement module 20, and a processing module 30. The joint impedance detection system 3 is used to determine whether the joint 53 connected to the circuit loop C3 has a defective area. The joint 53 is used to join the substrate 61 and the flexible circuit board 63, and the joint 53 includes a plurality of pins 43. The plurality of pins 43 are coupled to the substrate 61 and the flexible circuit board 63. The circuit circuit C3 is composed of these pins 43. At least two of the pins 43 are electrically connected. The circuit loop C3 has a first measurement contact 11 and a second measurement contact 12 and includes a circuit loop C3a, C3b, C3c.
於本發明之第三實施例中，部分的接腳43可包含一連通部431，其中接腳43a、43b、43c、43d分別包含一連通部431，且連通部431設置於接腳43a、43b、43c、43d的中間位置，電路迴路C3能夠經由接腳43a、43b、43c、43d的連通部431電性連接電路元件（即基板61或軟性電路板63）之子電路迴路。In the third embodiment of the present invention, part of the pins 43 may include a communication portion 431, wherein the pins 43a, 43b, 43c, 43d respectively include a communication portion 431, and the communication portion 431 is disposed on the pins 43a, 43b In the intermediate positions of, 43c, and 43d, the circuit circuit C3 can be electrically connected to the sub-circuit circuits of the circuit element (ie, the substrate 61 or the flexible circuit board 63) via the connecting portions 431 of the pins 43a, 43b, 43c, and 43d.
請參圖4B，於本發明之第三實施例中，第一量測接點11係連接接腳43a，電路迴路C3a由接腳43a的連通部431連接到基板61的子電路迴路，再經由基板61的子電路迴路連接到接腳43a，並由接腳43a連接至接腳43b之佈線設計所形成，電路迴路C3b由接腳43b的連通部431連接到基板61的子電路迴路，再經由基板61的子電路迴路連接到接腳43b，並由接腳43b連接至接腳43c之佈線設計所形成，電路迴路C3c由接腳43c的連通部431連接到基板61的子電路迴路，再經由基板61的子電路迴路連接到接腳43c，並由接腳43c連接至接腳43d，又由接腳43d的連通部431連接到基板61的子電路迴路，再經由基板61的子電路迴路連接到接腳43d之佈線設計所形成，而第二量測接點12係連接接腳43d，透過量測模組20測量電路迴路C3之一迴路阻抗值，並由處理模組30判斷迴路阻抗值是否超過一參考阻抗值，如此處理模組30能夠判斷基板61及軟性電路板63的接合處的接合品質。其餘技術特徵與第一實施例相同之處於此不再贅述。Please refer to FIG. 4B. In the third embodiment of the present invention, the first measurement contact 11 is connected to the pin 43a, and the circuit circuit C3a is connected to the sub-circuit circuit of the substrate 61 by the connecting portion 431 of the pin 43a, and then via The sub-circuit circuit of the substrate 61 is connected to the pin 43a, and is formed by the wiring design of the pin 43a connected to the pin 43b. The circuit circuit C3b is connected to the sub-circuit circuit of the substrate 61 by the connecting portion 431 of the pin 43b, and then via The sub-circuit circuit of the substrate 61 is connected to the pin 43b and is formed by the wiring design of the pin 43b connected to the pin 43c. The circuit circuit C3c is connected to the sub-circuit circuit of the substrate 61 by the connecting portion 431 of the pin 43c, and then via The sub-circuit circuit of the substrate 61 is connected to the pin 43c, and is connected to the pin 43d by the pin 43c, and is connected to the sub-circuit circuit of the substrate 61 by the connecting portion 431 of the pin 43d, and then connected through the sub-circuit circuit of the substrate 61 It is formed by the wiring design to the pin 43d, and the second measurement contact 12 is connected to the pin 43d. The measurement module 20 measures a circuit impedance value of a circuit circuit C3, and the processing module 30 judges the circuit impedance value. Whether it exceeds a reference impedance value. The group 30 is capable of judging the joint quality of the joint between the substrate 61 and the flexible circuit board 63. The rest of the technical features are the same as those of the first embodiment and will not be repeated here.
接著請參考圖5A係本發明之接合處阻抗檢測系統之第四實施例之架構示意圖，其中相同或相似元件使用相同或相似標號。5A is a schematic structural diagram of a fourth embodiment of the joint impedance detection system of the present invention, in which the same or similar components use the same or similar reference numerals.
於本發明之第四實施例中，二電路元件包括軟性電路板63及印刷電路板64，各個電路元件（即軟性電路板63或印刷電路板64）包括一子電路迴路（圖未示出），接合處阻抗檢測系統4包括接合處54、電路迴路C4、量測模組20及處理模組30。接合處阻抗檢測系統4係用以判斷電路迴路C4連接之接合處54是否具有一不良區域。接合處54係用以接合軟性電路板63及印刷電路板64，且接合處54包含複數接腳44，複數之接腳44耦接軟性電路板63及印刷電路板64。電路迴路C4是由該些接腳44中的至少二接腳44電性連接所形成。電路迴路C4具有第一量測接點11及第二量測接點12且包含電路迴路C4a、C4b、C4c，電路迴路C4a、C4b、C4c電性連接該些接腳44中的至少二接腳44，其中第一量測接點11、至少二接腳44及第二量測接點12之間係彼此串聯連接，且電路迴路C4可以佈線的方式電性連接於耦接軟性電路板63及印刷電路板64之該些接腳44中的至少二接腳44。In the fourth embodiment of the present invention, the two circuit elements include a flexible circuit board 63 and a printed circuit board 64, and each circuit element (ie, the flexible circuit board 63 or the printed circuit board 64) includes a sub-circuit loop (not shown) The joint impedance detection system 4 includes a joint 54, a circuit loop C4, a measurement module 20 and a processing module 30. The joint impedance detection system 4 is used to determine whether the joint 54 connected to the circuit loop C4 has a defective area. The joint 54 is used to join the flexible circuit board 63 and the printed circuit board 64, and the joint 54 includes a plurality of pins 44, and the plurality of pins 44 are coupled to the flexible circuit board 63 and the printed circuit board 64. The circuit loop C4 is formed by at least two of the pins 44 being electrically connected. The circuit loop C4 has a first measurement contact 11 and a second measurement contact 12 and includes circuit loops C4a, C4b, and C4c. The circuit loops C4a, C4b, and C4c are electrically connected to at least two of the pins 44. 44, wherein the first measurement contact 11, the at least two pins 44 and the second measurement contact 12 are connected in series with each other, and the circuit loop C4 can be electrically connected to the coupling flexible circuit board 63 and At least two pins 44 of the pins 44 of the printed circuit board 64.
於本發明之第四實施例中，部分的接腳44可包含一連通部441，其中接腳44a、44b、44c、44d分別包含一連通部441，且連通部441設置於接腳44a、44b、44c、44d的末端位置，電路迴路C4能夠經由接腳44a、44b、44c、44d的連通部441電性連接電路元件（即軟性電路板63或印刷電路板64）之子電路迴路。In the fourth embodiment of the present invention, part of the pins 44 may include a communication portion 441, wherein the pins 44a, 44b, 44c, and 44d respectively include a communication portion 441, and the communication portion 441 is disposed on the pins 44a, 44b. At the end positions of, 44c, 44d, the circuit circuit C4 can be electrically connected to a sub-circuit circuit of a circuit element (ie, the flexible circuit board 63 or the printed circuit board 64) via the connecting portion 441 of the pins 44a, 44b, 44c, and 44d.
請參圖5A，於本發明之第四實施例中，第一量測接點11係連接接腳44a，電路迴路C4a由接腳44a的連通部441連接到印刷電路板64的子電路迴路，再經由印刷電路板64的子電路迴路連接到接腳44b的連通部441之佈線設計所形成，電路迴路C4b由接腳44b連接到接腳44c之佈線設計所形成，電路迴路C4c由接腳44c的連通部441連接到印刷電路板64的子電路迴路，再經由印刷電路板64的子電路迴路連接到接腳44d的連通部441之佈線設計所形成，而第二量測接點12係連接接腳44d，透過量測模組20測量電路迴路C4之一迴路阻抗值，並由處理模組30判斷迴路阻抗值是否超過一參考阻抗值，如此處理模組30能夠判斷軟性電路板63及印刷電路板64的接合處的接合品質。其餘技術特徵與第一實施例相同之處於此不再贅述。Please refer to FIG. 5A. In the fourth embodiment of the present invention, the first measuring contact 11 is connected to the pin 44a, and the circuit loop C4a is connected to the sub-circuit loop of the printed circuit board 64 by the connecting portion 441 of the pin 44a. Then it is formed by the wiring design of the connecting portion 441 of the printed circuit board 64 connected to the pin 44b. The circuit circuit C4b is formed by the wiring design of the pin 44b connected to the pin 44c. The circuit circuit C4c is formed by the pin 44c. The connecting portion 441 is connected to the sub-circuit circuit of the printed circuit board 64, and then the sub-circuit circuit of the printed circuit board 64 is connected to the wiring design of the connecting portion 441 of the pin 44d. The second measurement contact 12 is connected. At pin 44d, a loop impedance value of one of the circuit loops C4 is measured through the measurement module 20, and the processing module 30 determines whether the loop impedance value exceeds a reference impedance value. In this way, the processing module 30 can judge the flexible circuit board 63 and the printing The joint quality of the joint of the circuit board 64. The rest of the technical features are the same as those of the first embodiment and will not be repeated here.
接著請參考圖5B係本發明之接合處阻抗檢測系統之第五實施例之架構示意圖，其中相同或相似元件使用相同或相似標號。5B is a schematic structural diagram of a fifth embodiment of the joint impedance detection system of the present invention, in which the same or similar components are denoted by the same or similar reference numerals.
於本發明之第五實施例大致類似於第四實施例，以下將針對本實施例與第四實施例不同之處進行說明。接合處阻抗檢測系統5包括接合處55、電路迴路C5、量測模組20及處理模組30。接合處阻抗檢測系統5係用以判斷電路迴路C5連接之接合處55是否具有一不良區域。接合處55係用以接合軟性電路板63及印刷電路板64，且接合處55包含複數接腳45，複數之接腳45耦接軟性電路板63及印刷電路板64。電路迴路C5是由該些接腳45中的至少二接腳45電性連接所形成。電路迴路C5具有第一量測接點11及一第二量測接點12且包含電路迴路C5a、C5b、C5c。The fifth embodiment of the present invention is substantially similar to the fourth embodiment, and the differences between this embodiment and the fourth embodiment will be described below. The joint impedance detection system 5 includes a joint 55, a circuit circuit C5, a measurement module 20, and a processing module 30. The joint impedance detection system 5 is used to determine whether the joint 55 connected to the circuit circuit C5 has a defective area. The joint 55 is used to join the flexible circuit board 63 and the printed circuit board 64, and the joint 55 includes a plurality of pins 45, and the plurality of pins 45 are coupled to the flexible circuit board 63 and the printed circuit board 64. The circuit loop C5 is formed by at least two of the pins 45 being electrically connected. The circuit loop C5 has a first measurement contact 11 and a second measurement contact 12 and includes a circuit loop C5a, C5b, C5c.
於本發明之第五實施例中，部分的接腳45可包含一連通部451，其中接腳45a、45b、45c、45d分別包含一連通部451，且連通部451設置於接腳45a、45b、45c、45d的中間位置，電路迴路C5能夠經由接腳45a、45b、45c、45d的連通部451電性連接電路元件（即軟性電路板63或印刷電路板64）之子電路迴路。In the fifth embodiment of the present invention, part of the pins 45 may include a communication portion 451, wherein the pins 45a, 45b, 45c, and 45d respectively include a communication portion 451, and the communication portion 451 is disposed on the pins 45a and 45b. In the intermediate positions of, 45c, 45d, the circuit loop C5 can be electrically connected to the sub-circuit loop of the circuit element (ie, the flexible circuit board 63 or the printed circuit board 64) via the connecting portions 451 of the pins 45a, 45b, 45c, and 45d.
請參圖5B，於本發明之第五實施例中，第一量測接點11係連接接腳45a，電路迴路C5a由接腳45a的連通部451連接到印刷電路板64的子電路迴路，再經由印刷電路板64的子電路迴路連接到接腳45a，並由接腳45a連接至接腳45b之佈線設計所形成，電路迴路C5b由接腳45b的連通部451連接到印刷電路板64的子電路迴路，再經由印刷電路板64的子電路迴路連接到接腳45b，並由接腳45b連接至接腳45c之佈線設計所形成，電路迴路C5c由接腳45c的連通部451連接到印刷電路板64的子電路迴路，再經由印刷電路板64的子電路迴路連接到接腳45c，並由接腳45c連接至接腳45d，又由接腳45d的連通部451連接到印刷電路板64的子電路迴路，再經由印刷電路板64的子電路迴路連接到接腳45d之佈線設計所形成，而第二量測接點12係連接接腳45d，透過量測模組20測量電路迴路C5之一迴路阻抗值，並由處理模組30判斷迴路阻抗值是否超過一參考阻抗值，如此處理模組30能夠判斷軟性電路板63及印刷電路板64的接合處的接合品質。其餘技術特徵與第一實施例相同之處於此不再贅述。Please refer to FIG. 5B. In a fifth embodiment of the present invention, the first measurement contact 11 is connected to the pin 45a, and the circuit circuit C5a is connected to the sub-circuit circuit of the printed circuit board 64 by the connecting portion 451 of the pin 45a. It is then connected to pin 45a through the sub-circuit loop of printed circuit board 64, and is formed by the wiring design of pin 45a connected to pin 45b. Circuit loop C5b is connected to the printed circuit board 64 by the connecting portion 451 of pin 45b. The sub-circuit loop is connected to the pin 45b via the sub-circuit loop of the printed circuit board 64, and is formed by the wiring design of the pin 45b connected to the pin 45c. The circuit loop C5c is connected to the print by the connecting portion 451 of the pin 45c. The sub-circuit circuit of the circuit board 64 is connected to the pin 45c via the sub-circuit circuit of the printed circuit board 64, and is connected to the pin 45d by the pin 45c, and is connected to the printed circuit board 64 by the connecting portion 451 of the pin 45d. The sub-circuit loop is formed by the wiring design connected to the pin 45d through the sub-circuit loop of the printed circuit board 64, and the second measurement contact 12 is connected to the pin 45d, and the circuit loop C5 is measured through the measurement module 20. One of the loop impedance values 30 determines whether the loop impedance value exceeds a reference resistance value, thus engaging quality processing module 64 at the junction 30 can be determined that the flexible circuit board 63 and the printed circuit board. The rest of the technical features are the same as those of the first embodiment and will not be repeated here.
接著請參考圖6係本發明之接合處阻抗檢測系統之第六實施例之架構示意圖，其中相同或相似元件使用相同或相似標號。Next, please refer to FIG. 6, which is a schematic structural diagram of a sixth embodiment of the joint impedance detection system of the present invention, in which the same or similar components use the same or similar reference numerals.
於本發明之第六實施例中，電路元件包括基板61、電路晶片62及軟性電路板63，接合處阻抗檢測系統6包括接合處56a、56b、電路迴路C6、量測模組20及處理模組30。接合處阻抗檢測系統6係用以判斷電路迴路C6連接之接合處56a、56b是否具有一不良區域。接合處56a係用以接合於基板61與電路晶片62以及接合處56b係用以接合於基板61與軟性電路板63，電路迴路C6是由接合處56a的該些接腳中的至少二接腳及接合處56b的該些接腳中的至少二接腳電性連接所形成。電路迴路C6具有第一量測接點11及第二量測接點12，且第一量測接點11、接合處56a之至少二接腳、接合處56b之至少二接腳及第二量測接點12之間係彼此串聯連接。透過量測模組20測量電路迴路C6之一迴路阻抗值，並由處理模組30判斷迴路阻抗值是否超過一參考阻抗值，藉由上述連接接合於基板61與電路晶片62的接合處56a及接合於基板61與軟性電路板63的接合處56b的電路迴路設計，如此處理模組30能夠判斷基板61與電路晶片62及基板61與軟性電路板63的兩個接合處的接合品質。其餘技術特徵與第一實施例相同之處於此不再贅述。In the sixth embodiment of the present invention, the circuit element includes a substrate 61, a circuit wafer 62, and a flexible circuit board 63. The joint impedance detection system 6 includes joints 56a, 56b, a circuit circuit C6, a measurement module 20, and a processing module. Group of 30. The joint impedance detection system 6 is used to determine whether the joints 56a, 56b connected to the circuit loop C6 have a defective area. The joint 56a is used to join the substrate 61 and the circuit wafer 62 and the joint 56b is used to join the substrate 61 and the flexible circuit board 63. The circuit circuit C6 is at least two of the pins of the joint 56a. And at least two of the pins of the joint 56b are electrically connected. The circuit circuit C6 has a first measurement contact 11 and a second measurement contact 12, and the first measurement contact 11, the at least two pins of the joint 56a, the at least two pins of the joint 56b, and the second amount The measuring contacts 12 are connected in series with each other. A loop impedance value of one of the circuit loops C6 is measured through the measurement module 20, and the processing module 30 determines whether the loop impedance value exceeds a reference impedance value, and is bonded to the joint 56a of the substrate 61 and the circuit chip 62 through the above connection and The circuit circuit design of the junction 56b of the substrate 61 and the flexible circuit board 63 is designed so that the processing module 30 can judge the joint quality of the substrate 61 and the circuit wafer 62 and the two junctions of the substrate 61 and the flexible circuit board 63. The rest of the technical features are the same as those of the first embodiment and will not be repeated here.
接著請參考圖7係本發明之接合處阻抗檢測系統之第七實施例之架構示意圖，其中相同或相似元件使用相同或相似標號。Please refer to FIG. 7, which is a schematic diagram of a seventh embodiment of the joint impedance detection system of the present invention, in which the same or similar components are denoted by the same or similar reference numerals.
於本發明之第七實施例中，電路元件包括基板61、電路晶片62、軟性電路板63及印刷電路板64，接合處阻抗檢測系統7包括接合處57a、57b、57c、電路迴路C7、量測模組20及處理模組30。接合處阻抗檢測系統7係用以對電路迴路C7連接之接合處57a、57b、57c是否具有一不良區域。接合處57a係用以接合於基板61與電路晶片62，接合處57b係用以接合於基板61與軟性電路板63以及接合處57c係用以接合於軟性電路板63與印刷電路板64。電路迴路C7是由接合處57a的該些接腳中的至少二接腳、接合處57b的該些接腳中的至少二接腳及接合處57c的該些接腳中的至少二接腳電性連接所形成。電路迴路C7具有第一量測接點11及第二量測接點12，且第一量測接點11、接合處57a之至少二接腳、接合處57b之至少二接腳、接合處57c之至少二接腳及第二量測接點12之間係彼此串聯連接。本實施例可透過量測模組20電性連接第一量測接點11及第二量測接點12以測量電路迴路C7之一迴路阻抗值，並由處理模組30判斷迴路阻抗值是否超過一參考阻抗值，藉由上述連接接合於基板61與電路晶片62的接合處57a、接合於基板61與軟性電路板63的接合處57b及接合於軟性電路板63與印刷電路板64的接合處57c的電路迴路設計，如此處理模組30能夠判斷基板61與電路晶片62、基板61與軟性電路板63及軟性電路板63與印刷電路板64的三個接合處的接合品質。In the seventh embodiment of the present invention, the circuit element includes a substrate 61, a circuit wafer 62, a flexible circuit board 63, and a printed circuit board 64. The joint impedance detection system 7 includes joints 57a, 57b, 57c, a circuit circuit C7, and a quantity. Test module 20 and processing module 30. The joint impedance detection system 7 is used to connect the joints 57a, 57b, and 57c of the circuit circuit C7 with a defective area. The joint 57a is used to join the substrate 61 and the circuit wafer 62, the joint 57b is used to join the substrate 61 and the flexible circuit board 63, and the joint 57c is used to join the flexible circuit board 63 and the printed circuit board 64. The circuit C7 is electrically powered by at least two of the pins of the joint 57a, at least two of the pins of the joint 57b, and at least two of the pins of the joint 57c. Sexual connection. The circuit circuit C7 has a first measurement contact 11 and a second measurement contact 12, and the first measurement contact 11, the at least two pins of the joint 57a, the at least two pins of the joint 57b, and the joint 57c. The at least two pins and the second measuring contact 12 are connected in series with each other. In this embodiment, the first measurement contact 11 and the second measurement contact 12 can be electrically connected through the measurement module 20 to measure a loop impedance value of the circuit loop C7, and the processing module 30 determines whether the loop impedance value is Exceeds a reference impedance value, and is connected to the joint 57a of the substrate 61 and the circuit wafer 62, the joint 57b of the substrate 61 and the flexible circuit board 63, and the joint of the flexible circuit board 63 and the printed circuit board 64 through the above connection. In the circuit circuit design of 57c, the processing module 30 can judge the joint quality of the three joints of the substrate 61 and the circuit wafer 62, the substrate 61 and the flexible circuit board 63, and the flexible circuit board 63 and the printed circuit board 64.
於本實施例中，電路迴路C7可更具有一第三量測接點13及一第四量測接點14，第三量測接點13設置於第一量測接點11及接合處57b之間，第四量測接點14設置於第二量測接點12及接合處57b之間，量測模組電性連接第三量測接點13及第四量測接點14以測量由第三量測接點13、接合處57a之至少二接腳、接合處57b之至少二接腳及第四量測接點14之間彼此串聯連接形成之電路迴路C7之一迴路阻抗值，如此處理模組能夠判斷基板61與電路晶片62及基板61與軟性電路板63的二個接合處的接合品質，其餘技術特徵與第一實施例相同之處於此不再贅述。In this embodiment, the circuit circuit C7 may further have a third measurement contact 13 and a fourth measurement contact 14, and the third measurement contact 13 is disposed at the first measurement contact 11 and the joint 57b. In between, the fourth measurement contact 14 is disposed between the second measurement contact 12 and the joint 57b. The measurement module is electrically connected to the third measurement contact 13 and the fourth measurement contact 14 to measure. A circuit impedance value of a circuit loop C7 formed by connecting the third measurement contact 13, the at least two pins of the joint 57a, the at least two pins of the joint 57b, and the fourth measurement contact 14 in series with each other. In this way, the processing module can judge the joint quality of the two joints of the substrate 61 and the circuit wafer 62 and the substrate 61 and the flexible circuit board 63. The rest of the technical features are the same as those of the first embodiment and will not be repeated here.
藉由上述本發明提供之接合處阻抗檢測方法及接合處阻抗檢測系統，透過電性連接接合處的該些接腳之至少二接腳以形成電路迴路，並測量電路迴路之一迴路阻抗值以判斷迴路阻抗值是否超過一參考阻抗值，以藉此檢測二電路元件之間的接合處的接合品質。此外本發明提供之接合處阻抗檢測方法及接合處阻抗檢測系統亦可以適用於不同電路元件之間的接合處並依據需求設計各式的電路迴路，並不以本說明書所示的電路迴路C1到C7為限，且基板亦不限於LCD的玻璃基板。By using the joint impedance detection method and the joint impedance detection system provided by the present invention, a circuit loop is formed by electrically connecting at least two pins of the pins at the joint, and measuring a loop impedance value of one of the circuit loops to It is determined whether the loop impedance value exceeds a reference impedance value, thereby detecting the joint quality of the joint between the two circuit elements. In addition, the joint impedance detection method and the joint impedance detection system provided by the present invention can also be applied to the joints between different circuit elements and design various circuit circuits according to requirements. The circuit circuits C1 to C1 shown in this specification are not used. C7 is limited, and the substrate is not limited to the glass substrate of the LCD.
需注意的是，上述實施方式僅例示本發明之較佳實施例，為避免贅述，並未詳加記載所有可能的變化組合。然而，本領域之通常知識者應可理解，上述各模組或元件未必皆為必要。且為實施本發明，亦可能包含其他較細節之習知模組或元件。各模組或元件皆可能視需求加以省略或修改，且任兩模組間未必不具有其他模組或元件。只要不脫離本發明基本架構者，皆應為本專利所主張之權利範圍，而應以專利申請範圍為準。It should be noted that the above-mentioned implementations are merely examples of the preferred embodiments of the present invention. To avoid redundant descriptions, not all possible combinations of changes are described in detail. However, those of ordinary skill in the art should understand that the above modules or components are not necessarily necessary. In order to implement the present invention, other more detailed conventional modules or components may also be included. Each module or component may be omitted or modified as required, and there may not be other modules or components between any two modules. As long as it does not depart from the basic structure of the present invention, it should be the scope of rights claimed by this patent, and the scope of patent application shall prevail.
90‧‧‧接合處90‧‧‧ Junction
91‧‧‧優良區域91‧‧‧Excellent area
92‧‧‧不良區域92‧‧‧ Bad area
1、2、3、4、5、6、7‧‧‧接合處阻抗檢測系統1,2,3,4,5,6,7‧‧‧joint impedance detection system
11‧‧‧第一量測接點11‧‧‧First measurement contact
12‧‧‧第二量測接點12‧‧‧Second measuring contact
13‧‧‧第三量測接點13‧‧‧Third measurement contact
14‧‧‧第四量測接點14‧‧‧Fourth measuring contact
20‧‧‧量測模組20‧‧‧Measuring module
30‧‧‧處理模組30‧‧‧Processing Module
41、41a、41b、41c、42、42a、42b、42c、42d、43、43a、43b、43c、43d、44、44a、44b、44c、44d、45、45a、45b、45c、45d‧‧‧接腳41, 41a, 41b, 41c, 42, 42a, 42b, 42c, 42d, 43, 43a, 43b, 43c, 43d, 44, 44a, 44b, 44c, 44d, 45, 45a, 45b, 45c, 45d Pin
411、421、431、441、451‧‧‧連通部411, 421, 431, 441, 451‧‧‧ Connected
51、52、53、54、55、56a、56b、57a、57b、57c‧‧‧接合處51, 52, 53, 54, 55, 56a, 56b, 57a, 57b, 57c
61‧‧‧基板61‧‧‧ substrate
62‧‧‧電路晶片62‧‧‧Circuit Chip
63‧‧‧軟性電路板63‧‧‧flexible circuit board
64‧‧‧印刷電路板64‧‧‧printed circuit board
C1、C2、C2a、C2b、C2c、C3、C3a、C3b、C3c、C4、C4a、C4b、C4c、C5、C5a、C5b、C5c、C6、C7‧‧‧電路迴路C1, C2, C2a, C2b, C2c, C3, C3a, C3b, C3c, C4, C4a, C4b, C4c, C5, C5a, C5b, C5c, C6, C7‧‧‧Circuit
301、302、303、304、305、306‧‧‧步驟301, 302, 303, 304, 305, 306‧‧‧ steps
圖1係先前技術中之接合處之示意圖。 圖2係本發明之接合處阻抗檢測系統之第一實施例之架構示意圖。 圖3係本發明之接合處阻抗檢測方法之步驟流程圖。 圖4A係本發明之接合處阻抗檢測系統之第二實施例之架構示意圖。 圖4B係本發明之接合處阻抗檢測系統之第三實施例之架構示意圖。 圖5A係本發明之接合處阻抗檢測系統之第四實施例之架構示意圖。 圖5B係本發明之接合處阻抗檢測系統之第五實施例之架構示意圖。 圖6係本發明之接合處阻抗檢測系統之第六實施例之架構示意圖。 圖7係本發明之接合處阻抗檢測系統之第七實施例之架構示意圖。FIG. 1 is a schematic diagram of a joint in the prior art. FIG. 2 is a schematic structural diagram of a first embodiment of a joint impedance detection system of the present invention. FIG. 3 is a flowchart of the steps of the method for detecting impedance of a joint according to the present invention. FIG. 4A is a schematic structural diagram of a second embodiment of the joint impedance detection system of the present invention. FIG. 4B is a schematic structural diagram of a third embodiment of the joint impedance detection system of the present invention. FIG. 5A is a schematic structural diagram of a fourth embodiment of the joint impedance detection system of the present invention. FIG. 5B is a schematic structural diagram of a fifth embodiment of the joint impedance detection system of the present invention. FIG. 6 is a schematic structural diagram of a sixth embodiment of the joint impedance detection system of the present invention. FIG. 7 is a schematic structural diagram of a seventh embodiment of the joint impedance detection system of the present invention.
Claims (12)
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| US6937028B2 (en) * | 2003-05-30 | 2005-08-30 | Agere Systems Inc. | Resistor value detection circuit |
| CN1712975A (en) * | 2004-06-22 | 2005-12-28 | 瀚宇彩晶股份有限公司 | Connected impedance measurement and structure |
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| TWI411841B (en) * | 2008-12-02 | 2013-10-11 | Au Optronics Corp | Lcd module and method for measuring contact resistances between circuit boards therein |
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| US6940301B2 (en) * | 2003-12-12 | 2005-09-06 | Au Optronics Corporation | Test pad array for contact resistance measuring of ACF bonds on a liquid crystal display panel |
| JP4695920B2 (en) * | 2005-05-19 | 2011-06-08 | 日置電機株式会社 | Impedance measuring device |
| JP5034781B2 (en) * | 2007-08-27 | 2012-09-26 | 富士通株式会社 | High-sensitivity resistance measuring device and monitoring method for solder bump |
| CN102339250A (en) * | 2010-07-16 | 2012-02-01 | 鸿富锦精密工业（深圳）有限公司 | Mainboard signal testing device |
| CN202119854U (en) * | 2011-03-03 | 2012-01-18 | 昌硕科技(上海)有限公司 | Pin welding state detection apparatus |
| CN202694326U (en) * | 2012-06-13 | 2013-01-23 | 深圳市祈飞科技有限公司 | Test device |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6937028B2 (en) * | 2003-05-30 | 2005-08-30 | Agere Systems Inc. | Resistor value detection circuit |
| TWI252943B (en) * | 2004-05-24 | 2006-04-11 | Hannstar Display Corp | Measuring method and structure for bonding impedance |
| CN1712975A (en) * | 2004-06-22 | 2005-12-28 | 瀚宇彩晶股份有限公司 | Connected impedance measurement and structure |
| TWI308220B (en) * | 2006-11-10 | 2009-04-01 | Innolux Display Corp | Bonding impedance detecting method for integrated circuit system |
| TWI411841B (en) * | 2008-12-02 | 2013-10-11 | Au Optronics Corp | Lcd module and method for measuring contact resistances between circuit boards therein |
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