1232306 五、發明說明（1) 【發明所屬之技術領域】 本發明係有關於一種捲帶自動接合之檢測方法，特別 係有關於一種檢測在各式凸塊間距中捲帶自動接合製程能 力之方法。 【先前技術】 捲帶自動接合〔Tape Automated Bonding，TAB〕係 利用熱壓合$又備將晶片接合於一捲帶輸送之電路薄膜，’如 捲帶承載封裝〔Tape Carrier Package〕之捲帶或覆晶薄 膜封裝〔Chi p-On-Film〕之軟膜，習知晶片係具有複^個 凸塊〔可由數百至數千之數〕，如金凸塊，在每一壓合 驟中應將一晶片之所有凸塊係與該電路薄膜之内引腳相互 熱接合’當晶片之凸塊間距愈小或晶片長度愈長，則晶片 ，凸塊愈不易準確接合於電路薄膜，特別當晶片之凸塊間 以下時，目前並未有適用之檢測方法，以 #估捲帶自動接合在不同凸塊微間距之可行性。 測試第2二557 ϊ「捲帶式晶粒接合之非破壞 (Χ^γχ 其係將接合有1C晶粒之捲帶放置於一 晶粒 ^ ^ ^ ^ ^ M T . . ,1 I. ^ 【發明内容】 測方法，利：f 5二：係在於提供-種捲帶自動接合之檢 且各式不等門^測試晶片與一測試電路薄膜分別設有對應 各式不等間距之凸塊與内引腳，該些内引腳之間設有局1232306 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a method for detecting automatic joining of tapes, and in particular to a method for detecting the ability of automatic joining processes of tapes in various bump pitches. . [Previous Technology] Tape Automated Bonding (TAB) is a circuit film that is bonded to a tape with a tape by using thermal compression bonding, such as a tape or a tape carrier package or a tape carrier package. Chip-on-Film (Chi p-On-Film) is a soft film. The conventional chip has multiple bumps [from hundreds to thousands], such as gold bumps. In each pressing step, the All the bumps of a wafer are thermally bonded with the inner pins of the circuit film. 'When the distance between the bumps of the wafer is smaller or the length of the wafer is longer, the wafer and the bumps are less likely to be accurately bonded to the circuit film. Below the bumps, there is currently no applicable detection method to evaluate the feasibility of automatic joining of coils at different pitches of bumps. Test No. 2 557 ϊ "Non-destructive reel-to-reel type die bonding (χ ^ γχ It is to place a reel with 1C die bonded on a die ^ ^ ^ ^ ^ MT.., 1 I. ^ [ SUMMARY OF THE INVENTION The measuring method is beneficial: f 5 2: It is to provide-a kind of automatic inspection of the tape and various types of doors ^ test wafer and a test circuit film are provided with bumps and Inner pins, with bureaus between these inner pins
1232306 五、發明說明（2) u j，路，以電性導接預留在部份凸塊之間的tf & r* 以供：：捲帶自動接合在不同凸塊微間距之可：：路區， 測方、明之次一目的係在於提供一種捲帶自動接人^ :在，Γ 一測試電路薄膜設有各式不等間 ^些内引腳之間設有局部互連線路，並且=引 ^接一測試墊，卩電性測試該些測試墊之方式：内 ^間距條件下凸塊之接合導 ^測在 之製程能力。 乂伢汁估捲帶自動接合 發月之再目的係在於提供一種用以檢測捲德6 # J合之測試電路薄膜，㈣數個不等間距二自J 均形成有一測試墊，該也内 弓丨腳外屬 工：份之内引腳之間連接有互連線路 ：= 之斷路區’藉由該些測試墊之電性測試，以Ϊ = 間距凸塊之接合程度。 j〜从檢測不同 有：依本發明之捲帶自動接合之檢測方法，其包含之步驟 供一測试晶片，該泪丨| 士士曰JJ 拓 凸塊組1凸塊組：包面係具有至少-此几仏〆 货匕s有複數個不相等間距之凸塊，該 ς 糸部份電性導接而保留有複數個 該測試晶片係具有非電性功能〔unfuncti〇nai〕較佳也_ 提供一測試電路簿膜，兮：目丨丨4雨k 电峪溥膜，該測试電路薄膜係具有至少一 兮此、:I ^腳組係包含有複數個不相等間距之内引腳， :p引腳之間係具有局部互連線路 路區之間的凸塊，並且每—内引腳之外端連接有一測試 1232306 五、發明說明（3) 塾，較佳地 〔electro-錯且不互連 測，或該電 〔peeling 接合該 之凸塊接合 電性測 之接合。 【實施方式 參閱所 請參閱 帶自動接合 「提供一測 電路薄膜」 在「提 提供之測試 有至少一凸 分配有複數 有非電性功 凸塊組22係 塊，該些凸 35 、 38 、 40 片20之金屬 ’該電路薄膜係包含有一電性遷移檢測區 migration detecting area〕，其具有兩兩交 之梳狀線路，以供捲帶材料導電間離子遷移檢 路薄膜可包含有包含有一剝離強度測試墊 strength test pad 〕； 測試晶片與該測試電路薄膜，使得該測試晶片 於該測試電路薄膜之内引腳；及 试該測試電路薄膜之測試塾，以檢測該些凸塊1232306 V. Description of the invention (2) uj, road, electrically connected tf & r * reserved between some bumps for :: the tape can automatically join at different pitches of different bumps :: In the road area, the test square and the next time the purpose is to provide a tape automatic access ^: In Γ, a test circuit film is provided with various types of unequal intervals ^ some internal pins are provided with interconnection lines, and = Introduction of a test pad, the method of electrical test of these test pads: the bonding guide of the bump under the condition of the inner space, and the test process capability. The purpose of the automatic jointing of the jujube tape is to provide a test circuit film for detecting the coil 6 # J, and a number of test pads are formed at different intervals.丨 External work: There are interconnections between the inner pins: = of the open circuit area 'Through the electrical test of these test pads, Ϊ = the degree of bonding of the pitch bumps. j ~ The difference from the detection is: according to the method for automatically joining the tape and reel according to the present invention, which includes steps for a test wafer, the tears 丨 | At least-these cargo daggers have a plurality of bumps with unequal spacing. The ς part is electrically connected and a plurality of test chips are retained. The non-electrical function [unfuncti〇nai] is also better. _ Provide a test circuit book film: ： 44k electric film, the test circuit film system has at least one of the following: The I ^ foot system includes a plurality of unequal pitch inner pins The: p pins are provided with bumps between the local interconnecting circuit areas, and a test 1232306 is connected to the outer end of each inner pin. 5. Description of the invention (3) 塾, preferably [electro-error And do not interconnect the test, or the electrical [peeling bonding of the bump bonding electrical test of the bond. [For the implementation, please refer to the reference, "provide a test circuit film" with automatic bonding. In the "provided test, there are at least one protrusion allocated with a plurality of non-electrical work bump groups 22 series blocks, and these protrusions 35, 38, 40 The metal of sheet 20 The circuit film includes an electrical migration detection area], which has comb-like lines that intersect one another for the tape material to conduct ion migration between the conductive path detection films. The film may include a peel strength Test pad strength test pad]; test the wafer and the test circuit film, so that the test wafer leads within the test circuit film; and test the test circuit film of the test circuit film to detect the bumps
附圖式，本發明將列舉以下之實施例說明。 第1圖，依本發明之一具體實施例所例舉之捲 檢測方法，其包含有「提供一測試晶片」π、 試電路薄膜」1 2、「接合該測試晶片與該測試 1 3及「電性測試」1 4等步驟。 供一測試晶片」11步驟中，請參閱第2圖，所 晶片2 0係包含有一壓合面21，該壓合面21係具 塊組2 2，在本實施例中，該壓合面2 1之周邊係 個凸塊組22、23，較佳地，該測試晶片20係龜 能〔unfunct ional〕，請再參閱第3圖，每一 包含有複數個不相等間距之凸塊221，如金凸 塊2 2 1之間距係以漸進方式選自於3 〇、3 3、 、42與4 5 //in，該些凸塊221係結合於該測試晶 墊222，並以該測試晶片20之内部線路223部份 imm 第7頁 1232306 五、發明說明（4) 電性導接該些凸塊221 ,使得該些凸塊221之間保留有複數 個不連續之斷路區224，在本實施例中，該些凸塊221係兩 兩電性連接，較佳地，該測試晶片2 〇另包含有至少一凸塊 組23 ’其凸塊長度係小於該凸塊組22之凸塊22ι長度，以 供檢測比較不同大小凸塊之接合強度，而能選擇出適用之 凸塊尺寸。 在「提供一測試電路薄膜」丨2之步驟中，請參閱第4 及5圖，所提供之電路薄膜30係包含有至少一引腳組31， 在本實施例中，引腳組3 1之數量係對應於上述測試晶片2 〇 之凸塊組22、23，每一引腳組31係包含有複數個不相等 距之内引腳311，每一内引腳311外端連接有一測試墊3 12 〔test pad〕，並且部份之内引腳311之間係具有局部互 連線路31 3，其電性連接路徑係用以補償上述之斷路區 224 ’當該晶片20與該電路薄膜30接合良好時該些互連線 路31 3係能導通在該些斷路區2 2 4之間的凸塊2 21。 ' 接合〔Inner Lead Bonding， I LB〕技術將該測試晶片2〇 之凸塊221與該測試電路薄膜30之内引腳311相互接合， 接合條件係模擬實際生產或預定生產之狀態，請參閱第5 在「接合該測試晶片與該測試電路薄膜」1 3之步驟 中’其係利用覆晶接合〔flip-chip Bonding〕或内弓I腳 圖，當接合良好時，每一凸塊221依序能經由接合處、對 應内引腳311、互連線路313、鄰接導通内引腳311、鄰接 凸塊221、晶片之墊222及晶片之線路223等等電性導通之 同一凸塊組2 2之其它凸塊2 2 1，該電性導通路徑均會通過 1232306 五、發明說明（5) 該些凸塊221與内引腳311之接合處，若接合不良， 些凸塊221之間會產生斷路。 “ 在「電性測試」U之步驟中，f先利用一電氣測量計 〔electric meter〕，其一端係接觸在具較大内引腳3 ^ 間距〔如45 //m〕之測試墊3 12〔請參閱第5圖較右側之測 試墊31 2〕，而電氣測量計之另一端係接觸在具最小 <引 腳311間距〔如30"m〕之測試墊312〔請參閱第5圖較左側 之測試墊312〕，如測得電流通過，表示在該兩測試墊312 之間該些凸塊221均能通由晶片線路223與互連線路313電 性導通，該些凸塊22 1係能在最小内引腳間距處之接人良 好，以該檢測之條件、該測試晶片2〇與該測試電路薄"膜^ 之材料應可符合最小凸塊間距，反之，若測得未有電流通 過’表示在該兩測試墊312之間的該些凸塊221有斷路^ 象，即至少一在該兩測試墊312之間的凸塊221接合不良， 以該檢測之條件無法可實施於最小凸塊間距〔3〇 :瓜〕， 調整該電氣測量計之另一端，使其接觸在具次一級較小内 引腳311間距〔如3 3 //m〕之測試墊3 12〔即測試之測試墊 312往右移〕，如再測得未有電流通過，則連續調整該電 氣測量計之另一端，以接觸具有漸大寬度之内引腳311間 距〔由35 至45 〕之測試墊312，直至測得有電流通< 過為止，以確定該製程能力可製作那一階段凸塊間距之捲 帶自動接合，在本實施例中，其係能評估在3〇、33、35、 38、40、42與45 //m凸塊間距範圍内捲帶自動接合之可行 性，但若在「電性測試」1 4之步驟中均測得未有電流通BRIEF DESCRIPTION OF THE DRAWINGS The invention will be illustrated by the following examples. FIG. 1 is a roll detection method exemplified according to a specific embodiment of the present invention, which includes “provide a test wafer” π, a test circuit film ”1 2,“ join the test wafer and the test 13 and “ Electrical test "1 4 steps. For a test wafer "11 step, please refer to Fig. 2. The wafer 20 includes a pressing surface 21, which is a block group 2 2. In this embodiment, the pressing surface 2 The periphery of 1 is a bump group 22, 23, preferably, the test wafer 20 is a turtle [unfunctional], please refer to FIG. 3 again, each of which includes a plurality of bumps 221 of unequal spacing, such as The distance between the gold bumps 2 2 1 is selected in a progressive manner from 3 0, 3 3, 42 and 4 5 // in. The bumps 221 are bonded to the test pad 222 and the test wafer 20 is used. The internal circuit 223 part imm Page 7 1232306 V. Explanation of the invention (4) The bumps 221 are electrically connected so that there are a plurality of discontinuous disconnection areas 224 between the bumps 221. In this implementation, In the example, the bumps 221 are electrically connected in pairs. Preferably, the test wafer 20 further includes at least one bump group 23 ′ whose bump length is shorter than the length of the bumps 22 ι of the bump group 22. , For testing and comparing the bonding strength of bumps of different sizes, and can choose the appropriate bump size. In the step of “providing a test circuit film”, please refer to FIGS. 4 and 5. The provided circuit film 30 includes at least one pin group 31. In this embodiment, the pin group 31 The number corresponds to the bump groups 22 and 23 of the above-mentioned test chip 20. Each pin group 31 includes a plurality of unequal inner pins 311, and a test pad 3 is connected to the outer end of each inner pin 311. 12 [test pad], and there are local interconnection lines 31 3 between some of the pins 311, and the electrical connection path is used to compensate the above-mentioned open area 224 'When the chip 20 is bonded to the circuit film 30 When good, the interconnect lines 31 3 are capable of conducting the bumps 2 21 between the disconnection areas 2 2 4. 'Bonding (Inner Lead Bonding, I LB) technology bonds the bump 221 of the test wafer 20 with the pins 311 in the test circuit film 30, and the bonding conditions simulate the actual production or scheduled production. 5 In the step of "Joining the test wafer and the test circuit film" 1 3 ', it uses flip-chip bonding or inner bow I foot diagram. When the bonding is good, each bump 221 is in order The same bump group 2 that can be electrically conducted through the joint, the corresponding inner pin 311, the interconnect line 313, the adjacent conductive inner pin 311, the adjacent bump 221, the wafer pad 222, and the wafer line 223, etc. For other bumps 2 2 1, the electrical conduction path will pass through 1232306. V. Description of the invention (5) The joints between the bumps 221 and the inner pins 311. If the joints are not well connected, a break will occur between the bumps 221. . "In the step of" electricity test "U, f first uses an electric meter, one end of which is in contact with a test pad with a larger inner pin 3 ^ pitch [such as 45 // m] 3 12 [Please refer to the test pad 31 2 on the right in Figure 5], and the other end of the electrical meter is in contact with the test pad 312 with a minimum < lead 311 pitch [such as 30 " m]. The test pad 312 on the left side], if the current is measured, it means that the bumps 221 can be electrically connected through the chip line 223 and the interconnection line 313 between the two test pads 312. The bumps 22 1 are Good access at the minimum internal pin pitch. Under the conditions of the test, the material of the test chip 20 and the test circuit thin "film" should be able to meet the minimum bump pitch. Otherwise, if no The current passing indicates that the bumps 221 between the two test pads 312 are broken, that is, at least one of the bumps 221 between the two test pads 312 is poorly connected, and it cannot be implemented under the conditions of the test. Minimum bump spacing [30: melon], adjust the other end of the electrical meter to make it contact In the second-level smaller inner lead 311 spacing [such as 3 3 // m] of the test pad 3 12 [that is, the test pad 312 of the test moves to the right], if it is measured that no current passes, then adjust the electrical continuously At the other end of the meter, contact the test pad 312 with the pitch of the inner pins 311 (from 35 to 45) with increasing width until the current flow is measured to determine the stage where the process capability can be made. Automatic bonding of the tapes of the bump pitch. In this embodiment, it can evaluate the feasibility of automatic bonding of the tapes within the range of 30, 33, 35, 38, 40, 42 and 45 // m bump pitch. However, if no current is measured during the steps of “Electrical Test” 1 4
1232306 五 發明說明（6) 過’表示該凸塊組22之該些凸塊221均未確實接合該引腳 組3 1之内引腳3 1 1，應檢查該測試晶片2 0與該測試電路薄 膜3 0之對位控制，若該測試晶片2 0邊角側之凸塊組2 2測試 結果甚差與該測試晶片2 0較中間側之凸塊組22測試結果差 異過大時〔請參閱第2圖〕’應考量該測試電路薄膜3 〇對 該測試晶片2 0之熱膨脹係數差異或是該測試晶片2 〇之長邊 長度，因此，本發明之捲帶自動接合檢測方法係具有「評 估捲帶自動接合在不同凸塊微間距之可行性」功效。 此外，在本實施例中，該測試晶片20之凸塊組22另包 含有完全電性導通之複數個凸塊225a、225b、225c，在4 , 實施例中，該些凸塊225a、225b、2 25c係設於該測試晶片〜^ 2 〇之最小凸塊間距之凸塊2 2 1之一側〔請參閱第3及6 圖〕，請參閱第5圖，而該測試電路薄膜30之引腳組31係 包含有對應於該些凸塊225a、225b、225c且電性獨立之内 引腳314a、3 14b、314c，在「接合該測試晶片與該測試電 路薄膜」13之步驟中，請參閱第6圖，該些凸塊225a、 225b、225c係與該些内引腳314a、314b、31 4c相接合，之 試塾係接觸一電源供應器，而連接該些内引腳3丨4b、3丨 後進行四點電阻量測，連接該些内引腳3 14a、3 14b之兩測 ....... 1 S ^ N d υ 1 4 〇 丄 之兩測試墊係接觸一電壓檢測計，該内引腳314b與該凸孤 225b之接合處電阻值（r)係可由該電源供應器之電流（丨）與 該電壓計（V)求得，R = V + I，因此，在適當測試條件下， 電阻值（R)之變化可為該内引腳3 14b與該凸塊22 5b之接合 耐用度之評估。1232306 Five descriptions of inventions (6) Passing 'means that none of the bumps 221 of the bump group 22 have actually joined the pins 3 1 within the pin group 3 1, the test chip 2 0 and the test circuit should be checked For the alignment control of the thin film 30, if the test result of the bump group 22 on the corner side of the test wafer 20 is very poor and the test result of the test wafer 20 on the bump side 22 of the middle side is too large (see section Figure 2] 'The test circuit film 3 〇 the thermal expansion coefficient difference of the test wafer 20 or the length of the long side of the test wafer 20 should be considered. With the feasibility of automatic bonding at different pitches of different bumps ". In addition, in this embodiment, the bump group 22 of the test wafer 20 further includes a plurality of bumps 225a, 225b, and 225c that are completely electrically conductive. In the fourth embodiment, the bumps 225a, 225b, 2 25c is located on one side of the bump 2 2 1 with the smallest bump pitch of the test wafer ~ ^ 2 〇 [see Figs. 3 and 6], please refer to Fig. 5, and the test circuit film 30 leads The pin set 31 includes the pins 314a, 3 14b, and 314c corresponding to the bumps 225a, 225b, and 225c and are electrically independent. In the step of "bonding the test chip and the test circuit film" 13, please Referring to FIG. 6, the bumps 225a, 225b, and 225c are connected to the inner pins 314a, 314b, and 31 4c. The test is to contact a power supply and connect the inner pins 3 丨 4b. After 4 and 3, four-point resistance measurement is performed. Connect two of these internal pins 3 14a and 3 14b ....... 1 S ^ N d υ 1 4 〇 丄 The two test pads are in contact with a voltage In the tester, the resistance (r) at the junction of the inner pin 314b and the convex solitary 225b can be obtained from the current (丨) of the power supply and the voltmeter (V), R = V + I Therefore, under appropriate test conditions, the change in the resistance value (R) can be an evaluation of the durability of the joint between the inner pin 3 14b and the bump 22 5b.
第10頁 1232306 五、發明說明（7) 再者，請參閱第4及7圖，本發明之測試電路薄膜3 〇係 另包含有一電性遷移檢測區32〔 electro- migration detect ing area〕，其具有兩兩交錯且不互連之梳狀線路 3 21，兩對應交錯之梳狀線路3 2 1係不相互導通且其間距係 模擬一般内引腳之間距而約介於45〜50 /zm之間，並在該些 梳狀線路3 2 1上形成一熱固性賸體4 〇，如底部填充膠體 〔underfilling material〕或填塗膠體〔p〇tting 之後進行電性遷移檢測試驗 compound 〕 一 _ — ^ W Ί 从 /TVJ w 舰…7s 狀、银 路321施加偏壓40V，其試驗條件應為濕度85RH、溫度85 〇c 並持續1 0 0 0小時，以觀察該些梳狀線路3 2 i之銅離子遷j ± ，象；另，較佳地，該測試電路薄膜3〇另包含有一剝離強、 f 測試墊33〔 peel ing strength test pad〕，該剝離強 2試墊33係具有-勉起端’以供甜央撕起，而測量出該 試塾33之抗剝離強度，因此，利用本發明之測 呷估JL f忐有效檢測捲帶自動壓合之各種製程能力，以 汗估其製程可行性。 之申請專利範圍所界定者 不脫離本發明之精神和範 屬於本發明之保護範圍▲ 、 本發明之保護範圍當視後附 為準’任何熟知此項技藝者，在 圍内所作之任何變化與修改，均Page 10 1232306 V. Description of the invention (7) Furthermore, referring to Figures 4 and 7, the test circuit film 3 of the present invention further includes an electro-migration detection area 32, which There are two interlaced and non-interconnected comb lines 3 21, and the two corresponding interlaced comb lines 3 2 1 are not conductive with each other and their pitch is similar to the distance between pins in the general range of about 45 ~ 50 / zm. And a thermosetting residue 40 is formed on the comb lines 3 2 1, such as an underfilling material or an underfilling material [electricity migration test test compound after potting] a _ — ^ W Ί Slave / TVJ w ... 7s, with a bias voltage of 40V on the silver road 321, the test conditions should be humidity 85RH, temperature 85 ° C, and last for 1000 hours to observe the comb lines 3 2 i Copper ion migration j ±, like; in addition, preferably, the test circuit film 30 additionally includes a peeling strength, f test pad 33 [peeling strength test pad], the peeling strength 2 test pad 33 has- End 'for the sweet Yang to tear, and the peel resistance of the test 塾 33 was measured Degree, therefore, the present invention using the measured estimated sipping nervous JL f effective detection volume with the various process capability of the automatic nip, in order to estimate its perspiration process feasibility. Those who are defined by the scope of the applied patent do not depart from the spirit and scope of the present invention and belong to the scope of protection of the present invention. ▲ The scope of protection of the present invention shall be subject to the appendix. Any changes and modifications made by those skilled in the art within the scope , Both
II 1232306 圓式簡單說明 【圖式簡單 第1圖··依 第2圖：依 之 第3圖：依 之 第4圖：依 之 第5圖：依 步 圖 第6圖：依 後 第7圖：依 之 說明】 照本發 照本發 測試晶 照本發 測試晶 照本發 測試電 照本發 驟後所 明之捲 明之捲 片壓合 明之捲 片之凸 明之捲 路薄膜 明之捲 提供之 照本發明之捲 測試電路薄膜 照本發明之捲 測试電路薄膜 帶自動 帶自動 面示意 帶自動 塊組局 帶自動 之上視 帶自動 測試電 帶自動 之四點 帶自動 之梳狀 接合之檢測流輕圖 接合之檢測方法， 圖； 接合之檢測方法 部示意圖； 接合之檢測方法 圖； 接合之檢測方法 路薄膜之弓丨腳組局 接合之檢測方法， 電阻量測示意®;ί合 接合之檢剛方法 β 線路局部示意圖。提供 所提供 所提供 所提供 在接合 元件符號簡單說明： 11 提供一測試晶片 提供一測試電路薄膜 接合3亥測式晶片與該 電性測試 ~ 測言式曰曰曰# 21壓 凸塊組 221凸 12 13 14 20 22 測試電路薄膜II 1232306 Simple explanation of the round form [Simplified diagram 1 ··· 2 picture: 3 picture according to: 4 picture according to: 5 picture according to step: 6 picture step by step: 7 picture after ： According to the instructions】 According to this issue, this test, this test, this test, this test, this test, this test, this test, this test, the next test, the first test, the next test, the next test, the next test, the next test The roll test circuit film of the present invention is based on the roll test circuit film of the present invention. The tape has an automatic surface, an automatic surface, an automatic block, a local band, an automatic upper video band, an automatic test, an electrical belt, an automatic four-point belt, and an automatic comb-like detection flow. Light diagram of the detection method of the diagram, diagram; Diagram of the inspection method of the diagram; Diagram of the inspection method of the diagram; The inspection method of the road film bow 丨 The method of detecting the joint of the foot, the schematic diagram of the resistance measurement ®; Partial schematic diagram of the rigid method β line. Provide a simple explanation of the provided provided bonding component symbols: 11 Provide a test wafer, provide a test circuit film, and bond the 3 test chip to the electrical test ~ Test type, say, say # 21 压 Projection block group 221 convex 12 13 14 20 22 Test circuit film
2 2 3線路 合面 塊 224斷路區 222 墊 1232306 圊式簡單說明 225a 、 225b 、 225c 凸塊 23 凸塊組 30 電路薄膜 31 引腳組 3 1 3 互連線路 3 2 1 梳狀線路 311 内引腳 312 測試墊 314a 、 314b 、 314c 内引腳 3 2 電性遷移檢測區 33剝離強度測試墊 40熱固性膠體 Φ ΦΦ2 2 3 Line junction block 224 Opening area 222 Pad 1232306 Simple description of the method 225a, 225b, 225c Bump 23 Bump group 30 Circuit film 31 Pin group 3 1 3 Interconnect line 3 2 1 Comb line 311 Internal lead Feet 312 Test pads 314a, 314b, 314c Inner pin 3 2 Electromigration detection area 33 Peel strength test pad 40 Thermoset colloid Φ ΦΦ
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