TWI617862B - Narrow bezel display module and data output device - Google Patents
Narrow bezel display module and data output device Download PDFInfo
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3685—Details of drivers for data electrodes
- G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/0426—Layout of electrodes and connections
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Abstract
本發明課題係將從驅動晶片至有效區域的邊框區域尺寸窄小化。 本發明的解決手段係資料輸出裝置具備：驅動晶片20，係配置在顯示面板10的邊框區域12；及多條訊號線31、32，一端連接於該驅動晶片20，且在鄰接於邊框區域12的有效區域11係平行地配線。邊框區域12具有：扇出區域12a，係位在從驅動晶片20與訊號線31、32之連接部至有效區域11之間；及扇入區域12b，係位在較該扇出區域12a更遠離有效區域11的位置。驅動晶片與訊號線之連接部25係設在位於驅動晶片20之有效區域11側的上邊21。多條訊號線31、32包含第1組訊號線31，其係配線成從連接部25朝向扇入區域12b側，並通過扇入區域12b及扇出區域12a而到達有效區域11。The subject of the present invention is to reduce the size of the frame area from the driving chip to the effective area. The solution of the present invention is a data output device including: a driving chip 20 that is disposed in a frame region 12 of the display panel 10; and a plurality of signal lines 31 and 32, one end of which is connected to the driving chip 20 and is adjacent to the frame region 12 The active area 11 is wired in parallel. The frame area 12 has: a fan-out area 12a located between the connection portion of the driving chip 20 and the signal lines 31 and 32 to the effective area 11; and a fan-in area 12b located farther from the fan-out area 12a The position of the effective area 11. The connection portion 25 between the driving chip and the signal line is provided on the upper side 21 on the effective area 11 side of the driving chip 20. The plurality of signal lines 31 and 32 include a first group of signal lines 31, which are routed from the connection portion 25 to the fan-in area 12b side, and reach the effective area 11 through the fan-in area 12b and the fan-out area 12a.
Description
本發明係關於液晶面板等顯示面板的邊框上的配線技術。The present invention relates to a wiring technology on a frame of a display panel such as a liquid crystal panel.
筆記型電腦或平板電腦等行動裝置市場中，一直在要求消耗電力降低及成本降低。另一方面，隨著面板解析度的提升或顯示畫質的提升，資料處理量及動作頻率有増無減，而相反地要求降低消耗電力及降低成本是一大課題。筆記型電腦或平板電腦中，對顯示面板輸入繪圖資料(Drawing Data)訊號的電路係由：負責繪圖資料本身的運算或各種運算處理或圖形處理的CPU(Central Processing Unit；中央處理單元)或GPU(Graphics Processing Unit；圖形處理單元)等處理器；以傳送自該處理器的繪圖資料作為輸入，執行顯示面板的時序控制或影像處理的時序控制器(Timing Controller，TCON)；以及以來自時序控制器的繪圖資料作為輸入，並配合顯示面板的型式而類比輸出繪圖資料的源極驅動器(Source Driver，SD)等驅動晶片，所構成。In the mobile device market such as laptops and tablets, there has been a demand for lower power consumption and lower costs. On the other hand, with the improvement of the panel resolution or the improvement of the display image quality, the amount of data processing and the operating frequency have not decreased. On the contrary, it is a major issue to reduce power consumption and reduce costs. In a notebook computer or tablet computer, a circuit for inputting drawing data signals to a display panel is composed of: a CPU (Central Processing Unit) or a GPU responsible for the calculation of the drawing data itself or various arithmetic processing or graphic processing (Graphics Processing Unit) and other processors; a timing controller (Timing Controller (TCON)) that executes timing control of a display panel or image processing by using graphics data transmitted from the processor as input; and The drawing data of the device is used as input, and a driving chip such as a source driver (SD) that outputs the drawing data is analogously outputted in accordance with the type of the display panel.
筆記型電腦或平板電腦等行動裝置中，時序控制器和源極驅動器大多是呈分離的狀態。例如，圖1所示的FHD(Full High Definition，1920×1080像素)顯示面板的情況中，大多需要1個時序控制器1及4個源極驅動器。此外，4K2K面板(解析度接近4000×2000像素的面板)的情況中，需要1個時序控制器1及8個源極驅動器的情形很多。再者，如圖1所示，將時序控制器與源極驅動器連接的FPC(Flexible Printed Cable；撓性印刷排線)需要配合使用數個源極驅動器，而隨著面板解析度的增高，組件數亦増加，因而構成成本上升的主因。而且，時序控制器與源極驅動器間雖有設置介面的必要，卻因該介面而導致電力消耗。由於這種背景因素，使圖1所示的電路構成處在難以降低成本及消耗電力的狀況。In a mobile device such as a notebook computer or a tablet computer, the timing controller and the source driver are mostly separated. For example, in the case of a FHD (Full High Definition, 1920 × 1080 pixels) display panel shown in FIG. 1, most of them require one timing controller 1 and four source drivers. In addition, in the case of a 4K2K panel (a panel having a resolution close to 4000 × 2000 pixels), there are many cases where one timing controller 1 and eight source drivers are required. Furthermore, as shown in FIG. 1, a flexible printed cable (FPC) connecting a timing controller and a source driver needs to use a plurality of source drivers, and as the panel resolution increases, the components The number also increases, which constitutes the main cause of rising costs. In addition, although it is necessary to provide an interface between the timing controller and the source driver, power consumption is caused by the interface. Because of this background factor, it is difficult to reduce the cost and power consumption of the circuit configuration shown in FIG. 1.
因此，為了減少組件數及消耗電力，如圖2及圖3所示的時序控制器及源極驅動器形成1個晶片的所謂系統驅動器(TCON＋SD)也可加以探究。圖2係顯示設有2個系統驅動器的構成，圖3則顯示系統驅動器集成為1個的構成。透過系統驅動器化，即可使組件數減少及成本降低。更進一步，由於時序控制器與源極驅動器之間不存在介面，所以消耗電力也可降低。特別是，從組件數及消耗電力降低的觀點來看，如圖3所示，可謂系統驅動器以只有一個為宜。但，系統驅動器則和以前的源極驅動器一樣安裝在液晶面板的玻璃上。繪圖資料則從處理器(CPU／GPU)直接輸入系統驅動器，或者經由eDP介面或mipi介面輸入系統驅動器。Therefore, in order to reduce the number of components and power consumption, the so-called system driver (TCON + SD) in which the timing controller and source driver shown in FIG. 2 and FIG. 3 form a single chip can also be investigated. FIG. 2 shows a structure provided with two system drivers, and FIG. 3 shows a structure integrated with one system driver. By driving the system, the number of components and costs can be reduced. Furthermore, since there is no interface between the timing controller and the source driver, power consumption can be reduced. In particular, from the viewpoint of reducing the number of components and power consumption, as shown in FIG. 3, it may be said that only one system driver is suitable. However, the system driver is mounted on the glass of the LCD panel like the previous source driver. Graphics data is input directly from the processor (CPU / GPU) to the system driver, or from the eDP interface or mipi interface to the system driver.
此處，液晶面板係以源極線與閘極線所構成。FHD面板的情況中，源極線需要1920×3(RGB)條線，閘極線則需要1080條線。源極線為將繪圖資料從源極驅動器類比輸出的線(資料線)，並隔開預定間隔地配線成互相平行。閘極線則按逐條閘極線一邊作時間性移動一邊驅動源極線的繪圖資料的控制線，其係朝和源極線正交與源極線正交的方向隔開預定間隔配線成互相平行。閘極線與源極線的各交叉點則設有顯示像素(pixel)。此外，在目前階段，源極驅動器或系統驅動器係以實裝在液晶玻璃上的方式，亦即所謂COG(Chip On the Glass；玻璃覆晶)方式為主流。Here, the liquid crystal panel is composed of a source line and a gate line. In the case of an FHD panel, the source line needs 1920 × 3 (RGB) lines, and the gate line needs 1080 lines. The source line is a line (data line) for analogously outputting drawing data from the source driver, and is wired in parallel to each other at predetermined intervals. The gate line is a control line that drives the drawing data of the source line while moving in time with each gate line. It is wired at predetermined intervals in a direction orthogonal to the source line and orthogonal to the source line. Parallel to each other. Each intersection of the gate line and the source line is provided with a display pixel. In addition, at the current stage, a source driver or a system driver is mainly mounted on a liquid crystal glass, that is, a so-called COG (Chip On the Glass) method.
液晶面板(顯示面板)源極線的模型揭示於圖4。液晶面板係分為屬於源極驅動器實裝區域的扇出區域(Fan out Area)、及液晶像素作矩陣排列的有效區域(Active Area)。從該有效區域至包含扇出區域的玻璃模組邊緣部分係稱為液晶面板的邊框區域，該邊框區域較狹窄者即被認為商品價值較高。A model of a source line of a liquid crystal panel (display panel) is disclosed in FIG. 4. The liquid crystal panel is divided into a fan out area belonging to a source driver mounting area and an active area in which liquid crystal pixels are arranged in a matrix. From the effective area to the edge of the glass module including the fan-out area, it is called the bezel area of the liquid crystal panel, and the narrower bezel area is considered to have higher product value.
如圖4所示，設有4個源極驅動器的情況中，1個源極驅動器進行驅動所需的COG上源極線配線數只要少數即可。例如，FHD面板的情況中，源極線有1920×3(RGB)＝5860條，而源極驅動器設有4個的情況中，每1個源極驅動器就要驅動1440條源極線。例如，專利文獻1中，即揭示了設有4個源極驅動器的構成。另一方面，如圖2、圖3及圖5所示，時序控制器(TCON)及源極驅動器(SD)加以整合時，或者源極驅動器進行集成化而組件數為1個或2個時，1個源極驅動器需要驅動的COG上源極線配線數就增多，而產生邊框區域的高度變大的問題。As shown in FIG. 4, in a case where four source drivers are provided, only a small number of source line wirings on the COG are required for one source driver to drive. For example, in the case of an FHD panel, there are 1920 × 3 (RGB) = 5860 source lines, and when there are four source drivers, each source driver must drive 1,440 source lines. For example, Patent Document 1 discloses a configuration in which four source drivers are provided. On the other hand, when the timing controller (TCON) and the source driver (SD) are integrated as shown in Figs. 2, 3, and 5, or when the source driver is integrated and the number of components is one or two As a result, the number of source line wirings on the COG to be driven by one source driver increases, and a problem arises that the height of the frame region becomes large.
此處，參照圖6就顯示面板(液晶面板)邊框區域的構成加以說明。邊框區域的中心具有時序控制器與源極驅動器已施以整合的驅動晶片，源極線即從驅動晶片上邊向有效區域有效區域進行布線配線。而且，源極線的布線配線一般是使全部的線以一定角度θ從最左端或者最右端的線向面板的中心線實施布線配線。從該驅動晶片與源極線之連接部至有效區域有效區域之間的區域，在本案說明書中係定義為「扇出區域」，圖中，該扇出區域的高度係以H 1來表示。再者，邊框區域中存在有位於較該扇出區域更遠離有效區域有效區域的區域，在本案說明書中，該區域係定義為「扇入區域」。該扇入區域中，從晶片下邊向左右延伸的閘極訊號驅動線係朝面板的左右方向實施布線配線，邊框區域的左右部分則配置有測試墊。此外，扇入區域中配置有源極線的測試線或其測試墊，甚至進一步配置有閘極驅動控制訊號線或其測試墊等。該扇入區域的高度在圖中係以H 2來表示。上述H 1＋H 2的值即為邊框區域整體的高度。本發明的目的即在提供得以減少該邊框區域(特別是以H 1表示的扇出區域)之高度的技術。 先前技術文獻 專利文獻 Here, the configuration of a frame region of a display panel (liquid crystal panel) will be described with reference to FIG. 6. In the center of the frame area, there is a driving chip integrated with the timing controller and the source driver. The source lines are wired from the top of the driving chip to the effective area of the effective area. In addition, as for the wiring of the source lines, all the wires are generally wired at a certain angle θ from the leftmost or rightmost line to the center line of the panel. From the connecting portion of the driving source lines of the wafer to a region between the active region active area is defined as a line "fanout region" in the specification of the figure, the height of the fan-out lines in the region represented by H 1. Furthermore, there is an area in the border area that is located farther from the effective area than the fan-out area. In the description of this case, this area is defined as a "fan-in area." In the fan-in area, the gate signal driving wires extending from the lower side of the chip to the left and right are wired to the left and right directions of the panel, and the left and right portions of the frame area are provided with test pads. In addition, in the fan-in area, a test line or a test pad of the source electrode line is configured, and a gate drive control signal line or a test pad thereof is further configured. The height of the fan-in area is represented by H 2 in the figure. The above-mentioned value of H 1 + H 2 is the height of the entire frame region. An object of the present invention is to provide a technique capable of reducing the height of the frame region (particularly, the fan-out region represented by H 1 ). Prior art literature patent literature
[專利文獻1] 日本特開2005－31332號公報[Patent Document 1] Japanese Patent Laid-Open No. 2005-31332
如前所述，如圖2、圖3、及圖5所示，時序控制器(TCON)與源極驅動器(SD)施以整合時，或者源極驅動器進行集成化而組件數為1個或2個時，1個源極驅動器進行驅動所需的COG上源極線配線數會增多，有邊框區域高度變大的問題。特別是，此種情況中，邊框區域之中以H 1表示的扇出區域的高度較難以刪減。 As mentioned above, as shown in Figures 2, 3, and 5, when the timing controller (TCON) is integrated with the source driver (SD), or the source driver is integrated and the number of components is one or In the case of two, the number of source line wirings on the COG required for one source driver to drive increases, and there is a problem that the height of the frame area becomes large. In particular, in this case, the height of the fan-out area indicated by H 1 among the frame areas is difficult to delete.
此處，參照圖7，舉傳統液晶面板的配線構造為例來說明求取邊框區域高度H 1的方法。首先，假設有效區域源極線的配線節距為P pix、扇出區域源極線的配線節距為Pw，驅動晶片上源極線的連接部(輸出墊) 節距為P bp，從驅動晶片最邊端的連接部至顯示面板最邊端的源極線為止的距離為D x。此處，由於P pix＞P bp，連接驅動晶片與有效區域的源極線的一部分必須以一定角度使其傾斜。位於扇出區域最邊端的源極線配線與、有效區域中和源極線延伸方向正交的正交方向之方向軸的角度θ，係以θ＝sin－1(P w／P pix)表示。於是，區域邊框中扇出區域的高度H 1即為H 1＝D x・tanθ＝D x・tan(sin－1(P w／P pix))。 Here, referring to FIG. 7, a method of obtaining the height H 1 of the frame region will be described by taking a wiring structure of a conventional liquid crystal panel as an example. First, suppose the wiring pitch of the source line in the active area is P pix , the wiring pitch of the source line in the fan-out area is Pw, and the pitch of the connection portion (output pad) of the source line on the driver chip is P bp The distance from the connecting portion at the extreme edge of the chip to the source line at the extreme edge of the display panel is D x . Here, since P pix > P bp , a part of the source line connecting the driving chip and the active region must be inclined at a certain angle. The angle θ of the direction axis of the source line wiring at the extreme end of the fan-out area and the orthogonal direction orthogonal to the extension direction of the source line in the effective area is expressed by θ = sin-1 (P w / P pix ) . Therefore, the height H 1 of the fan-out area in the area frame is H 1 = D x · tanθ = D x · tan (sin-1 (P w / P pix )).
依此方式，即可知H 1的數值係取決於D x，該D x值越大，H 1的數值亦越大。而且可知，θ越大，H 1的數值也越大。還有，P w越大，H 1的數值也越大。因P pix係由顯示面板尺寸及解析度所決定的值，故在實施源極線配線之際，P pix可說是無法改變的固定值。P pix為一定的情況中，P w越大，θ也越大，H 1也跟著變大。依此方式，θ即屬於由P w及P pix所決定的值。 In this manner, known to a line depends on the value H D x, D x larger the value, the greater the value of H 1 also. Further, it can be seen that the larger θ is, the larger the value of H 1 is. The larger the value of P w is, the larger the value of H 1 is. Since P pix is a value determined by the size and resolution of the display panel, P pix can be said to be a fixed value that cannot be changed when the source wiring is implemented. When P pix is constant, the larger P w is, the larger θ is, and H 1 also increases. In this way, θ is a value determined by P w and P pix .
例如，13.3吋的FHD面板中，假設P w＝7μm時，在源極驅動器為4個構成的情況中，係形成H 1＝1.5mm，但源極驅動器為2個構成的情況中，則形成H 1＝3mm，而源極驅動器為1個構成的情況中，即形成H 1＝6mm。H 1的尺寸係由晶片最邊端側的源極線與有效區域之距離Dx、及角度θ所決定。亦即，源極驅動器的集成度越高，H 1的尺寸就越大，而在源極驅動器為1個構成的情況中，H 1的尺寸達到最大。依此方式，組件數減少時，邊框區域(特別是扇出區域)的尺寸就變大，從而存在著商品價值降低的大問題。 For example, in a 13.3-inch FHD panel, when P w = 7 μm, when the source driver has four configurations, H 1 = 1.5 mm is formed, but when the source driver has two configurations, it is formed. In a case where H 1 = 3 mm and the source driver has a single configuration, H 1 = 6 mm is formed. The size of H 1 is determined by the distance Dx and the angle θ between the source line and the effective region on the extreme side of the wafer. That is, the higher the degree of integration of the source driver, H a greater size, in the source driver is composed of a case where, H is a maximum size. In this way, when the number of components is reduced, the size of the frame area (especially the fan-out area) becomes larger, and there is a large problem that the value of the product is reduced.
對於這點，乃存在有扇出區域尺寸H 1必須降至4mm以下的要求。但，如前所述，H 1的尺寸係θ越大其值越大，而且θ係由P w及P pix所決定的值，而P pix為固定值，無法加以調整，此外，P w過於狹窄時，鄰接的源極線間會發生所謂串擾(cross-talk)等問題，因此P w無法設在一定值以下。而且，在玻璃配線的製造上，因訊號配線難以設在一定寬度以下，故θ值也有限制，將θ減小以縮減H 1尺寸的作法有其極限。 For this, there is a requirement that the size H 1 of the fan-out area must be reduced to 4 mm or less. However, as mentioned above, the larger the size of H 1 is, the larger the value of θ is. The value of θ is determined by P w and P pix . P pix is a fixed value and cannot be adjusted. In addition, P w is too large. When it is narrow, problems such as cross-talk occur between adjacent source lines, so P w cannot be set below a certain value. In addition, in the manufacture of glass wiring, since the signal wiring is difficult to be set below a certain width, the value of θ is also limited, and the method of reducing θ to reduce the size of H 1 has its limit.
因此，本發明之目的即在於提供縱使在源極驅動器等驅動晶片的集成度提高的情況下，從驅動晶片至有效區域的邊框區域尺寸也可窄小化的源極線配線方式。Therefore, an object of the present invention is to provide a source line wiring method in which the size of a frame region from a driver chip to an effective region can be reduced even when the integration degree of a driver chip such as a source driver is improved.
本案發明人等針對上述問題的解決手段熱切探討的結果，獲得了以下的認知，亦即，透過有效運用邊框區域中較扇出區域遠離有效區域位置的扇入區域，使連接於驅動晶片輸出端的訊號線的一部分以通過扇入區域後朝向有效區域的方式實施配線，即可超越傳統設計上的限制，使邊框區域尺寸得以窄小化。然後，本案發明人等又想到，若能根據上述認知，即可解決傳統技術的問題，從而完成本發明。以下即針對本發明的構成具體加以說明。As a result of earnest discussions on the solutions to the above-mentioned problems, the inventors of the present case have obtained the following knowledge, that is, by effectively using a fan-in area in the frame area that is farther from the effective area than the fan-out area, the Part of the signal line is wired in such a way that it passes through the fan-in area and faces the effective area, which can exceed the traditional design restrictions and reduce the size of the frame area. Then, the inventors of the present case thought that if the above-mentioned cognition can be used, the problems of the conventional technology can be solved, and the present invention can be completed. The structure of the present invention will be specifically described below.
本發明的第1面向係關於用以向液晶面板等顯示面板輸出繪圖資料的資料輸出裝置。本發明的資料輸出裝置包括驅動晶片及連接於該驅動晶片的多條源極線。驅動晶片係配置在顯示面板的邊框區域。因該邊框區域一般係以玻璃形成，故如本發明般的構成可稱為COG(Chip On the Glass)方式等(但，本發明並不限定在邊框區域為玻璃的情形)。這種COG方式和基底薄膜形成有連接配線的COF(Chip On the Film；薄膜覆晶)方式有明確的區別。再者，驅動晶片可為源極驅動器，也可為閘極驅動器，也可為源極驅動器與時序控制器整合所得的所謂系統驅動器。本發明中，驅動晶片以在邊框區域僅配置1個為佳，但也不限定於此，也可在邊框區域配置複數個(例如2至4個)。而且，多條訊號線係一端連接在驅動晶片，通過邊框區域，再於鄰接邊框區域的有效區域施行平行配線。訊號線可為連接於源極驅動器的源極線，也可為連接於閘極驅動器的閘極線。A first aspect of the present invention relates to a data output device for outputting drawing data to a display panel such as a liquid crystal panel. The data output device of the present invention includes a driving chip and a plurality of source lines connected to the driving chip. The driving chip is arranged in a frame region of the display panel. Since the frame region is generally formed of glass, a structure like the present invention may be referred to as a COG (Chip On the Glass) method or the like (however, the present invention is not limited to a case where the frame region is glass). There is a clear difference between this COG method and a COF (Chip On the Film) method in which connection wiring is formed on the base film. Furthermore, the driving chip may be a source driver, a gate driver, or a so-called system driver obtained by integrating the source driver and the timing controller. In the present invention, it is preferable that only one drive chip be arranged in the frame region, but it is not limited to this, and a plurality of (for example, 2 to 4) may be arranged in the frame region. Moreover, one end of a plurality of signal lines is connected to the driver chip, and parallel wiring is performed through the frame area and then in the effective area adjacent to the frame area. The signal line may be a source line connected to the source driver, or a gate line connected to the gate driver.
此處，邊框區域具有扇出區域及扇入區域。扇出區域係指從驅動晶片與訊號線的連接部(亦即，驅動晶片的輸出端)至有效區域之間的區域。再者，扇入區域係指位在較扇出區域遠離有效區域的區域。如圖6所示，扇入區域一般配置有源極線的測試線或其測試墊，甚至配置有閘極驅動控制訊號線或其測試墊等。在此情況中，驅動晶片與訊號線的連接部係設在位於驅動晶片之有效區域側的上邊。而且，多條訊號線至少包含第1組訊號線，其係配線成從上述連接部向扇入區域側，依序通過該扇入區域及扇出區域而到達有效區域。Here, the border region has a fan-out region and a fan-in region. The fan-out area refers to the area from the connection between the driver chip and the signal line (ie, the output end of the driver chip) to the effective area. Moreover, the fan-in area refers to an area located farther from the effective area than the fan-out area. As shown in FIG. 6, the fan-in area is generally configured with a test line or a test pad of the source electrode line, and even a gate drive control signal line or a test pad thereof. In this case, the connection portion between the driving chip and the signal line is provided on the upper side of the effective region side of the driving chip. Moreover, the plurality of signal lines include at least the first group of signal lines, which are wired from the above-mentioned connection portion to the fan-in area side, and sequentially pass through the fan-in area and the fan-out area to reach the effective area.
依上述構成，本發明係在配線構造上作了巧思，使多條訊號線的一部分(第1組訊號線)通過邊框區域的扇入區域，將傳統配線方式中未曾使用於訊號線配線的扇入區域活用作為訊號線的配線區域。依此方式，藉由將多條訊號線的一部分配線成通過扇入區域的方式，即可使邊框區域的尺寸，特別是扇出區域的尺寸窄小化。According to the above structure, the present invention makes a clever idea in the wiring structure, so that a part of the plurality of signal lines (the first group of signal lines) passes through the fan-in area of the frame area, and the traditional wiring method has not been used for signal line wiring. The fan-in area is used as a wiring area for signal lines. In this way, by wiring a part of the plurality of signal lines to pass through the fan-in area, the size of the frame area, especially the size of the fan-out area can be narrowed.
特別是，本發明係將驅動晶片與訊號線(至少第1組訊號線)的連接部設在驅動晶片的上邊。亦即，驅動晶片的形狀具有：位在有效區域側的上邊、位在該上邊之相反側的下邊、連結這些上邊與下邊的左邊、右邊等至少四個邊。例如，驅動晶片為形成以上邊及下邊為長邊，以左邊及右邊為短邊的橫向較長型的矩形。而且，使驅動晶片與訊號線的連接部設在驅動晶片之四邊中的上邊。依此方式，本發明中，多條訊號線係構成為包含第1組訊號線，其係以從設在驅動晶片之上邊的連接部朝向扇入區域側再通過扇入區域及扇出區域而到達有效區域的方式實施配線。依此方式，藉由將從驅動晶片之上邊拉出的第1組訊號線暫且先轉向扇入區域，且通過扇入區域及扇出區域的方式迂迴後，再以導向有效區域的方式實施配線，即可使邊框區域(特別是扇出區域)的尺寸窄小化。亦即，如本發明般的COG方式的顯示器中，因必須將驅動晶片配置在邊框區域，故在邊框窄化方面會有設計上的極限，但若依本發明，即使是COG方式的顯示器，仍可超越這種設計上的極限，而實現邊框區域的窄小化。In particular, in the present invention, the connection portion between the driving chip and the signal line (at least the first group of signal lines) is provided on the driving chip. That is, the shape of the driver chip has at least four sides, such as an upper side located on the effective area side, a lower side located on the opposite side of the upper side, and left and right sides connecting these upper and lower sides. For example, the driving chip is a horizontally long rectangle with the upper and lower sides being long sides and the left and right sides being short sides. Further, the connection portions between the driving chip and the signal lines are provided on the upper sides of the four sides of the driving chip. In this way, in the present invention, the plurality of signal lines are configured to include the first group of signal lines, which are directed from the connection portion provided on the upper side of the driving chip toward the fan-in area side and then pass through the fan-in area and the fan-out area. Implement wiring so that it reaches the effective area. In this way, the first set of signal wires pulled from the top of the driver chip is temporarily diverted to the fan-in area first, and after detouring through the fan-in area and the fan-out area, the wiring is implemented in a way that guides the effective area. , The size of the frame area (especially the fan-out area) can be reduced. That is, in the display of the COG system like the present invention, since the driving chip must be arranged in the frame area, there is a design limit in narrowing the frame. However, according to the present invention, even the display of the COG system, The design limit can still be exceeded, and the frame area can be narrowed.
另外，雖然也可考慮將訊號線連接到驅動晶片的左右短邊或下邊，但在該情況下，邊框窄化的效果會有限制，無法像本發明將訊號線連接到驅動晶片上邊的配線構造那樣使邊框尺寸窄小化。亦即，為了使邊框窄化效果發揮到最大限度，如本發明的方式，將連接部設在驅動晶片之上邊，並使自該連接部拉出的訊號線朝扇出區域迂迴的配線結構乃至為重要。In addition, although it is also conceivable to connect the signal line to the left and right short sides or the lower side of the driver chip, in this case, the effect of narrowing the frame will be limited, and the wiring structure for connecting the signal line to the driver chip cannot be used in the present invention. That narrows the frame size. That is, in order to maximize the narrowing effect of the frame, as in the method of the present invention, the connection portion is provided on the driver chip, and the signal line drawn from the connection portion is routed to the fan-out area and the wiring structure is even Is important.
本發明中，多條訊號線以再包含第2組訊號線為佳，該第2組訊號線係配線成僅通過邊框區域的扇出區域再到達有效區域。依此方式，即和傳統配線方式同樣地，透過設置僅通過扇出區域的訊號線，將扇出區域及扇入區域的兩者有效加以運用，使扇出區域尺寸的窄小化得以更有效率地實現。 In the present invention, it is preferable that the plurality of signal lines further include a second group of signal lines, and the second group of signal lines are wired to pass through the fan-out area of the border area and then reach the effective area. In this way, similar to the traditional wiring method, by setting up signal lines that only pass through the fan-out area, both the fan-out area and the fan-in area are effectively used to make the size of the fan-out area narrower. Efficiently.
本案說明書中，訊號線在有效區域的延伸方向係定義為「延伸方向」(圖中的y軸方向)，而與該延伸方向正交的方向則定義為「正交方向」(圖中的x軸方向)。於此情況下，在有效區域中，較佳為，以朝正交方向看，第1組訊號線係位在第2組訊號線外側的2個位置，而且，朝正交方向看，第2組訊號線係位在第1組訊號線所在的前述2個位置之間。依此方式，位於正交方向兩外側的第1組訊號線係配線成暫先通過扇入區域後，再到達有效區域；位於正交方向中央的第2組訊號線則配線成僅通過扇出區域就到達有效區域，使由扇出區域及扇入區域組成的邊框區域的空間可有效率地加以利用。 In the description of this case, the extension direction of the signal line in the effective area is defined as "extension direction" (the y-axis direction in the figure), and the direction orthogonal to the extension direction is defined as the "orthogonal direction" (x in the figure) Axis direction). In this case, in the effective area, it is preferable that the first group of signal lines is located at two positions outside the second group of signal lines when viewed in the orthogonal direction, and when viewed in the orthogonal direction, the second group The group signal line is located between the aforementioned two positions where the first group signal line is located. In this way, the first group of signal lines located on the two outer sides of the orthogonal direction are routed to temporarily pass through the fan-in area and then reach the effective area; the second group of signal lines located at the center of the orthogonal direction are routed to pass through the fan-out only. The area reaches the effective area, so that the space of the border area composed of the fan-out area and the fan-in area can be efficiently used.
本發明中，第1組訊號線具有第1部至第4部。第1部係以其與驅動晶片的連接部為起點，朝離開有效區域的方向配線的部位。第2部係連接於第1部，在扇入區域朝正交方向配線的部位。另外，第2部較佳為在扇入區域中與正交方向平行延伸，但並非限定於此，即使多少有些傾斜，只要朝正交方向延伸即可。第3部係銜接於第2部，並從扇入區域通過扇出區域朝接近有效區域的方向配線的部位。第4部係銜接於第3部，再配線於有效區域上的部位。由於透過以上述第1部至第4部構成第1組訊號線，得以最短方式到達有效區域，故可刪減第1組訊號線的配線成本。 In the present invention, the first group of signal lines includes first to fourth sections. The first part is a part where the wiring is made in a direction away from the effective area, starting from the connection part with the driving chip. The second part is a part connected to the first part, and is wired in an orthogonal direction in the fan-in area. In addition, the second part preferably extends parallel to the orthogonal direction in the fan-in area, but is not limited to this. Even if it is slightly inclined, it may be extended in the orthogonal direction. The third part is a part which is connected to the second part and is wired from the fan-in area through the fan-out area toward the effective area. The fourth part is connected to the third part, and is then wired to the effective area. Since the first group of signal lines is constituted by the first to fourth parts, the effective area can be reached in the shortest way, so the wiring cost of the first group of signal lines can be reduced.
本發明中，驅動晶片較佳為使連接部間的節距較有效區域中的訊號線間節距狹窄。在此情況中，第2組訊號線中的至少一部分具有以既定角度對延伸方向及正交方向傾斜的方式配線的傾斜部。此外，第1組訊號線的第3部係以既定角度對正交方向傾斜的方式實施配線。此時，第1組訊號線之第3部的傾斜角度θ 1較佳為大於第2組訊號線之傾斜部的傾斜角度θ 2(θ 2＞θ 1)。依此方式，透過將第1組訊號線實施配線，即可有效實現扇出區域尺寸的窄小化。 In the present invention, it is preferable that the driving chip has a narrow pitch between signal lines in a region where the pitch between the connecting portions is more effective. In this case, at least a part of the second group of signal lines has an inclined portion that is wired such that the extending direction and the orthogonal direction are inclined at a predetermined angle. In addition, the third part of the first group of signal wires is wired so that the orthogonal direction is inclined at a predetermined angle. At this time, the inclination angle θ 1 of the third portion of the first group of signal lines is preferably larger than the inclination angle θ 2 of the inclined portion of the second group of signal lines (θ 2 > θ 1 ). In this way, by implementing the wiring of the first group of signal wires, the size of the fan-out area can be effectively reduced.
本發明中，在正交方向最靠內側的連接部中連接於驅動晶片的第1組訊號線，係在有效區域中配線於正交方向最靠外側。而且，在正交方向最靠外側的連接部中連接於驅動晶片的第1組訊號線係在有效區域中配線在正交方向的最靠內側。如前所述，本發明中，第1組訊號線係局部地以和驅動晶片之連接端為起點，且延伸於有效區域的相反方向。依上述構成的方式，有關於第1組訊號線，藉由在邊框區域連接於驅動晶片越靠內側的輸出端，在有效區域則配置在越靠外側的位置，即可避免多條第1組訊號線發生混線(交叉)的情形(參照圖11)。In the present invention, the first group of signal lines connected to the driving chip in the connection portion located most inward in the orthogonal direction is routed to the outside most in the orthogonal direction in the effective area. Furthermore, the first group of signal wires connected to the driving chip in the outermost connection portion in the orthogonal direction is the innermost portion of the wiring in the orthogonal direction in the effective area. As mentioned above, in the present invention, the first group of signal lines locally starts from the connection end with the driving chip and extends in the opposite direction of the effective area. According to the above structure, regarding the first group of signal lines, by connecting the output end closer to the inner side of the driving chip in the frame area and arranging the outer side in the effective area, multiple first group can be avoided. Signal lines are mixed (crossed) (see Figure 11).
本發明的第2面向係關於顯示模組。本發明的顯示模組包括上述第1面向的資料輸出裝置及顯示面板。另外，如前所述，顯示面板具有：配置有驅動晶片的邊框區域；及鄰接於該邊框區域，而多條訊號線係平行地配線的有效區域。A second aspect of the present invention relates to a display module. A display module of the present invention includes the first-oriented data output device and a display panel. In addition, as described above, the display panel includes: a frame region in which a driving chip is arranged; and an effective region adjacent to the frame region, and a plurality of signal lines are wired in parallel.
若依本發明，即使在驅動晶片的集成度已提高的情況中，從驅動晶片至有效區域的邊框區域尺寸也可窄小化。According to the present invention, even in a case where the integration degree of the driving chip has been improved, the size of the frame region from the driving chip to the effective region can be reduced.
以下，使用附圖就本發明的實施方式加以說明。本發明並非限定在下文說明的方式，而是包含本行業者在自明的範圍內可自下文所述方式作適當改變者。本發明可將下文說明的各實施方式作適當的組合，各實施方式也可單獨利用。 另外，本案說明書中，所稱「A至B」係指「A以上B以下」的情況。Hereinafter, embodiments of the present invention will be described using the drawings. The present invention is not limited to the methods described below, but includes those skilled in the art who can make appropriate changes from the methods described below within the scope of self-evident. In the present invention, the embodiments described below can be appropriately combined, and the embodiments can be used independently. In addition, in the description of this case, "A to B" refers to a case where "A is higher than A and B is lower".
圖8係揭示本發明顯示模組1的較佳形態方式。基本上，顯示模組1由包含顯示面板10、驅動晶片20、多條源極線(訊號線)31、32、及閘極訊號驅動線41所構成。顯示面板10的例子有液晶面板或有機EL面板。此外，圖8所示例子中，驅動晶片20係時序控制器(TCON)與源極驅動器(SD)業已整合者，其負責將繪圖資料輸出到源極線31、32的功能、及控制該繪圖資料之輸出時序的功能。但，也可使驅動晶片20僅單只具備源極驅動器的功能，時序控制器則可另外設置。源極線31、32及閘極訊號驅動線41係連接至驅動晶片20的輸出端。閘極訊號驅動線41則連接於未圖示的閘極驅動器。另外，圖8所示的例子中，由於驅動晶片20係擔負擔時序控制器及源極驅動器雙方兩者的功能，故該驅動晶片20連接有閘極訊號驅動線4。但，驅動晶片20僅作為提供源極驅動器功能的情形中時，閘極訊號驅動線41只要連接於另行設置的時序控制器即可。FIG. 8 illustrates a preferred embodiment of the display module 1 of the present invention. Basically, the display module 1 includes a display panel 10, a driving chip 20, a plurality of source lines (signal lines) 31, 32, and a gate signal driving line 41. Examples of the display panel 10 are a liquid crystal panel or an organic EL panel. In addition, in the example shown in FIG. 8, the driver chip 20 series timing controller (TCON) and the source driver (SD) have been integrated, and are responsible for the function of outputting drawing data to the source lines 31 and 32 and controlling the drawing. Data output timing function. However, the driving chip 20 may be provided with only the function of the source driver, and the timing controller may be separately provided. The source lines 31 and 32 and the gate signal driving line 41 are connected to the output terminal of the driving chip 20. The gate signal driving line 41 is connected to a gate driver (not shown). In the example shown in FIG. 8, the driver chip 20 is responsible for both the timing controller and the source driver. Therefore, the driver chip 20 is connected to the gate signal driving line 4. However, in a case where the driving chip 20 is provided only as a source driver function, the gate signal driving line 41 only needs to be connected to a timing controller provided separately.
上述的顯示模組1中，也可將包含驅動晶片20及源極線31、32者視為資料輸出裝置。亦即，也可將資料輸出裝置(驅動晶片20及源極線31、32)從顯示模組1分離，而僅製造或販售該資料輸出裝置。本發明的資料輸出裝置係在例如筆記型電腦或平板電腦中，作為將類比影像資料輸出到顯示面板的電路功能。In the display module 1 described above, those including the driving chip 20 and the source lines 31 and 32 may be regarded as a data output device. That is, the data output device (the driving chip 20 and the source lines 31 and 32) may be separated from the display module 1, and only the data output device may be manufactured or sold. The data output device of the present invention is, for example, a notebook computer or a tablet computer, and functions as a circuit for outputting analog video data to a display panel.
顯示面板10一般係由源極線、閘極線、及顯示像素所構成。源極線係在以玻璃等構成的面板基板上隔開預定間隔彼此平行地設置多條。閘極線則在相同的面板基板上沿著與源極線正交的方向隔開預定間隔彼此平行地設置多條。顯示像素係設在源極線與閘極線的各交叉點。各顯示像素連接有作為開關元件的TFT(Thin Film Transistor；薄膜電晶體)。例如，FHD液晶面板的情況中，源極線需要1920×3(RGB)條線，閘極線則需要1080條線。The display panel 10 generally includes a source line, a gate line, and display pixels. A plurality of source lines are provided on a panel substrate made of glass or the like in parallel with each other at predetermined intervals. The gate lines are provided on the same panel substrate in parallel with each other at predetermined intervals in a direction orthogonal to the source lines. The display pixels are provided at the intersections of the source line and the gate line. Each display pixel is connected to a TFT (Thin Film (R) Transistor) as a switching element. For example, in the case of an FHD liquid crystal panel, the source line needs 1920 × 3 (RGB) lines, and the gate line needs 1080 lines.
源極驅動器(驅動晶片20)為用以驅動顯示面板之源極線的電路。源極驅動器係連接於多條源極線，藉以對各源極線施加驅動電壓(調階顯示電壓)。源極驅動器也可設在以玻璃等構成的面板基板上。本發明的顯示模組雖然也可對一個顯示面板裝設複數個源極驅動器，但在組件數刪減及消耗電力刪減的觀點上，以一個顯示面板僅裝設一個源極驅動器12較合適。此外，顯示模組也可具備用以驅動顯示面板閘極線的閘極驅動器，惟其圖示已予省略。閘極驅動器係將使TFT導通(ON)的掃描訊號依序施加於各閘極線。操作訊號藉由閘極驅動器施加於閘極線，使TFT形成ON狀態，而驅動電壓從源極驅動器施加於源極線時，電荷即儲存在位於各交叉點的顯示元件中。藉此效應，顯示元件的透光率根據施加在源極線的驅動電壓而發生變化，經由顯示元件進行影像顯示。The source driver (the driving chip 20) is a circuit for driving the source lines of the display panel. The source driver is connected to a plurality of source lines, so that a driving voltage (step display voltage) is applied to each source line. The source driver may be provided on a panel substrate made of glass or the like. Although the display module of the present invention can also install a plurality of source drivers on a display panel, from the viewpoint of reducing the number of components and reducing power consumption, it is more appropriate to install only one source driver 12 on a display panel. . In addition, the display module may also be provided with a gate driver for driving the gate line of the display panel, but its illustration has been omitted. The gate driver sequentially applies a scanning signal that turns on the TFT to each gate line. The operation signal is applied to the gate line by the gate driver, so that the TFT is turned on, and when the driving voltage is applied to the source line from the source driver, the charges are stored in the display elements located at the intersections. With this effect, the light transmittance of the display element changes according to the driving voltage applied to the source line, and an image is displayed through the display element.
再者，圖11中，係將驅動晶片20(源極驅動器)的構成簡化並放大顯示。如圖11所示，驅動晶片20的形狀具有：位於有效區域側的上邊21、位於該上邊21之相反側的下邊22、連結這些上邊21與下邊22的左邊23、右邊24等至少四個邊。圖示的例子中，驅動晶片20係以上邊21及下邊22為長邊，左邊23及右邊24為短邊，而形成橫向長型的矩形。但，驅動晶片20的形狀並非限定於此，也可設成角部呈圓弧狀的大致四角形、角部切除的大致四角形(八角形)、或其他多角形。此外，驅動晶片20的左右短邊(左邊23–右邊24)相較於上下長邊(上邊21–下邊22)通常非常短。例如，長邊：短邊的比例為10：1至40：1或20：1至30：1左右。具體而言，上下長邊為30mm左右，左右短邊則為1mm左右。驅動晶片20更具有和訊號線(源極線)連接用的連接部25(連接端子)。例如圖8至圖11所示，驅動晶片和訊號線的連接部25係配置在驅動晶片的上邊21。圖示的例子中，全部的連接部25係位在驅動晶片的上邊21。惟，至少後述的第1組源極線31和驅動晶片20的連接部25若配置在驅動晶片的上邊21，則例如後述的第2組源極線32和驅動晶片20的連接部25即可配置在驅動晶片的下邊22。In addition, in FIG. 11, the structure of the driving chip 20 (source driver) is simplified and enlarged. As shown in FIG. 11, the shape of the driving chip 20 includes at least four sides such as an upper side 21 on the effective area side, a lower side 22 on the opposite side of the upper side 21, a left side 23 and a right side 24 connecting the upper side 21 and the lower side 22. . In the example shown in the figure, the upper side 21 and the lower side 22 of the driving chip 20 are long sides, and the left side 23 and the right side 24 are short sides to form a horizontally long rectangle. However, the shape of the driving wafer 20 is not limited to this, and it may be provided in a substantially quadrangular shape with arc-shaped corners, a substantially quadrangular (octagonal) shape with cut corners, or other polygons. In addition, the left and right short sides (the left side 23 to the right side 24) of the driving chip 20 are usually very short compared to the upper and lower long sides (the upper side 21 to the lower side 22). For example, the ratio of long side to short side is about 10: 1 to 40: 1 or 20: 1 to 30: 1. Specifically, the upper and lower long sides are about 30 mm, and the left and right short sides are about 1 mm. The driving chip 20 further includes a connection portion 25 (connection terminal) for connection to a signal line (source line). For example, as shown in FIG. 8 to FIG. 11, the connecting portion 25 of the driving chip and the signal line is arranged on the upper side 21 of the driving chip. In the example shown in the figure, all the connecting portions 25 are located on the upper side 21 of the driving chip. However, if at least the connection portion 25 of the first group of source lines 31 and the driver chip 20 described below is disposed on the top 21 of the driver chip, for example, the connection portion 25 of the second group of source lines 32 and the driver chip 20 described later may be It is arranged below the driver chip 22.
如圖8所示，顯示面板10係劃分為有效區域有效區域11及邊框區域12。有效區域有效區域11為多條多條源極線與多條多條閘極線相交叉，且在其各交叉點設有顯示元件的區域。影像係顯示在該有效區域有效區域11。另一方面，邊框區域12則為配置有驅動晶片20的區域，連接於驅動晶片20之輸出端的各種源極線31、32則配線成向有效區域有效區域11連結。由於該邊框區域12並非顯示影像的部分，故要求其尺寸儘量窄小化。因邊框區域12一般是以玻璃形成，故將在邊框區域12配置驅動晶片20的構成稱為COG(Chip On the Glass；玻璃覆晶)方式。此種COG方式與在基底薄膜形成連接配線的COF(Chip On the Film；薄膜覆晶)方式有明確區別。As shown in FIG. 8, the display panel 10 is divided into an effective area, an effective area 11 and a frame area 12. Effective area The effective area 11 is an area where a plurality of source lines intersect with a plurality of gate lines, and display elements are provided at each intersection thereof. The video is displayed in the effective area effective area 11. On the other hand, the frame region 12 is a region where the driving chip 20 is arranged, and various source lines 31 and 32 connected to the output terminal of the driving chip 20 are wired to be connected to the effective region 11. Since the frame region 12 is not a part where an image is displayed, its size is required to be as small as possible. Since the frame region 12 is generally formed of glass, a configuration in which the driving chip 20 is disposed in the frame region 12 is called a COG (Chip On the Glass) method. This COG method is clearly different from a COF (Chip On the Film) method in which connection wiring is formed on a base film.
此外，如圖8所示，邊框區域12係劃分成扇出區域12a及扇入區域12b。扇出區域12a為從驅動晶片20和源極線31、32的連接部25(亦即，驅動晶片20的輸出端)至有效區域11之間的區域。此外，扇入區域12b則為位在較扇出區域12a遠離有效區域11的區域。例如圖6所示，扇入區域12b配置有連接於驅動晶片20的影像輸入線、或電源輸入線、源極線測試墊、閘極訊號測試墊等。圖8中，扇出區域12a與扇入區域12b的交界線係以延伸於正交方向(有效區域中，與源極線的延伸方向正交的方向)的虛線表示。此外，圖8中，扇出區域12a的高度係以符號H 1標示，扇入區域12b的高度則以符號H 2標示。本發明係在這些扇出區域12a及扇入區域12b中，就以使扇出區域12a之高度H 1窄小化為目的之源極線配線方式進行提案。 As shown in FIG. 8, the frame region 12 is divided into a fan-out region 12 a and a fan-in region 12 b. The fan-out region 12 a is a region from the connection portion 25 of the driving chip 20 and the source lines 31 and 32 (ie, the output end of the driving chip 20) to the effective region 11. In addition, the fan-in area 12b is an area located farther from the effective area 11 than the fan-out area 12a. For example, as shown in FIG. 6, the fan-in area 12 b is provided with an image input line, a power input line, a source line test pad, a gate signal test pad, and the like connected to the driving chip 20. In FIG. 8, the boundary line between the fan-out region 12 a and the fan-in region 12 b is indicated by a dotted line extending in an orthogonal direction (a direction orthogonal to the extending direction of the source line in the effective region). In addition, in FIG. 8, the height of the fan-out area 12 a is indicated by the symbol H 1 , and the height of the fan-in area 12 b is indicated by the symbol H 2 . The present invention proposes a source line wiring method for narrowing the height H 1 of the fan-out region 12 a in these fan-out regions 12 a and 12 b.
如圖8所示，本發明中，多條源極線中包含有第1組源極線31及第2組源極線32。第1組源極線31係配線成從驅動晶片20的連接部25(輸出端)朝向扇入區域12b，且在扇入區域12b中與正交方向大致平行地延伸，再從該扇入區域12b通過扇出區域12a而到達有效區域11。此外，第2組源極線32係配線成從驅動晶片20的連接部25(輸出端)不通過扇入區域12b，而僅通過扇出區域12a即到達有效區域11。 As shown in FIG. 8, in the present invention, the plurality of source lines include a first group of source lines 31 and a second group of source lines 32. The first group of source lines 31 are wired from the connection portion 25 (output end) of the driving chip 20 toward the fan-in area 12b, and extend substantially parallel to the orthogonal direction in the fan-in area 12b, and then from the fan-in area 12b reaches the effective area 11 through the fan-out area 12a. In addition, the second set of source lines 32 are wired so that the connection portion 25 (output end) of the driving chip 20 does not pass through the fan-in region 12b, but passes through the fan-out region 12a to reach the effective region 11.
再者，驅動晶片20上，沿正交方向(x軸方向)隔開一定間隔設有複數個連接部25(輸出端)。各個連接部25(輸出端)連接有源極線。此時，第1組源極線31係連接於設在正交方向左右外側的驅動晶片20之連接部25(輸出端)。因此，第1組源極線31係位於驅動晶片20的左右兩側2個位置。此外，第1組源極線31在顯示面板10的有效區域11中也是配置在正交方向的左右外側。另一方面，第2組源極線32係位於第1組源極線31所在的前述2個位置之間。亦即，第2組源極線32係連接於設在正交方向中央之驅動晶片20的連接部25(輸出端)。此外，第2組源極線32在顯示面板10的有效區域11中也是配置在正交方向的中央。透過依此方式實施配線，第1組源極線31與第2組源極線32在邊框區域12皆不會有交叉的情形。 Furthermore, a plurality of connection portions 25 (output ends) are provided on the driving wafer 20 at regular intervals in the orthogonal direction (x-axis direction). Each connection portion 25 (output terminal) is connected to a source line. At this time, the first group of source lines 31 are connected to the connection portion 25 (output end) of the driving chip 20 provided on the left and right outer sides in the orthogonal direction. Therefore, the first group of source lines 31 are located at two positions on the left and right sides of the driving chip 20. The source lines 31 of the first group are also arranged on the left and right outer sides in the orthogonal direction in the effective area 11 of the display panel 10. On the other hand, the source line 32 of the second group is located between the aforementioned two positions where the source line 31 of the first group is located. That is, the second group of source lines 32 is connected to the connection portion 25 (output end) of the driving chip 20 provided at the center in the orthogonal direction. The source lines 32 of the second group are also arranged at the center in the orthogonal direction in the effective area 11 of the display panel 10. By implementing the wiring in this way, neither the source lines 31 of the first group nor the source lines 32 of the second group cross each other in the frame region 12.
此外，第1組源極線31的條數和第2組源極線32條數只要按照顯示面板的解析度或所要求的邊框區域尺寸適當調整即可。例如，本實施方式中，第1組源極線31係存在於2個位置，但第1組源極線31只要分別包含至少2條以上源極線(合計4條)即可，但也可包含4條以上(合計8條)或10條以上(合計20條)。此外，例如第2組源極線32的數目假設為100%時，2個位置的第1組源極線31的合計數可採取10至100%、15至80%、或20至60%左右。另外，2個位置的第1組源極線31的合計數較佳為第2組源極線32的條數以下。 In addition, the number of source lines 31 in the first group and 32 source lines in the second group may be appropriately adjusted in accordance with the resolution of the display panel or the required size of the frame region. For example, in the present embodiment, the first group of source lines 31 exists in two positions, but the first group of source lines 31 may include at least two or more source lines (a total of four), but they may be Contains 4 or more (8 in total) or 10 or more (20 in total). In addition, for example, when the number of source lines 32 in the second group is assumed to be 100%, the total number of source lines 31 in the first group in two positions may be about 10 to 100%, 15 to 80%, or 20 to 60%. . The total number of source lines 31 in the first group at the two positions is preferably equal to or less than the number of source lines 32 in the second group.
圖9為第1組及第2組源極線31、32之配線構造的放大顯示圖。如圖9所示，第1組源極線31係由分別包含第1部31a、第2部31b、第3部31c、第4部31d所構成。另外，包含在第1組的多條源極線31中，從第1部31a至第4部31d係全都隔開一定間隔平行地配線。FIG. 9 is an enlarged display diagram of the wiring structure of the source lines 31 and 32 of the first group and the second group. As shown in FIG. 9, the first group of source lines 31 is composed of a first portion 31 a, a second portion 31 b, a third portion 31 c, and a fourth portion 31 d. In addition, among the plurality of source lines 31 included in the first group, all of the source lines 31 are wired in parallel from the first portion 31a to the fourth portion 31d at a constant interval.
第1部31a係以連接在驅動晶片20的連接部25(輸出端)為起點，朝離開有效區域11的方向配線的部位。因此，第1部31a係整體均配線在扇入區域12b。第1部31a係一端連接於驅動晶片20的連接部25(輸出端)，另一端銜接於第2部31b。圖示例中，第1部31a係與延伸方向(y軸方向)平行延伸。The first portion 31 a is a portion that is wired in a direction away from the effective area 11 starting from the connection portion 25 (output end) connected to the driving chip 20. Therefore, the entire first portion 31a is wired in the fan-in area 12b. The first portion 31a is a connecting portion 25 (output terminal) connected to the driving chip 20 at one end, and is connected to the second portion 31b at the other end. In the example of the figure, the first portion 31a extends parallel to the extending direction (y-axis direction).
第2部31b為在扇入區域12b中朝正交方向(x軸方向)配線的部位。第2部31b為一端銜接於第1部31a，另一端銜接於第3部31c。此外，第2部31b係整體配線於扇入區域12b。第2部31b較佳為在扇入區域12b中與正交方向(y軸方向)平行地延伸。另外，第2部31b的長度只要按每條源極線調整，使後述第3部31c的傾斜角度θ 1與第3部31c間的節距P w1位於適當範圍即可。 The second portion 31b is a portion that is wired in the orthogonal direction (x-axis direction) in the fan-in area 12b. The second portion 31b is connected to the first portion 31a at one end and to the third portion 31c at the other end. The second portion 31b is entirely wired to the fan-in area 12b. The second portion 31b preferably extends parallel to the orthogonal direction (y-axis direction) in the fan-in region 12b. Further, the length of the second portion 31b of each source line just press adjustments to be described later, the third inclined angle θ 1 31c to 31c and the pitch between the first 3 P w1 in the proper range.
第3部31c為從扇入區域12b通過扇出區域12a朝接近有效區域11的方向配線的部位。第3部31c係一端銜接於第2部31b，另一端銜接於第4部31d。如圖9所示，第3部31c較佳為以既定角度θ 1對正交方向軸(y軸)傾斜。角度θ 1較佳為45度以上，例如45度至90度、50度至85度、或60度至80度。此外，第3部31c的傾斜角度θ 1較佳為至少大於後述第2組源極線32的傾斜部32b的傾斜角度θ 2(θ 1＞θ 2)。另外，圖9中，第1組源極線31之第3部31c間的節距係以符號P w1表示。該第3部31c的節距P w1以至少5μm以上為佳，5至15μm特佳。再者，第3部31c的節距P w1以至少大於後述第2組源極線32之傾斜部32b的節距P w2(P w1＞P w2)為佳。 The third portion 31c is a portion that is wired from the fan-in area 12b through the fan-out area 12a toward the effective area 11. The third part 31c is connected to the second part 31b at one end and the fourth part 31d at the other end. As shown in FIG. 9, it is preferable that the third portion 31 c is inclined with respect to the orthogonal direction axis (y-axis) at a predetermined angle θ 1 . The angle θ 1 is preferably 45 degrees or more, for example, 45 degrees to 90 degrees, 50 degrees to 85 degrees, or 60 degrees to 80 degrees. The inclination angle θ 1 of the third portion 31 c is preferably at least larger than the inclination angle θ 2 (θ 1 > θ 2 ) of the inclined portion 32 b of the source line 32 of the second group described later. In addition, in FIG. 9, the pitch between the third portions 31 c of the first group of source lines 31 is indicated by the symbol P w1 . The pitch P w1 of the third portion 31 c is preferably at least 5 μm or more, and particularly preferably 5 to 15 μm. The pitch P w1 of the third portion 31 c is preferably at least larger than the pitch P w2 (P w1 > P w2 ) of the inclined portion 32 b of the source line 32 of the second group described later.
第4部31d為配線在有效區域11上的部位。因此，第4部31d係以和有效區域11上之顯示像素節距對應的間隔配置。有效區域11中，源極線全都呈平行。The fourth portion 31d is a portion where the wiring is placed on the effective area 11. Therefore, the fourth portion 31d is arranged at intervals corresponding to the pitch of the display pixels on the effective area 11. In the effective region 11, the source lines are all parallel.
此外，如圖9所示，第2組源極線32的一部分中，屬於扇出區域12a的部分係由包含直線部32a及傾斜部32b所構成。第2組源極線32係由直線部32a與傾斜部32b的兩者或任一者、及配置於有效區域11上的有效部32c所構成。第2組源極線32可包含僅由直線部32a與有效部32c組成者、或僅由傾斜部32b與有效部32c構成者。基本上，第2組源極線32中，位於正交方向中央者係僅由直線部32a與有效部32c構成，而位於正交方向最靠左右外側者則僅由傾斜部32b與有效部32c構成，位於其間者則由包含直線部32a、傾斜部32b、及有效部32c所構成。另外，第2組所包含的多條源極線32係直線部32a、傾斜部32b及有效部32c隔開一定間隔平行地配線。In addition, as shown in FIG. 9, a part of the second group of source lines 32 that belongs to the fan-out area 12 a is composed of a straight portion 32 a and an inclined portion 32 b. The second set of source lines 32 is composed of either or both of the straight portion 32 a and the inclined portion 32 b, and the effective portion 32 c disposed on the effective region 11. The second set of source lines 32 may include only a straight portion 32a and an effective portion 32c, or a portion consisting of only the inclined portion 32b and the effective portion 32c. Basically, in the second group of source lines 32, those located at the center of the orthogonal direction are composed of only the straight portion 32a and the effective portion 32c, and those located at the outermost sides of the orthogonal direction are composed of only the inclined portion 32b and the effective portion 32c The structure is located between the straight portion 32a, the inclined portion 32b, and the effective portion 32c. In addition, the plurality of source lines 32 included in the second group are linear portions 32a, inclined portions 32b, and effective portions 32c, and are wired in parallel at regular intervals.
直線部32a係以連接在與驅動晶片20的連接部(輸出端)為起點，而朝接近有效區域11的方向配線的部位。因此，直線部32a係整體配線在扇出區域12a。直線部32a係一端連接於驅動晶片20的輸出端，另一端銜接於傾斜部32b。圖示例中，直線部32a係與延伸方向(y軸方向)平行來延伸設置。The linear portion 32 a is a portion that is wired in a direction approaching the effective area 11 starting from a connection portion (output end) connected to the drive chip 20. Therefore, the straight portion 32a is entirely wired in the fan-out area 12a. One end of the linear portion 32a is connected to the output end of the driving chip 20, and the other end is connected to the inclined portion 32b. In the example shown in the figure, the straight portion 32a is extended to be parallel to the extending direction (y-axis direction).
傾斜部32b，係一端銜接於直線部32a，另一端連接於有效部32c，且以既定角度對延伸方向(y軸方向)及正交方向(x軸方向)傾斜的部位。傾斜部32b係朝接近有效區域11的方向配線在扇出區域12a。如圖9所示，傾斜部32b較佳為以既定角度θ 2對正交方向軸(y軸)傾斜。角度θ 2以45度以下為佳，例如，以5度至45度、10度至30度、或15度至20度為佳。因傾斜部32b的角度θ 2會影響扇出區域12a的高度H 1，故儘量以小角度為宜。再者，如前所述，傾斜部32b的傾斜角度θ 2係至少小於第1組源極線31之第3部31c的傾斜角度θ 1。此外，圖9中，第2組源極線32之傾斜部32b間的節距係以符號P w2標示。該傾斜部32b的節距P w2較佳為至少3μm以上，而3至10μm為特佳。而且，如前所述，傾斜部32b的節距P w2係至少小於第1組源極線31之第3部31c的節距P w1。 The inclined portion 32b is a portion where one end is connected to the linear portion 32a and the other end is connected to the effective portion 32c and is inclined at a predetermined angle with respect to the extension direction (y-axis direction) and the orthogonal direction (x-axis direction). The inclined portion 32 b is wired in the fan-out area 12 a in a direction approaching the effective area 11. As shown in FIG. 9, the inclined portion 32 b is preferably inclined with respect to the orthogonal direction axis (y-axis) at a predetermined angle θ 2 . The angle θ 2 is preferably 45 degrees or less, and for example, 5 degrees to 45 degrees, 10 degrees to 30 degrees, or 15 degrees to 20 degrees is preferable. Since the angle θ 2 of the inclined portion 32 b affects the height H 1 of the fan-out area 12 a, it is preferable to use a small angle as much as possible. In addition, as described above, the inclination angle θ 2 of the inclined portion 32 b is at least smaller than the inclination angle θ 1 of the third portion 31 c of the first group of source lines 31. In addition, in FIG. 9, the pitch between the inclined portions 32 b of the source lines 32 of the second group is indicated by a symbol P w2 . The pitch P w2 of the inclined portion 32 b is preferably at least 3 μm or more, and particularly preferably 3 to 10 μm. As described above, the pitch P w2 of the inclined portion 32 b is at least smaller than the pitch P w1 of the third portion 31 c of the source line 31 of the first group.
有效部32c為配線在有效區域11上的部位。因此，有效部32c係以對應於有效區域11上的顯示像素節距的間隔來配置。有效區域11中，源極線全都呈平行。The effective portion 32 c is a portion where the wiring is provided on the effective area 11. Therefore, the effective portions 32 c are arranged at intervals corresponding to the pitch of the display pixels on the effective area 11. In the effective region 11, the source lines are all parallel.
如圖8及圖9所示，第1組源極線31係配置在驅動晶片20的左右外側且條數為一定的源極線，這些第1組源極線31係在朝向離開有效區域11的方向延伸後，在扇入區域12b朝橫方向延伸，且在充分到達面板的左右側之後，朝接近有效區域11的方向彎折，然後通過扇出區域12a而與有效區域11之源極線端連接。As shown in FIGS. 8 and 9, the first group of source lines 31 are arranged on the left and right outer sides of the driving chip 20 and have a fixed number of source lines. These first group of source lines 31 are oriented away from the effective area 11. After extending in the direction, the fan-in area 12b extends in the horizontal direction, and after reaching the left and right sides of the panel sufficiently, it is bent in a direction close to the effective area 11 and then passes through the fan-out area 12a to the source line of the effective area 11端 连接。 End connection.
如參照圖7所說明者，從和面板尺寸或面板解析度的關係來考量源極線的配線節距Pw為一定的情況時，扇出區域12a的高度H 1一般是由自驅動晶片20之端部至有效區域11之端部為止的距離D x及配線的角度θ來決定。從而，只要將圖7所示的距離D x縮小，或是將角度θ縮小，扇出區域12a的高度H 1也可減小。 As described with reference to FIG. 7, when the wiring pitch Pw of the source line is constant from the relationship with the panel size or the panel resolution, the height H 1 of the fan-out area 12 a is generally determined by the self-driving chip 20. end angle θ to the active region and the wiring distance D x up to the end portion 11 is determined. Therefore, as long as the distance D x shown in FIG. 7 is reduced or the angle θ is reduced, the height H 1 of the fan-out area 12 a can also be reduced.
圖10至圖12為本發明配線方式的放大圖。如前所述，扇出區域12a的高度H 1係由自驅動晶片20之端部至有效區域11之端部為止的距離D x及配線角度θ來決定。對於此點，本發明的配線方式中，第1組源極線31係配線成暫先通過扇入區域12b後，接著通過扇出區域12a，再到達有效區域11，因其傾斜角度θ 1可在某種程度內自由地調整，故在決定扇出區域12a的高度H 1之際該第1組源極線31的配線可以忽略。因此，本發明的配線方式中，只有第2組源極線32是決定扇出區域12a之高度H 1的主要因素。此處，從驅動晶片20之端部至第2源極線32所連接的有效區域11之端部為止的距離D B(參照圖9、圖10)就可較圖7所示的傳統配線方式的距離D x短縮。因此，由第2組源極線32所決定的扇出區域12a之高度H 1可充分縮小。 10 to 12 are enlarged views of a wiring method of the present invention. As described above, the height H 1 of the fan-out area 12 a is determined by the distance D x and the wiring angle θ from the end of the driving chip 20 to the end of the effective area 11. In this regard, in the wiring method of the present invention, the first group of source lines 31 is wired to pass through the fan-in area 12b temporarily, then through the fan-out area 12a, and then reach the effective area 11, because of its tilt angle θ 1 may It can be adjusted freely to some extent, so when determining the height H 1 of the fan-out area 12 a, the wiring of the source lines 31 of the first group can be ignored. Therefore, in the wiring method of the present invention, only the second group of source lines 32 is the main factor that determines the height H 1 of the fan-out area 12 a. Here, the distance D B (see FIGS. 9 and 10) from the end of the driving chip 20 to the end of the effective region 11 to which the second source line 32 is connected can be compared with the conventional wiring method shown in FIG. The distance D x is shortened. Therefore, the height H 1 of the fan-out area 12 a determined by the second group of source lines 32 can be sufficiently reduced.
換言之，如圖7所示，只要減小源極線的傾斜角度θ，即可減小扇出區域12a的高度H 1。但，由於設計上的問題，傾斜角度θ無法設在一定值以下，傾斜角度θ的縮小有其極限。因此，以該極限值的傾斜角度θ傾斜的源極線數越多，圖7所示的距離D x就越長，結果，高度H 1越大。相對於此種情況，如圖9及圖10所示，本發明中，由於使第1組源極線31a的配線轉向扇入區域12b，以極限值的傾斜角度θ 2(相當於圖7的θ)傾斜的源極線只有第2組源極線32，結果，圖9所示的D B即短於圖7所示的距離D x。結果，透過有效活用扇入區域12b，以源極線的一部分通過扇入區域12b的方式實施配線，即可使扇出區域12a的高度H 1充分縮小。依此方式，透過有效活用扇入區域12b，相同條數的源極線可實施配線，而不會超出傳統尺寸。 In other words, as shown in FIG. 7, as long as the inclination angle θ of the source line is reduced, the height H 1 of the fan-out region 12 a can be reduced. However, due to design problems, the inclination angle θ cannot be set below a certain value, and the reduction of the inclination angle θ has its limit. Therefore, the larger the number of source lines inclined at the inclination angle θ of this limit value, the longer the distance D x shown in FIG. 7 is, and as a result, the height H 1 is larger. In contrast to this, as shown in FIG. 9 and FIG. 10, in the present invention, since the wiring of the first group of source lines 31 a is turned to the fan-in area 12 b, the tilt angle θ 2 (equivalent to the θ) The inclined source lines are only the second set of source lines 32. As a result, D B shown in FIG. 9 is shorter than the distance D x shown in FIG. 7. As a result, the area through effective use of the fan 12b, a portion of the fan through the source line region 12b of the wiring embodiments, can make the height H 1 of the fan-out region 12a sufficiently reduced. In this way, by effectively utilizing the fan-in area 12b, the same number of source lines can be implemented without exceeding the conventional size.
再者，圖11係揭示藉第1組訊號線連接的驅動晶片輸出端與有效區域輸入端的對應關係。第1組訊號線中，在正交方向最靠內側的連接部連接於驅動晶片的訊號線係在有效區域中配線於正交方向最靠外側。此外，第1組訊號線中，在正交方向最靠外側的連接部係連接於驅動晶片的訊號線，但在有效區域中則係配線於正交方向最靠內側。依此方式，有關於第1訊號線，係藉由使在邊框區域中連接於驅動晶片越靠內側輸出端者，在有效區域中配置在越靠外側位置，即可避免多條第1訊號線發生混線(交叉)。Furthermore, FIG. 11 shows the corresponding relationship between the output terminal of the driving chip and the input terminal of the active area connected by the first group of signal lines. In the first group of signal lines, the signal line connected to the drive chip at the innermost portion in the orthogonal direction is connected to the outermost portion in the orthogonal direction in the effective area. In addition, in the first group of signal lines, the connection part that is most outward in the orthogonal direction is connected to the signal line of the driving chip, but in the effective area, it is wired most inward in the orthogonal direction. In this way, regarding the first signal line, a plurality of first signal lines can be avoided by arranging the output terminals located closer to the inside of the driver chip in the frame area and positioned more outward in the effective area. Blending (crossover) occurs.
圖12中，係將利用傳統配線方式的顯示面板與利用本發明配線方式的顯示面板並列顯示。如圖12所示，若依本發明的配線方式，可達成邊框區域，特別是扇出區域之邊框的窄化。例如，13.3吋的FHD面板中，P w＝7μm時，在傳統配線方式中，H 1＝6mm為其極限，本發明則可刪減至H 1＝4mm。依此方式，在現況下，扇出區域高度H 1＝6mm為極限，若依本發明，該H 1可成功刪減至2／3左右，本發明對本技術領域的貢獻可謂甚大。 [産業上的可利用性] In FIG. 12, a display panel using a conventional wiring method and a display panel using a wiring method of the present invention are displayed side by side. As shown in FIG. 12, according to the wiring method of the present invention, the frame area can be narrowed, especially the frame area of the fan-out area. For example, in a 13.3-inch FHD panel, when P w = 7 μm, in the conventional wiring method, H 1 = 6 mm is the limit, and the present invention can be reduced to H 1 = 4 mm. In this way, in the current situation, the height of the fan-out area H 1 = 6 mm is the limit. If the present invention can successfully reduce the H 1 to about 2/3, the contribution of the present invention to the technical field can be described as very large. [Industrial availability]
本發明適合在例如筆記型電腦或平板電腦中利用於液晶面板的邊框窄化技術。The present invention is suitable for use in a bezel narrowing technology of a liquid crystal panel in a notebook computer or a tablet computer, for example.
1‧‧‧顯示模組1‧‧‧Display Module
10‧‧‧顯示面板10‧‧‧Display Panel
11‧‧‧有效區域11‧‧‧Effective area
12‧‧‧邊框區域12‧‧‧ border area
12a‧‧‧扇出區域12a‧‧‧fan-out area
12b‧‧‧扇入區域12b‧‧‧fan-in area
20‧‧‧驅動晶片20‧‧‧Driver
21‧‧‧上邊21‧‧‧top
22‧‧‧下邊22‧‧‧ below
23‧‧‧左邊23‧‧‧ left
24‧‧‧右邊24‧‧‧ right
25‧‧‧連接部25‧‧‧Connecting Department
31‧‧‧第1組源極線(訊號線)31‧‧‧Group 1 source line (signal line)
31a‧‧‧第1部31a‧‧‧Part 1
31b‧‧‧第2部31b‧‧‧Part 2
31c‧‧‧第3部31c‧‧‧Part 3
31d‧‧‧第4部31d‧‧‧Part 4
32‧‧‧第2組源極線(訊號線)32‧‧‧Group 2 source line (signal line)
32a‧‧‧直線部32a‧‧‧Straight line
32b‧‧‧傾斜部32b‧‧‧inclined
32c‧‧‧有效部32c‧‧‧Effective Department
41‧‧‧閘極控制線41‧‧‧Gate control line
圖1為時序控制器與源極驅動器分離的顯示模組的整體構成方塊圖。 圖2為時序控制器與源極驅動器一體化的顯示模組的整體構成方塊圖。 圖3為時序控制器與源極驅動器一體化的顯示模組的整體構成方塊圖。 圖4為時序控制器與源極驅動器分離的顯示模組中，顯示面板的有效區域及邊框區域圖。 圖5為時序控制器與源極驅動器一體化的顯示模組中，顯示面板的有效區域及邊框區域圖。 圖6為顯示面板源極線的傳統配線方式圖。 圖7為自圖6所示的顯示面板之中央起左側一半的放大圖，藉以說明傳統配線方式中邊框區域尺寸是如何求得的圖示。 圖8為本發明顯示模組的源極線配線方式圖。 圖9為自圖8所示的顯示面板之中央起左側一半的放大圖，藉以說明邊框區域尺寸得以窄小化的本發明功效圖。 圖10為圖9所示放大圖的簡化圖。 圖11為藉第1組訊號線連接的驅動晶片輸出端與有效區域輸入端的對應關係圖。 圖12為傳統配線方式與本發明配線方式的效果比較圖。FIG. 1 is a block diagram of an overall structure of a display module in which a timing controller and a source driver are separated. FIG. 2 is a block diagram of an overall structure of a display module in which a timing controller and a source driver are integrated. FIG. 3 is a block diagram of an overall structure of a display module in which a timing controller and a source driver are integrated. FIG. 4 is a diagram of an effective area and a frame area of a display panel in a display module in which a timing controller and a source driver are separated. 5 is a diagram of an effective area and a frame area of a display panel in a display module in which a timing controller and a source driver are integrated. FIG. 6 is a diagram of a conventional wiring mode of a source line of a display panel. FIG. 7 is an enlarged view of the left half from the center of the display panel shown in FIG. 6 to illustrate how to obtain the size of the frame area in the conventional wiring method. FIG. 8 is a diagram of a wiring mode of a source line of a display module according to the present invention. FIG. 9 is an enlarged view of the left half from the center of the display panel shown in FIG. 8 to illustrate the effect diagram of the present invention in which the size of the frame region is reduced. FIG. 10 is a simplified diagram of the enlarged view shown in FIG. 9. FIG. 11 is a correspondence diagram between the output end of the driving chip and the input end of the effective area connected by the first group of signal lines. FIG. 12 is a diagram comparing the effects of the conventional wiring method and the wiring method of the present invention.
1‧‧‧顯示模組 1‧‧‧Display Module
10‧‧‧顯示面板 10‧‧‧Display Panel
11‧‧‧有效區域 11‧‧‧Effective area
12‧‧‧邊框區域 12‧‧‧ border area
12a‧‧‧扇出區域 12a‧‧‧fan-out area
12b‧‧‧扇入區域 12b‧‧‧fan-in area
20‧‧‧驅動晶片 20‧‧‧Driver
31‧‧‧第1組源極線 31‧‧‧Group 1 source line
32‧‧‧第2組源極線 32‧‧‧Group 2 source line
41‧‧‧閘極驅動線 41‧‧‧Gate driving line
Claims (7)
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| JP2016216810A JP6152464B1 (en) | 2016-11-05 | 2016-11-05 | Narrow frame display module and data output device |
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| TWI617862B true TWI617862B (en) | 2018-03-11 |
| TW201818124A TW201818124A (en) | 2018-05-16 |
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| TW106124596A TWI617862B (en) | 2016-11-05 | 2017-07-21 | Narrow bezel display module and data output device |
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| JP (1) | JP6152464B1 (en) |
| KR (1) | KR101820382B1 (en) |
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| CN111796446A (en) * | 2019-04-02 | 2020-10-20 | 力领科技股份有限公司 | Display device |
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| TW201818124A (en) | 2018-05-16 |
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| JP6152464B1 (en) | 2017-06-21 |
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