TWI602274B - 半導體封裝 - Google Patents

半導體封裝 Download PDF

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TWI602274B
TWI602274B TW103131825A TW103131825A TWI602274B TW I602274 B TWI602274 B TW I602274B TW 103131825 A TW103131825 A TW 103131825A TW 103131825 A TW103131825 A TW 103131825A TW I602274 B TWI602274 B TW I602274B
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bump
printed circuit
circuit board
semiconductor package
package
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TW103131825A
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TW201526188A (zh
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崔元
金映勳
朴賢耕
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三星電機股份有限公司
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007—Surface contacts, e.g. bumps
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/36—Assembling printed circuits with other printed circuits
    • H05K3/368—Assembling printed circuits with other printed circuits parallel to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/2612—Auxiliary members for layer connectors, e.g. spacers
    • H01L2224/26152—Auxiliary members for layer connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/26175—Flow barriers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/042—Stacked spaced PCBs; Planar parts of folded flexible circuits having mounted components in between or spaced from each other
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/041—Solder preforms in the shape of solder balls

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Combinations Of Printed Boards (AREA)

Description

半導體封裝
本發明係有關於一種半導體封裝，且特別是有關於一種能穩定改良堆疊板之層間接合的半導體封裝。
一般而言，用來電性連接或機械性固定多個電子元件的印刷電路板(printed circuit board,PCB)包含絕緣層與銅箔(copper foil)，絕緣層由絕緣材料形成，如酚(phenol)樹脂、環氧樹脂、或類似物，而銅箔層係貼附至絕緣層，從而形成預定的佈線圖案。
PCB主要係分類為：單層PCB(single PCB)，其中佈線圖案係僅形成在絕緣層的一個表面上；雙層PCB(double PCB)，其中佈線圖案係形成在絕緣層的兩個表面上；多層PCB，其中具有佈線圖案形成其上的複數個絕緣層係堆疊，而形成多層形狀的佈線圖案。
在這種情況下，在多層PCB具有半導體裝置固定在各層上的結構的例子中，焊球係夾置(interpose)在對應的層與層之間，以使各層相互電性連接至彼此。
焊球係設置在具有電性裝置固定其上之PCB與設 置在PCB之下方的印刷電路板之間，，而另一個電性裝置係設置在下方的PCB的情況下，焊球係設置在電性裝置的兩側。
然而，對於依據藉由上述架構而配置之相關技藝的半導體封裝，在最近藉由3D封裝而配置的結構之中，夾置在頂封裝與下封裝件之間的焊球並不適用於以焊球連接上及下印刷電路板的標準，原因是使用在各層的電路圖案的微型化、與半導體封裝之安裝空間的擴大，致使難以處理精細的電路圖案，因此，對應封裝之間的層間匹配並不能準確地被執行。
本發明之一目的在於提供一種半導體裝置，半導體裝置包含凸塊使得夾置在上及下印刷電路板之間的焊球可維持在穩定的移位狀態(displacement state)。
本發明之另一目的在於提供一種凸塊，凸塊具有其內部係穿孔(perforated)的中空(hollow)形狀、或其上部係被擠壓(depress)的凹陷(concave)形狀，藉以維持與焊球之間的穩定耦接狀態。
依據本發明一範例性實施例，提供一種半導體封裝，包括：一下封裝件，具有一晶片模組固定在該下封裝件上，藉以被連接至一電路圖案；一上封裝件，堆疊在該下封裝件上，具有一電性裝置固定在該上封裝件上；以及一凸塊，接收一焊球的一端並被耦接至該焊球，該焊球電性連接該下封裝件與該上封裝件。
凸塊可使用與電路圖案相同材料的銅以作為凸塊的材料。
凸塊具有接收空間形成在凸塊之中，凸塊的接收空間的內部直徑可小於焊球的直徑。
凸塊具有一上表面，該上表面可被配置以被擠壓。
凸塊可被配置以對應至複數個焊球的位置與數量，而當一回銲(reflow)製程被執行時，焊球可被部分地熔化並引入凸塊的內部空間。
凸塊係被形成為圓環形、四方形、多邊形之任何一種形狀，凸塊可被配置成與下封裝件的電路圖案整合地(integrally)凸出(protrude)。
為了對本發明之上述及其他方面有更佳的瞭解，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下：
10‧‧‧下封裝件
12‧‧‧下印刷電路板
14、54‧‧‧電路圖案
15‧‧‧上封裝件
16、56‧‧‧絕緣層
18‧‧‧晶片模組
20‧‧‧焊球
30‧‧‧凸塊
32‧‧‧接收空間
50‧‧‧上封裝件
52‧‧‧上印刷電路板
100‧‧‧半導體封裝
D‧‧‧乾膜
第1圖繪示依照本發明一範例性實施例之半導體封裝的示意圖。
第2A圖繪示依照本發明一範例性實施例之電路圖案與阻銲劑被施加在半導體封裝之印刷電路板之狀態的示意圖。
第2B圖繪示依照本發明一範例性實施例之種子層被形成在半導體封裝之印刷電路板上之狀態的示意圖。
第2C圖繪示依照本發明一範例性實施例之乾膜被曝光並顯影(develop)在半導體封裝之印刷電路板之狀態的示意圖。
第2D圖繪示依照本發明一範例性實施例之銅柱(copper post)被鍍(plate)在半導體封裝之印刷電路板上之狀態的示意圖。
第2E圖繪示依照本發明一範例性實施例之乾膜從半導體封裝之印刷電路板上被脫層(delaminate)之狀態的示意圖。
第2F圖繪示依照本發明一範例性實施例之蝕刻製程被執行在半導體封裝之印刷電路板上之狀態的示意圖。
第3A圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合(bond)之前的示意圖。
第3B圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合之狀態的示意圖。
第3C圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合之狀態下，一回銲(reflow)被執行之狀態的示意圖。
第3D圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合之狀態下，此回銲被完成之狀態的示意圖。
於此後，將特舉範例性實施例，並配合所附圖式，作詳細說明如下。
第1圖繪示依照本發明一範例性實施例之半導體封裝的示意圖。第2A圖繪示依照本發明一範例性實施例之電路圖 案與阻銲劑被施加在半導體封裝之印刷電路板之狀態的示意圖。第2B圖繪示依照本發明一範例性實施例之種子層(seed layer)被形成在半導體封裝之印刷電路板上之狀態的示意圖。第2C圖繪示依照本發明一範例性實施例之乾膜(dry film)在半導體封裝之印刷電路板上之被曝光並顯影(develop)之狀態的示意圖。第2D圖繪示依照本發明一範例性實施例之銅柱(copper post)被鍍(plate)在半導體封裝之印刷電路板上之狀態的示意圖。第2E圖繪示依照本發明一範例性實施例之乾膜從半導體封裝之印刷電路板上被脫層(delaminate)之狀態的示意圖。第2F圖繪示依照本發明一範例性實施例之蝕刻製程被執行在半導體封裝之印刷電路板上之狀態的示意圖。第3A圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合(bond)之前的示意圖。第3B圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合之狀態的示意圖。第3C圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合之狀態下，一回銲(reflow)被執行之狀態的示意圖。第3D圖繪示依照本發明一範例性實施例之半導體封裝之上印刷電路板與其下印刷電路板被接合之狀態下，此回銲被完成之狀態的示意圖。
如第1圖所示，依據本發明範例性實施例之半導體封裝100可包含下封裝件10、堆疊在下封裝件10上的上封裝件50、耦接至焊球20的凸塊30，焊球20係電性連接下封裝件10 與上封裝件50至彼此。
下封裝件10可包含下印刷電路板12、第一電路圖案14、阻銲層、及晶片模組18，第一電路圖案14形成在下印刷電路板12的至少一表面，阻銲層係被施加以保護電路圖案14，晶片模組18係被固定以被連接至第一電路圖案14。
形成在下印刷電路板12上的第一電路圖案14係藉由執行蝕刻製程而在鍍層被堆疊的狀態下被配置。
再者，第一絕緣層16係施加在下印刷電路板12的上表面之上，以保護第一電路圖案14。
於此例中，雖然並未繪示於圖式之中，當複數個印刷電路板被堆疊在下印刷電路板12的下側之上時，下印刷電路板12可被提供貫孔(via)以用於連接各層。
再者，晶片模組18可被固定在下印刷電路板12之上。晶片模組18可被設置在第一電路圖案14被形成的位置之上，且可被電性連接至第一電路圖案14。
堆疊在下封裝件10上的上封裝件50具有多個第二電路圖案54與電性裝置(未繪示)，各個第二電路圖案54形成在上印刷電路板52的上表面及底表面之上，電性裝置藉由一固定製程(如表面黏著技術(surface mounting technology,SMT))而被安裝在印刷電路板52之上表面之上。
也就是說，形成在上印刷電路板52之上表面的第二電路圖案54係被形成以固定電性裝置(未繪示)，而第二絕緣層56 係形成以保護電路圖案。相反地，形成在上印刷電路板52之底表面的第二電路圖案54係被形成以被電性連接至下封裝件10。
雖未繪示在圖式之中，電性裝置可藉由封膠材料而被封膠(mold)。
如上所述方式而配置的上封裝件50與下封裝件10須配置而使得下封裝件10的晶片模組18的上表面維持在晶片模組18與上封裝件50之間相隔一預定間距的狀態下。也就是說，為了避免晶片模組18與上封裝件50相互連接、或避免當外部衝擊被施加而由上封裝件50破壞晶片模組18的上部，上封裝件50與下封裝件10須維持一預定間距。
為此目的，焊球20與凸塊30可被安裝並耦接至下封裝件10與上封裝件50。
雖然第1圖繪示之例中，焊球20係配置在上封裝件的第二電路圖案54上，而凸塊30係配置在下封裝件的第一電路圖案14上，相反地，焊球20可被配置在下封裝件10上，而凸塊30可被配置在上封裝件50上。
由於耦接至焊球20的凸塊30具有接收空間32形成於其中，當凸塊30被耦接至焊球20時，凸塊30可接收焊球20的一端。
凸塊30的整體形狀可被配置為各種形狀，例如圓環形、四方形、多邊形、或類似的形狀，而接收空間32的形狀也可被設計，並形成具有各種形狀，以求穩定接收焊球20之一端。
再者，凸塊30使用與下封裝件之第一電路圖案14相同材料的銅，致使凸塊30可整合於第一電路圖案14。於此例之中，凸塊30的接收空間32可被配置為具有小於焊球20之直徑的內部直徑。
再者，依據焊球20的位置與數量，凸塊30可被配置而相互面向並對應。如第1圖所示，焊球20的一直徑係小於凸塊30的一外周圍的一直徑。
因此，在依據本發明實施範例之上封裝件50被耦接至下封裝件10的狀態中，當回銲(reflow)製程被執行時，焊球20的一部分被熔化，而熔化的焊球係被引入凸塊的接收空間並且固化，使得凸塊30與焊球20係被整合。
於此例中，凸塊30可不具有接收空間形成在其中，而可被配置為其上表面係以一預定深度而被擠壓的形狀。
凸塊30的擠壓深度與面積係藉由計算焊球20以一預定深度而被接收的程度而被形成，然後在回銲製程中被部分地熔化，從而與凸塊30整合。
如此，在此例中，凸塊30與焊球20被配置為在回銲製程中相互整合，即使在分別製造上封裝件50與下封裝件10之後，在上封裝件50與下封裝件10耦接的過程中，凸塊30的中心與焊球20的中心並非準確地匹配，焊球20與凸塊30仍可被整合，使得製造製程之時間可被減少，而也可確保產品的可靠度。
同時，第2A至2F圖繪示依據本發明範例性實施例在半導體封裝的多個元件中製造下封裝件的製程。
此處，依據本發明範例性實施例，一個凸塊30被形成的情況係被顯示為一個例子。
如圖所示，具有第一電路圖案14的下封裝件10與施加在下印刷電路板12上的第一絕緣層16係被準備。
接著，種子層15係形成在第一電路圖案14上。種子層15使用與第一電路圖案14相同的材料。
在種子層15係被形成在電路圖案14上的例子中，鍍層乾膜D係堆疊在第一絕緣層16上。
在這種情況下，乾膜D係參考凸塊30的形狀而被堆疊，使得凸塊30可被整合地(integrally)形成在第一電路圖案14上。也就是說，當乾膜D係被堆疊時，在凸塊30具有圓柱狀且具有接收空間形成其中之結構的例子中，乾膜D係設置在接收空間將被形成的位置處，且乾膜D係被設置在被設置的乾膜D與其外部間隔一預定間距的位置處。
如上述之乾膜D被堆疊的例子中，銅係填入凸塊將被形成的位置處，而乾膜D係接著從第一絕緣層16被脫層(delaminate)。
當乾膜D被去除時，用於去除種子層15的蝕刻製程係被執行。
當蝕刻製程被完成時，晶片模組18係固定在下封裝 件10上。
下封裝件係藉由上述之製程而被完成時，上封裝件50與下封裝件10係被組合，如第3A至3D圖所示。
此處，上封裝件50具有第二電路圖案54、第二絕緣層56、與電性裝置(未繪示)係被固定在上印刷電路板52上的結構。由於此種結構對應至一般的封裝製程，故其細詳說明係予省略。
如圖所示，在上封裝件50與下封裝件10各被製成後，它們係被設置以使得焊球20與凸塊30面向彼此。
在上封裝件50與下封裝件10的移位(displacement)係被完成的情況下，上封裝件50係被下移，而下封裝件10係被上移，直到焊球20係緊密地貼附至凸塊30的中心。
在如上所述，在焊球20與凸塊30被緊密貼附至彼此之後，回銲製程係被執行。當回銲製程被執行時，焊球20的一部分係被熔化而被引入至凸塊的接收空間32中。
於此例中，值得注意的是，須考慮焊球20不會被回銲製程完全地熔化的時間、距離等的量。
其原因在於，在焊球20被完全地熔化的情況下，熔化的焊球可能超過凸塊的接收空間32的填充量，而多出來的焊球20的部分可能流動至上封裝件及下封裝件的電路圖案14與54，或可能施加至上封裝件及下封裝件之電路圖案14與54。
在經由上述製程，上封裝件50與下封裝件10被整 合至彼此的例子中，雖然焊球20的中心與凸塊30的中心並非準確地匹配，焊球20與凸塊30可維持穩定的耦接狀態。
再者，半導體封裝的總高度可被減少，而晶片模組18與上封裝件之上印刷電路板52之間的預定間隙可藉由耦接凸塊30至被熔化且被引入至凸塊30的焊球20而被形成。
依據本發明範例性實施例，半導體封裝具有凸塊夾置(interpose)在具有電性裝置固定其上之上及下印刷電路板之間，致使在回銲被執行時，焊球可被熔化並被引入至凸塊，從而維持上及下印刷電路板之穩定之耦接狀態，使得增加可靠度並降低封裝的總高度成為可能，而有效地增進產品特性。
綜上所述，雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作各種之更動與潤飾。因此，本發明之保護範圍當視後附之申請專利範圍所界定者為準。
10‧‧‧下封裝件
12‧‧‧下印刷電路板
14、54‧‧‧電路圖案
15‧‧‧上封裝件
16、56‧‧‧阻銲層
18‧‧‧晶片模組
20‧‧‧焊球
30‧‧‧凸塊
50‧‧‧上封裝件
52‧‧‧上印刷電路板
100‧‧‧半導體封裝

Claims (10)

  1. 一種半導體封裝，包括：一下印刷電路板；一第一電路圖案，形成於該下印刷電路板上；一第一絕緣層，形成於該第一電路圖案上，且該第一絕緣層具有一第一開口以暴露該第一電路圖案的一部份；一凸塊(bump)，形成於該第一開口中且位於該第一絕緣層的一上表面上，且該凸塊具有一接收空間形成於該凸塊中；以及一焊球(solder ball)，形成於該凸塊上；其中該焊球的一直徑係小於該凸塊的一外周圍的一直徑。
  2. 如申請專利範圍第1項所述之半導體封裝，其中該下印刷電路板具有一晶片模組固定在該下印刷電路板上。
  3. 如申請專利範圍第1項所述之半導體封裝，更包括：一上印刷電路板；一第二電路圖案，形成於該上印刷電路板上；一第二絕緣層，形成於該第二電路圖案上，且該第二絕緣層具有一第二開口以暴露該第二電路圖案的一部份。
  4. 如申請專利範圍第1項所述之半導體封裝，其中該凸塊係由銅材料所製成。
  5. 如申請專利範圍第1或3項所述之半導體封裝，其中該凸塊的該接收空間的內部直徑係小於該焊球的該直徑。
  6. 如申請專利範圍第1項所述之半導體封裝，其中該凸塊具 有一上表面，該上表面係被配置以被擠壓(depress)。
  7. 如申請專利範圍第1項所述之半導體封裝，其中該凸塊係被配置以對應至複數個焊球的位置與數量。
  8. 如申請專利範圍第1項所述之半導體封裝，其中當一回銲(reflow)製程被執行時，一焊球係被部分地熔化並被引入該凸塊的該接收空間。
  9. 如申請專利範圍第1項所述之半導體封裝，其中該凸塊係被形成為圓環形、四方形、多邊形之任何一種形狀。
  10. 如申請專利範圍第1項所述之半導體封裝，其中該凸塊係以與該下印刷電路板的該第一電路圖案整合的方式(integrally)被配置。
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Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10199356B2 (en) 2017-02-24 2019-02-05 Micron Technology, Inc. Semiconductor device assembles with electrically functional heat transfer structures
US10096576B1 (en) * 2017-06-13 2018-10-09 Micron Technology, Inc. Semiconductor device assemblies with annular interposers

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130157418A1 (en) * 2011-12-14 2013-06-20 Joonyoung Choi Integrated circuit packaging system with interconnects and method of manufacture thereof

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100216839B1 (ko) * 1996-04-01 1999-09-01 김규현 Bga 반도체 패키지의 솔더 볼 랜드 메탈 구조
US5977632A (en) * 1998-02-02 1999-11-02 Motorola, Inc. Flip chip bump structure and method of making
KR100386081B1 (ko) * 2000-01-05 2003-06-09 주식회사 하이닉스반도체 반도체 패키지 및 그 제조 방법
US6426556B1 (en) * 2001-01-16 2002-07-30 Megic Corporation Reliable metal bumps on top of I/O pads with test probe marks
US6930032B2 (en) * 2002-05-14 2005-08-16 Freescale Semiconductor, Inc. Under bump metallurgy structural design for high reliability bumped packages
US7015590B2 (en) * 2003-01-10 2006-03-21 Samsung Electronics Co., Ltd. Reinforced solder bump structure and method for forming a reinforced solder bump
JP4175197B2 (ja) * 2003-06-27 2008-11-05 株式会社デンソー フリップチップ実装構造
KR20070040869A (ko) 2005-10-13 2007-04-18 삼성전자주식회사 돌기 및 홈이 형성된 금속 부재를 이용한 적층 패키지
US8299595B2 (en) * 2010-03-18 2012-10-30 Stats Chippac Ltd. Integrated circuit package system with package stacking and method of manufacture thereof
US8241963B2 (en) * 2010-07-13 2012-08-14 Taiwan Semiconductor Manufacturing Company, Ltd. Recessed pillar structure
KR101238213B1 (ko) * 2011-01-31 2013-03-04 하나 마이크론(주) 적층형 반도체 패키지 및 이의 제조 방법
US8835301B2 (en) * 2011-02-28 2014-09-16 Stats Chippac, Ltd. Semiconductor device and method of forming bump structure with insulating buffer layer to reduce stress on semiconductor wafer
KR101740483B1 (ko) * 2011-05-02 2017-06-08 삼성전자 주식회사 고정 부재 및 할로겐-프리 패키지간 연결부를 포함하는 적층 패키지
US8409979B2 (en) * 2011-05-31 2013-04-02 Stats Chippac, Ltd. Semiconductor device and method of forming interconnect structure with conductive pads having expanded interconnect surface area for enhanced interconnection properties
US8803333B2 (en) * 2012-05-18 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Three-dimensional chip stack and method of forming the same
US9583470B2 (en) * 2013-12-19 2017-02-28 Intel Corporation Electronic device with solder pads including projections

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130157418A1 (en) * 2011-12-14 2013-06-20 Joonyoung Choi Integrated circuit packaging system with interconnects and method of manufacture thereof

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