JP2006294692A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2006294692A JP2006294692A JP2005109993A JP2005109993A JP2006294692A JP 2006294692 A JP2006294692 A JP 2006294692A JP 2005109993 A JP2005109993 A JP 2005109993A JP 2005109993 A JP2005109993 A JP 2005109993A JP 2006294692 A JP2006294692 A JP 2006294692A
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- wiring layer
- wiring
- semiconductor device
- conductive plug
- forming step
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Abstract
【解決手段】 半導体装置1は、配線層10,20、ICチップ30、ビアプラグ42,44、封止樹脂50、および半田ボール60を備えている。この配線層10中には、ビアプラグ42が形成されている。ビアプラグ42における配線層20側の端面の面積は、その反対側の端面すなわちICチップ30側の端面の面積よりも小さい。この配線層20中には、ビアプラグ44が形成されている。ビアプラグ44における配線層10側の端面の面積は、その反対側の端面すなわち後述する半田ボール60側の端面の面積よりも小さい。また、配線層10を構成する絶縁樹脂14の熱分解温度は、配線層20を構成する絶縁樹脂24の熱分解温度よりも高い。
【選択図】 図1
Description
図1は、本発明による半導体装置の第1実施形態を示す断面図である。半導体装置1は、配線層10,20、ICチップ30、ビアプラグ42,44、封止樹脂50、および半田ボール60を備えている。半導体装置1においてICチップ30、配線層10および配線層20は、この順に積層されるとともに、互いに電気的に接続されている。すなわち、配線層10の一面10a上にICチップ30が載置され、配線層10の上記一面とは反対側の面10b上に配線層20が設けられている。
図9は、本発明による半導体装置の第2実施形態を示す断面図である。半導体装置2は、配線層10,70、ICチップ30、ビアプラグ42,46、封止樹脂50、および半田ボール62を備えている。これらのうち、配線層10、ICチップ30、ビアプラグ42および封止樹脂50それぞれの構成は、図1で説明したものと同様である。また、半導体装置2において、ICチップ30、配線層10および配線層70は、この順に積層されるとともに、互いに電気的に接続されている。
2 半導体装置
10,20 配線層
12,22 導体配線
14,24 絶縁樹脂
16,26 密着金属膜
30 ICチップ
32 半田ボール
34 アンダーフィル樹脂
36 ビアプラグ
38 半田ボール
42,44 ビアプラグ
46 ビアプラグ
50 封止樹脂
60 半田ボール
62 半田ボール
70 配線層
74 絶縁樹脂
80 ICチップ
82 半田ボール
90 支持基板
Claims (17)
- 支持基板上に第1の配線層を形成する第1配線層形成工程と、
前記第1の配線層の一面上に、半導体素子を載置する半導体素子載置工程と、
前記半導体素子載置工程よりも後に、前記支持基板を除去する支持基板除去工程と、
前記支持基板除去工程よりも後に、前記第1の配線層の前記一面とは反対側の面上に、第2の配線層を形成する第2配線層形成工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項1に記載の半導体装置の製造方法において、
前記第2配線層形成工程においては、前記第1配線層形成工程において形成された前記第1の配線層を構成する樹脂よりも熱分解温度が低い樹脂を、前記第2の配線層を構成する樹脂として用いる、半導体装置の製造方法。 - 請求項1または2に記載の半導体装置の製造方法において、
前記第1配線層形成工程は、第1の配線を形成する第1配線形成工程と、前記第1の配線から前記第1の配線層の前記一面まで延びる第1の導電プラグを形成する第1導電プラグ形成工程とを含み、
前記第2配線層形成工程は、前記第1の配線から前記第2の配線層における前記第1の配線層とは反対側の面まで延びる第2の導電プラグを形成する第2導電プラグ形成工程を含む、半導体装置の製造方法。 - 請求項3に記載の半導体装置の製造方法において、
前記第2導電プラグ形成工程は、前記第2の導電プラグの前記第1の配線層と反対側に、バンプを形成するバンプ形成工程を含み、
前記第2の導電プラグは、前記バンプと一体に形成される、半導体装置の製造方法。 - 請求項1または2に記載の半導体装置の製造方法において、
前記第1配線層形成工程は、第1の配線を形成する第1配線形成工程と、前記第1の配線から前記第1の配線層の前記一面まで延びる第1の導電プラグを形成する第1導電プラグ形成工程とを含み、
前記第2配線層形成工程は、前記第1の配線に接続されるように第2の導電プラグを形成する第2導電プラグ形成工程と、前記第2の導電プラグに接続されるように第2の配線を形成する第2配線形成工程とを含む、半導体装置の製造方法。 - 請求項1乃至5いずれかに記載の半導体装置の製造方法において、
前記半導体素子載置工程と前記支持基板除去工程との間に、前記半導体素子の側面を覆うように前記第1の配線層上に封止樹脂を形成する封止樹脂形成工程を含む、半導体装置の製造方法。 - 請求項1乃至6いずれかに記載の半導体装置の製造方法において、
前記支持基板はシリコン基板である、半導体装置の製造方法。 - 第1の配線層と、
前記第1の配線層の一面上に載置された半導体素子と、
前記第1の配線層の前記一面とは反対側の面上に設けられた第2の配線層と、
前記第1の配線層中に設けられた第1の導電プラグと、
前記第2の配線層中に設けられた第2の導電プラグと、を備え、
前記第1の導電プラグにおける前記第2の配線層側の端面は、その反対側の端面よりも面積が小さく、
前記第2の導電プラグにおける前記第1の配線層側の端面は、その反対側の端面よりも面積が小さく、
前記第1の配線層を構成する樹脂は、前記第2の配線層を構成する樹脂よりも熱分解温度が高いことを特徴とする半導体装置。 - 請求項8に記載の半導体装置において、
前記第1の配線層は、第1の配線を含んでおり、
前記第1の導電プラグは、前記第1の配線から前記第1の配線層の前記一面まで延びており、
前記第2の導電プラグは、前記第1の配線から前記第2の配線層における前記第1の配線層とは反対側の面まで延びている半導体装置。 - 請求項8または9に記載の半導体装置において、
前記第2の導電プラグの前記第1の配線層と反対側に設けられたバンプを備え、
前記バンプと前記第2の導電プラグとは、同一の金属材料によって形成されている半導体装置。 - 請求項8に記載の半導体装置において、
前記第1および第2の配線層は、それぞれ第1および第2の配線を含んでおり、
前記第1の導電プラグは、前記第1の配線から前記第1の配線層の前記一面まで延びており、
前記第2の導電プラグは、前記第1の配線から前記第2の配線まで延びている半導体装置。 - 請求項8乃至11いずれかに記載の半導体装置において、
前記半導体素子の側面を覆うように前記第1の配線層上に設けられた封止樹脂を備える半導体装置。 - 請求項8乃至12いずれかに記載の半導体装置において、
前記第1の導電プラグ間の最小間隔は、前記第2の導電プラグ間の最小間隔よりも小さい半導体装置。 - 請求項8乃至13いずれかに記載の半導体装置において、
前記第1の配線層を構成する前記樹脂は、ポリベンゾオキサゾールまたはポリイミド樹脂であり、
前記第2の配線層を構成する前記樹脂は、エポキシ樹脂である半導体装置。 - 第1の配線を含む第1の配線層と、
前記第1の配線層の一面上に載置された半導体素子と、
前記第1の配線層の前記一面とは反対側の面上に設けられ、第2の配線を含む第2の配線層と、
前記第1の配線における前記第2の配線層側の面上に設けられた第1の密着金属膜と、
前記第2の配線における前記第1の配線層側の面上に設けられた第2の密着金属膜と、
を備えることを特徴とする半導体装置。 - 請求項15に記載の半導体装置において、
前記第2の配線層中に設けられ、前記第1の配線と前記第2の配線とを電気的に接続する導電プラグを備え、
前記第2の密着金属膜は、前記導電プラグを覆うように設けられており、当該導電プラグ上において前記第1の密着金属膜と接している半導体装置。 - 請求項15または16に記載の半導体装置において、
前記第1および第2の密着金属膜は、Niを含んでいる半導体装置。
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US20060226556A1 (en) | 2006-10-12 |
US7927999B2 (en) | 2011-04-19 |
US8035231B2 (en) | 2011-10-11 |
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