TWI602269B - 柱頂互連之封裝堆疊方法與構造 - Google Patents

柱頂互連之封裝堆疊方法與構造 Download PDF

Info

Publication number
TWI602269B
TWI602269B TW105118189A TW105118189A TWI602269B TW I602269 B TWI602269 B TW I602269B TW 105118189 A TW105118189 A TW 105118189A TW 105118189 A TW105118189 A TW 105118189A TW I602269 B TWI602269 B TW I602269B
Authority
TW
Taiwan
Prior art keywords
package
metal
carrier
metal pillars
end faces
Prior art date
Application number
TW105118189A
Other languages
English (en)
Other versions
TW201813014A (zh
Inventor
陳裕緯
王啓安
徐宏欣
Original Assignee
力成科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 力成科技股份有限公司 filed Critical 力成科技股份有限公司
Priority to TW105118189A priority Critical patent/TWI602269B/zh
Priority to US15/434,071 priority patent/US20170358557A1/en
Application granted granted Critical
Publication of TWI602269B publication Critical patent/TWI602269B/zh
Publication of TW201813014A publication Critical patent/TW201813014A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/107—Indirect electrical connections, e.g. via an interposer, a flexible substrate, using TAB
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1094—Thermal management, e.g. cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1431—Logic devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H01L2924/143—Digital devices
    • H01L2924/1433—Application-specific integrated circuit [ASIC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1811—Structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H01L2924/1815—Shape
    • H01L2924/1816—Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18161—Exposing the passive side of the semiconductor or solid-state body of a flip chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

柱頂互連之封裝堆疊方法與構造
本發明係有關於半導體晶片封裝領域，特別係有關於一種柱頂互連之封裝堆疊方法與構造。
半導體晶片封裝構造早期是表面接合在一外部印刷電路板上，並可以具備有各種已知的封裝型態。當一頂部封裝構造表面接合在一底部封裝構造上，便可組合成封裝堆疊構造(Package-On-Package,POP)。其中，用以連接頂部與底部封裝構造的中介端子的尺寸與間距將會明顯地影響封裝堆疊構造的製作良率，通常中介端子是包含銲球。
在現有利用雷射鑽孔的底部封裝構造中，例如銲球之中介端子係預先設置於底部封裝構造的基板上並以模封膠體密封之。隨後，以雷射鑽孔方式以露出中介端子被模封膠體包圍的錫球表面，以供頂部封裝構造的銲球接合，故上下堆疊的頂部與底部封裝構造可以迴焊組成一封裝堆疊構造(POP)。
請參閱第1圖，一種習知封裝堆疊構造(POP)係包含一底部封裝構造10以及一上方堆疊之頂部封裝構造20，該底部封裝構造10與該頂部封裝構造20之間係以複數個例如被模封銲球之中介端子30作迴焊接合。該底部封裝構造10係包含一基板11， 一晶片12係安裝在該基板11上並以一模封膠體13密封之，可利用複數個覆晶接合之凸塊電性連接該晶片12至該基板11。該些中介端子30係預先接合於該基板11之上表面並亦被該模封膠體13所密封。複數個底端子14係接合於該基板11之下表面。以雷射鑽孔作業露出該些中介端子30之頂面，並且該模封膠體13在該些中介端子30之間將形成一擋牆15。該頂部封裝構造20係包含另一基板21，一晶片22係安裝在該基板21上並以一模封膠體23密封之。可利用複數個打線形成之銲線24電性連接該晶片22與該基板21。該基板21之下表面設置有連接墊，以接合該些中介端子30。
第2圖繪示在習知封裝堆疊構造之製程中進行雷射鑽孔作業時之底部封裝構造的局部截面示意圖。以一雷射鑽孔器40對該底部封裝構造10之該模封膠體13進行雷射鑽孔作業，直到該些中介端子30之頂面為露出；同時，該模封膠體13在該些中介端子30之間形成之擋牆15，其原本用意是避免錫球對接時鎔融短接。然而，當該些中介端子30之間距微小化時，雷射鑽孔孔徑需要的斜角，將導致擋牆的矮化、縮小化而功能失效。因此，雷射鑽孔的底部封裝構造無法符合下一代微間距封裝堆疊構造(POP)的要求，這是因為製程中擋牆的厚度與斜角要求，限制了底部封裝構造走向微間距的發展能力。
為了解決上述之問題，本發明之主要目的係在於提供一種柱頂互連之封裝堆疊方法與構造，用以防止封裝堆疊構造 中底部封裝構造的中介導通元件的銲料橋接，中介端子能更微間距的排列與微小化，並且底部封裝構造的模封膠體之平坦面可不必要地製作重配置線路結構。
本發明之次一目的係在於提供一種柱頂互連之封裝堆疊方法與構造，使得中介端子之間距可以不大於頂端子之間距，亦同時可不大於底端子之間距，在POP產品設計上更有調整彈性。
本發明的目的及解決其技術問題是採用以下技術方案來實現的。本發明揭示一種柱頂互連之封裝堆疊方法，首先，提供一載板。之後，在該載板上電鍍形成複數個第一金屬柱與複數個第二金屬柱，其中該些第一金屬柱之複數個第一頂端面係相對於該些第二金屬柱之複數個第二頂端面更加遠離該載板。之後，在該載板上設置一晶片。之後，在該載板上形成一模封膠體，其中該模封膠體係密封該晶片、該些第一金屬柱以及該些第二金屬柱。之後，以平坦化研磨該模封膠體之方式，共平面地顯露出該些第一金屬柱之該些第一頂端面與該些第二金屬柱之該些第二頂端面在該模封膠體之一平坦面。之後，在該平坦面上安裝一頂部封裝構造，並且在該頂部封裝構造與該模封膠體之間介入一中介轉板，該頂部封裝構造係包含複數個頂端子，該中介轉板係包含複數個中介端子，在迴悍過程中，該些頂端子係接合至該中介轉板之對應接墊，該些中介端子係接合至該些第一金屬柱之該些第一頂端面與該些第二金屬柱之該些第二頂端面。
本發明的目的及解決其技術問題還可採用以下技術措施進一步實現。
在前述封裝堆疊方法中，該載板係可為一底部封裝構造之線路基板。
在前述封裝堆疊方法中，該載板之下表面係可接合有複數個底端子。
在前述封裝堆疊方法中，該些第一金屬柱係可電鍍形成於一防焊層上，該些第二金屬柱係電鍍形成於該載板之複數個基板連接墊上。
在前述封裝堆疊方法中，該載板係可為一扇出型晶圓/面板等級封裝製程所使用之暫時載板。
在前述封裝堆疊方法中，該些第一金屬柱係可電鍍形成於一重配置線路層上，該些第二金屬柱係可電鍍形成於該載板上。
藉由上述的技術手段，本發明可以達成中介端子為微間距的封裝堆疊構造(POP)之製作。相較於雷射鑽孔(laser-drilling)類型的封裝堆疊構造的底部封裝構造，本發明採用電鍍金屬柱、模封平坦化研磨的底部封裝構造並搭配中介基板組成一封裝堆疊構造，具備以下功效：第一、縮小底部封裝構造與中介基板對接單元的端子間距，而不會像雷射鑽孔類型有鎔融短接風險；第二、透過模封平坦化研磨，可以露出底部封裝構造的晶片表面，以提高晶片散熱。
10‧‧‧底部封裝構造
11‧‧‧基板
12‧‧‧晶片
13‧‧‧模封膠體
14‧‧‧底端子
15‧‧‧擋牆
20‧‧‧頂部封裝構造
21‧‧‧基板
22‧‧‧晶片
23‧‧‧模封膠體
24‧‧‧銲線
30‧‧‧中介端子
40‧‧‧雷射鑽孔器
50‧‧‧平坦研磨器
100‧‧‧封裝堆疊構造
110‧‧‧載板
120‧‧‧第一金屬柱
121‧‧‧第一頂端面
130‧‧‧第二金屬柱
131‧‧‧第二頂端面
140‧‧‧晶片
141‧‧‧凸塊
150‧‧‧模封膠體
151‧‧‧平坦面
160‧‧‧頂部封裝構造
161‧‧‧頂端子
162‧‧‧晶片
163‧‧‧封膠體
164‧‧‧基板
170‧‧‧中介轉板
171‧‧‧中介端子
172‧‧‧接墊
180‧‧‧底端子
191‧‧‧防焊層
192‧‧‧基板連接墊
200‧‧‧封裝堆疊構造
264‧‧‧重配置線路層
290‧‧‧重配置線路層
第1圖：一種習知封裝堆疊構造(POP)之截面示意圖。
第2圖：在習知封裝堆疊構造之製程中進行雷射鑽孔作業時之底部封裝構造的局部截面示意圖。
第3圖：依據本發明之第一具體實施例，一種柱頂互連之封裝堆疊構造之截面示意圖。
第4A至4F圖：依據本發明之第一具體實施例，繪示一種柱頂互連之封裝堆疊方法中各主步驟之元件截面示意圖。
第5A至5H圖：依據本發明之第二具體實施例，繪示另一種柱頂互連之封裝堆疊方法中各主步驟之元件截面示意圖。
以下將配合所附圖示詳細說明本發明之實施例，然應注意的是，該些圖示均為簡化之示意圖，僅以示意方法來說明本發明之基本架構或實施方法，故僅顯示與本案有關之元件與組合關係，圖中所顯示之元件並非以實際實施之數目、形狀、尺寸做等比例繪製，某些尺寸比例與其他相關尺寸比例或已誇張或是簡化處理，以提供更清楚的描述。實際實施之數目、形狀及尺寸比例為一種選置性之設計，詳細之元件佈局可能更為複雜。
依據本發明之第一具體實施例，一種柱頂互連之封裝堆疊構造100舉例說明於第3圖之截面示意圖。一種柱頂互連之封裝堆疊方法舉例說明於第4A至4F圖各主步驟之元件截面示意 圖。
請參閱第3圖，一種封裝堆疊構造100係包含複數個第一金屬柱120與複數個第二金屬柱130、一晶片140、一模封膠體150以及一頂部封裝構造160。該些第一金屬柱120與該些第二金屬柱130係電鍍形成在一載板110上，其中該些第一金屬柱120之複數個第一頂端面121係相對於該些第二金屬柱130之複數個第二頂端面131更加遠離該載板110。
該晶片140係設置在該載板110上，可為覆晶接合方式設置該晶片140。該模封膠體150係形成在該載板110上，其中該模封膠體150係密封該晶片140、該些第一金屬柱120以及該些第二金屬柱130。其中，以平坦化研磨該模封膠體150之方式，共平面地顯露出該些第一金屬柱120之該些第一頂端面121與該些第二金屬柱130之該些第二頂端面131在該模封膠體150之一平坦面151。該頂部封裝構造160係安裝在該平坦面151上，並且在該頂部封裝構造160與該模封膠體150之間介入一中介轉板170，該頂部封裝構造160係包含複數個頂端子161，該中介轉板170係包含複數個中介端子171。在迴焊過程中，該些頂端子161係接合至該中介轉板170之對應接墊172，該些中介端子171係接合至該些第一金屬柱120之該些第一頂端面121與該些第二金屬柱130之該些第二頂端面131。在本實施例中，該晶片140之背面係不外露於該模封膠體150之平坦面151。
該封裝堆疊構造100之製造方法係進一步說明如 後。首先，請參閱第4A圖，提供一載板110。在本實施例中，該載板110係可為一底部封裝構造之線路基板。該載板110之下表面係可接合有複數個底端子180，其具體結構例如可為矩陣陣列之銲球。該載板110之上表面係形成有一防焊層191，複數個基板連接墊192係不被該防焊層191所覆蓋並電性連接至對應之底端子180。
之後，請參閱第4B圖，在該載板110上電鍍形成複數個第一金屬柱120與複數個第二金屬柱130，其中該些第一金屬柱120之複數個第一頂端面121係相對於該些第二金屬柱130之複數個第二頂端面131更加遠離該載板110；換言之，在相同電鍍柱長度下，該些第一金屬柱120係較高於該些第二金屬柱130。在一具體結構中，該些第一金屬柱120係可電鍍形成於該防焊層191上，該些第二金屬柱130係電鍍形成於該載板110之該些複數個基板連接墊192上。該些第一金屬柱120與該些第二金屬柱130之材質係可包含銅(Cu)。
之後，請參閱第4C圖，在該載板110上設置一晶片140。該晶片140係可包含複數個凸塊141，利用覆晶接合方式，該些凸塊141係接合該載板110之覆晶接墊，並且該晶片140之主動面係朝向該載板110。該些凸塊141係可包含金凸塊或是銅凸塊。該些第一金屬柱120之該些第一頂端面121與該些第二金屬柱130之該些第二頂端面131係應至少高於該晶片140之主動面，但依實際需求，該些第一金屬柱120之該些第一頂端面121與該些第 二金屬柱130之該些第二頂端面131係可高於或不高於該晶片140之背面。
之後，請參閱第4D圖，在該載板110上形成一模封膠體150，其中該模封膠體150係密封該晶片140、該些第一金屬柱120以及該些第二金屬柱130。該模封膠體150係可為一種熱固性絕緣化合物，並以壓縮模封或是轉移模封形成。在本步驟中，該模封膠體150之厚度應大於該些第一金屬柱120之高度，亦應大於該些第二金屬柱130之高度。
之後，請參閱第4E圖，利用一平坦研磨器50平坦化研磨該模封膠體150，藉此一方式，共平面地顯露出該些第一金屬柱120之該些第一頂端面121與該些第二金屬柱130之該些第二頂端面131在該模封膠體150之一平坦面151。
之後，請參閱第4F圖，在該平坦面151上安裝一頂部封裝構造160，並且在該頂部封裝構造160與該模封膠體150之間介入一中介轉板170，該頂部封裝構造160係包含複數個頂端子161，該中介轉板170係包含複數個中介端子171。在迴焊過程中，該些頂端子161係接合至該中介轉板170之對應接墊172，該些中介端子171係接合至該些第一金屬柱120之該些第一頂端面121與該些第二金屬柱130之該些第二頂端面131。此外，該頂部封裝構造160係可更包含一晶片162、一密封該晶片162之封膠體163以及一承載該晶片162之基板164。
因此，本發明提供一種柱頂互連之封裝堆疊方法與 構造，用以防止該封裝堆疊構造100中底部封裝構造的例如中介端子171等中介導通元件的銲料橋接，該些中介端子171能更微間距的排列與微小化，並且底部封裝構造的模封膠體150之平坦面151可不必要地製作重配置線路結構。此外，該些中介端子171之間距可以不大於該些頂端子161之間距，亦同時可不大於該些底端子180之間距，在封裝堆疊構造(POP)的產品設計上更有調整彈性。
依據本發明之第二具體實施例，另一種柱頂互連之封裝堆疊方法舉例說明於第5A至5H圖各主步驟之元件截面示意圖。最後製造得到之封裝堆疊構造200係如第5H圖所示。在本實施例中，該晶片140之背面係外露於該模封膠體150之平坦面151。
首先，請參閱第5A圖，提供一載板110。在本實施例中，該載板110係可為一扇出型晶圓/面板等級封裝製程所使用之暫時載板。該載板110之具體結構係可為一玻璃片或是一金屬片。該載板110上係可預先形成一重配置線路層290。
之後，請參閱第5B圖，在該載板110上電鍍形成複數個第一金屬柱120與複數個第二金屬柱130，其中該些第一金屬柱120之複數個第一頂端面121係相對於該些第二金屬柱130之複數個第二頂端面131更加遠離該載板110。在本實施例中，該些第一金屬柱120係可電鍍形成於一重配置線路層290上，該些第二金屬柱130係可電鍍形成於該載板110上。當該重配置線路層290本身具有尚未移除之晶種層，可在該重配置線路層290與該載板110上分別地直接電鍍形成該些第一金屬柱120與該些第二金屬柱 130。當該載板110上缺乏晶種層，可在該重配置線路層290與該載板110上預先以物理氣相沉積或濺鍍方式全面覆蓋一晶種層，例如鈦/銅(Ti/Cu)，以利金屬柱之電鍍進行。在電鍍完成之後，再使上述晶種層圖案化，以移除晶種層之非線路區域。
之後，請參閱第5C圖，在該載板110上設置一晶片140。該晶片140係能以覆晶接合方式達到晶片安裝。該晶片140之複數個凸塊141係接合至該重配置線路層290。之後，請參閱第5D圖，在該載板110上形成一模封膠體150，其中該模封膠體150係密封該晶片140、該些第一金屬柱120以及該些第二金屬柱130。
之後，請參閱第5E圖，以平坦化研磨該模封膠體150之方式，共平面地顯露出該些第一金屬柱120之該些第一頂端面121與該些第二金屬柱130之該些第二頂端面131在該模封膠體150之一平坦面151。在本實施例中，該晶片140之背面係亦共平面地顯露於該模封膠體150之該平坦面151。
之後，請參閱第5F圖，由該模封膠體150剝離該載板110，以顯露出該模封膠體150之下表面。此外，複數個底端子180係可設置於該重配置線路層290。
之後，請參閱第5G與5H圖，在該平坦面151上安裝一頂部封裝構造160，並且在該頂部封裝構造160與該模封膠體150之間介入一中介轉板170，該頂部封裝構造160係包含複數個頂端子161，該中介轉板170係包含複數個中介端子171。在迴焊過程中，該些頂端子161係接合至該中介轉板170之對應接墊172，該些 中介端子171係接合至該些第一金屬柱120之該些第一頂端面121與該些第二金屬柱130之該些第二頂端面131。此外，該頂部封裝構造160係可更包含一晶片162、一密封該晶片162之封膠體163以及一電性連接該晶片162之重配置線路層264。該頂部封裝構造160係可實質相同於封裝堆疊構造之底部封裝構造。
因此，本發明的一種柱頂互連之封裝堆疊方法實現了中介端子微間距排列的封裝堆疊構造之製造，底部封裝構造中電鍍出各式長度之金屬柱並以模封研磨露出金屬柱之端面，再搭配中介轉板對頂部封裝構造的接合，藉此解決了避免習知中介端子在利用錫球對接時鎔融短接的問題。
以上所揭露的僅為本發明較佳實施例而已，當然不能以此來限定本發明之權利範圍，因此依本發明權利要求所作的等同變化，仍屬本發明所涵蓋的範圍。
100‧‧‧封裝堆疊構造
110‧‧‧載板
120‧‧‧第一金屬柱
121‧‧‧第一頂端面
130‧‧‧第二金屬柱
131‧‧‧第二頂端面
140‧‧‧晶片
141‧‧‧凸塊
150‧‧‧模封膠體
151‧‧‧平坦面
160‧‧‧頂部封裝構造
161‧‧‧頂端子
162‧‧‧晶片
163‧‧‧封膠體
170‧‧‧中介轉板
171‧‧‧中介端子
172‧‧‧接墊
180‧‧‧底端子
191‧‧‧防焊層
192‧‧‧基板連接墊

Claims (10)

  1. 一種柱頂互連之封裝堆疊方法，包含：提供一載板；在該載板上電鍍形成複數個第一金屬柱與複數個第二金屬柱，其中該些第一金屬柱之複數個第一頂端面係相對於該些第二金屬柱之複數個第二頂端面更加遠離該載板；在該載板上設置一晶片；在該載板上形成一模封膠體，其中該模封膠體係密封該晶片、該些第一金屬柱以及該些第二金屬柱；以平坦化研磨該模封膠體之方式，共平面地顯露出該些第一金屬柱之該些第一頂端面與該些第二金屬柱之該些第二頂端面在該模封膠體之一平坦面；以及在該平坦面上安裝一頂部封裝構造，並且在該頂部封裝構造與該模封膠體之間介入一中介轉板，該頂部封裝構造係包含複數個頂端子，該中介轉板係包含複數個中介端子，在迴焊過程中，該些頂端子係接合至該中介轉板之對應接墊，該些中介端子係接合至該些第一金屬柱之該些第一頂端面與該些第二金屬柱之該些第二頂端面。
  2. 如申請專利範圍第1項所述之柱頂互連之封裝堆疊方法，其中該載板係為一底部封裝構造之線路基板。
  3. 如申請專利範圍第2項所述之柱頂互連之封裝堆疊方法，其中該載板之下表面係接合有複數個底端子。
  4. 如申請專利範圍第2項所述之柱頂互連之封裝堆疊方法，其中該些第一金屬柱係電鍍形成於一防焊層上，該些第二金屬柱係電鍍形成於該載板之複數個基板連接墊上。
  5. 如申請專利範圍第1項所述之柱頂互連之封裝堆疊方法，其中該載板係為一扇出型晶圓/面板等級封裝製程所使用之暫時載板。
  6. 如申請專利範圍第5項所述之柱頂互連之封裝堆疊方法，其中該些第一金屬柱係電鍍形成於一重配置線路層上，該些第二金屬柱係電鍍形成於該載板上。
  7. 一種柱頂互連之封裝堆疊構造，包含：複數個第一金屬柱與複數個第二金屬柱，係電鍍形成在一載板上，其中該些第一金屬柱之複數個第一頂端面係相對於該些第二金屬柱之複數個第二頂端面更加遠離該載板；一晶片，係設置在該載板上；一模封膠體，係形成在該載板上，其中該模封膠體係密封該晶片、該些第一金屬柱以及該些第二金屬柱；其中，以平坦化研磨該模封膠體之方式，共平面地顯露出該些第一金屬柱之該些第一頂端面與該些第二金屬柱之該些第二頂端面在該模封膠體之一平坦面，且該些第二金屬柱的高度大於該些第一金屬柱的高度；以及一頂部封裝構造，係安裝在該平坦面上，並且在該頂部封裝構造與該模封膠體之間介入一中介轉板，該頂部封裝構造係包含複數個頂端子，該中介轉板係包含複數個中介端 子，在迴焊過程中，該些頂端子係接合至該中介轉板之對應接墊，該些中介端子係接合至該些第一金屬柱之該些第一頂端面與該些第二金屬柱之該些第二頂端面，其中該些頂端子與該些中介端子位於該中介轉板的相對側。
  8. 如申請專利範圍第7項所述之柱頂互連之封裝堆疊構造，其中該載板係為一底部封裝構造之線路基板。
  9. 如申請專利範圍第8項所述之柱頂互連之封裝堆疊構造，其中該載板之下表面係接合有複數個底端子。
  10. 如申請專利範圍第7項所述之柱頂互連之封裝堆疊構造，其中該模封膠體之下表面係接合有複數個底端子。
TW105118189A 2016-06-08 2016-06-08 柱頂互連之封裝堆疊方法與構造 TWI602269B (zh)

Priority Applications (2)

Application Number Priority Date Filing Date Title
TW105118189A TWI602269B (zh) 2016-06-08 2016-06-08 柱頂互連之封裝堆疊方法與構造
US15/434,071 US20170358557A1 (en) 2016-06-08 2017-02-16 Package-on-package structure and manufacturing method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105118189A TWI602269B (zh) 2016-06-08 2016-06-08 柱頂互連之封裝堆疊方法與構造

Publications (2)

Publication Number Publication Date
TWI602269B true TWI602269B (zh) 2017-10-11
TW201813014A TW201813014A (zh) 2018-04-01

Family

ID=60573050

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105118189A TWI602269B (zh) 2016-06-08 2016-06-08 柱頂互連之封裝堆疊方法與構造

Country Status (2)

Country Link
US (1) US20170358557A1 (zh)
TW (1) TWI602269B (zh)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108538735B (zh) * 2017-03-02 2020-05-29 中芯国际集成电路制造(上海)有限公司 金属凸块装置及其制造方法
DE102018103505A1 (de) * 2018-02-16 2019-08-22 Osram Opto Semiconductors Gmbh Komposithalbleiterbauelement und Verfahren zur Herstellung eines Komposithalbleiterbauelements
KR102086364B1 (ko) * 2018-03-05 2020-03-09 삼성전자주식회사 반도체 패키지
US10937754B1 (en) * 2019-10-06 2021-03-02 Nanya Technology Corporation Semiconductor package and manufacturing method thereof
US11335666B2 (en) * 2020-07-09 2022-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device and manufacturing method thereof

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201226088A (en) * 2010-12-30 2012-07-01 Metal Ind Res & Dev Ct Electrolytic processing method and semi-finished product of electrolytic processing workpiece
TW201236088A (en) * 2011-02-17 2012-09-01 Samsung Electronics Co Ltd Semiconductor package having through substrate via (TSV) interposer and method of manufacturing the semiconductor package
TW201442203A (zh) * 2013-02-11 2014-11-01 Marvell World Trade Ltd 層疊封裝結構
TW201537716A (zh) * 2014-03-25 2015-10-01 Phoenix Pioneer Technology Co Ltd 覆晶堆疊封裝結構及其製作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8372741B1 (en) * 2012-02-24 2013-02-12 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201226088A (en) * 2010-12-30 2012-07-01 Metal Ind Res & Dev Ct Electrolytic processing method and semi-finished product of electrolytic processing workpiece
TW201236088A (en) * 2011-02-17 2012-09-01 Samsung Electronics Co Ltd Semiconductor package having through substrate via (TSV) interposer and method of manufacturing the semiconductor package
TW201442203A (zh) * 2013-02-11 2014-11-01 Marvell World Trade Ltd 層疊封裝結構
TW201537716A (zh) * 2014-03-25 2015-10-01 Phoenix Pioneer Technology Co Ltd 覆晶堆疊封裝結構及其製作方法

Also Published As

Publication number Publication date
US20170358557A1 (en) 2017-12-14
TW201813014A (zh) 2018-04-01

Similar Documents

Publication Publication Date Title
US11177201B2 (en) Semiconductor packages including routing dies and methods of forming same
CN108122861B (zh) 具有虚设管芯的封装结构、半导体装置及其形成方法
US9293449B2 (en) Methods and apparatus for package on package devices with reversed stud bump through via interconnections
US9412678B2 (en) Structure and method for 3D IC package
TWI588965B (zh) 層疊封裝元件及其製造方法
TWI720035B (zh) 半導體裝置與其製造方法
KR100800478B1 (ko) 적층형 반도체 패키지 및 그의 제조방법
TWI602269B (zh) 柱頂互連之封裝堆疊方法與構造
KR20190003403A (ko) 반도체 패키지 및 방법
TWI604591B (zh) 薄型扇出式多晶片堆疊封裝構造及其製造方法
KR20180054419A (ko) 패키지 구조와 그 형성 방법
KR20180030391A (ko) 더미 커넥터를 구비한 반도체 패키지와 이를 형성하는 방법
US20100171206A1 (en) Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
TWI576928B (zh) 模封互連基板及其製造方法
US11004812B2 (en) Package structure and method of forming the same
TWI582917B (zh) 以封膠體取代基板核心之多晶片封裝構造
JP2008277569A (ja) 半導体装置及びその製造方法
US9613910B2 (en) Anti-fuse on and/or in package
US10985101B2 (en) Semiconductor package and manufacturing method thereof
TWI578421B (zh) 可堆疊半導體封裝構造及其製造方法
TW202133282A (zh) 半導體封裝
CN107622996B (zh) 三维高密度扇出型封装结构及其制造方法
CN107301981B (zh) 集成的扇出型封装件以及制造方法
JP5338572B2 (ja) 半導体装置の製造方法
CN114220775A (zh) 半导体装置封装以及形成半导体装置封装的方法