TWI720035B - 半導體裝置與其製造方法 - Google Patents

半導體裝置與其製造方法 Download PDF

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TWI720035B
TWI720035B TW105133468A TW105133468A TWI720035B TW I720035 B TWI720035 B TW I720035B TW 105133468 A TW105133468 A TW 105133468A TW 105133468 A TW105133468 A TW 105133468A TW I720035 B TWI720035 B TW I720035B
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component
semiconductor device
conductive
semiconductor
dielectric
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TW201725661A (zh
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陳煜仁
陳憲偉
葉德強
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台灣積體電路製造股份有限公司
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Abstract

一種半導體裝置包含經垂直堆疊以具有一垂直高度之複數個半導體晶粒及環繞該等經堆疊半導體晶粒之一介電質。該半導體裝置進一步具有位於該等經堆疊半導體晶粒外部且延伸穿過該介電質之一導電柱。在該半導體裝置中，該導電柱之一高度大於該垂直高度。

Description

半導體裝置與其製造方法
本發明實施例係關於一種半導體裝置及製造一半導體裝置之一方法。
涉及半導體裝置之電子裝備在我們之日常生活中不可或缺。隨著電子技術的進步，電子裝備變得更加精密且涉及用於執行所要多功能性之更大數量之積體電路。因此，電子裝備之製造包含愈來愈多之組裝及處理步驟以及用於生產電子裝備中之半導體裝置之材料。因此，需要不斷簡化生產步驟，提高生產效率並降低每一電子裝備之相關聯製造成本。 在製造半導體裝置之操作期間，以包含具有不同熱性質之各種材料之若干個整合式組件來組裝半導體裝置。如此，在半導體裝置固化之後，整合式組件處於非所要組態中。非所要組態將導致半導體裝置之良率損失、組件之間的不良接合性、裂縫產生、組件分層等。此外，半導體裝置之組件包含數量有限且因此成本高之各種金屬材料。組件之非所要組態及半導體裝置之良率降低將進一步加劇材料浪費且因此將提高製造成本。 隨著具有不同材料之不同組件涉及其中及半導體裝置之製造操作之一複雜性提高，修改半導體裝置之一結構及改良製造操作存在更多挑戰。如此，需要不斷改良用於製造半導體之方法及解決以上缺陷。
在某些實施例中，一半導體裝置包含經垂直堆疊以具有一垂直高度之複數個半導體晶粒及環繞該等經堆疊半導體晶粒之一介電質。該半導體裝置進一步具有位於該等經堆疊半導體晶粒外部且延伸穿過介電質之一導電柱。在該半導體裝置中，該導電柱之一高度大於該垂直高度。 在某些實施例中，製造一半導體裝置之一方法包含：提供一基板並在該基板上方放置一導電柱，其中該導電柱之一高度大於約250 μm。該方法進一步包含：在該基板上方且毗鄰該導電柱垂直堆疊複數個半導體晶粒，放置一介電質以環繞該導電柱及該複數個半導體晶粒，並透過該導電柱電連接該複數個半導體晶粒。 在某些實施例中，製造一半導體裝置之一方法包含：垂直堆疊複數個半導體晶粒，提供一基板並在該基板上方放置一導電柱，其中該導電柱之一高度大於約250 μm。該方法進一步包含：毗鄰該導電柱安置該複數個半導體晶粒，放置一介電質以環繞該導電柱及該複數個半導體晶粒，並透過該導電柱電連接該複數個半導體晶粒。
以下揭露內容提供諸多不同實施例或實例以用於實施所提供標的物之不同特徵。下文闡述組件及配置之特定實例以簡化本揭露。當然，此等組件及配置僅係實例且並不意欲係限制性的。舉例而言，在以下說明中，一第一構件形成於一第二構件上方或該第二構件上可包含其中第一構件與第二構件直接接觸而形成之實施例，且亦可包含其中額外構件可形成於第一構件與第二構件之間使得第一構件與第二構件可不直接接觸之實施例。另外，本發明實施例可在各種實例中重複元件符號及/或字母。此重複係出於簡潔及清晰目的且本身並不指示所論述之各種實施例及/或組態之間的一關係。 此外，為便於說明，本文中可使用空間相對術語(諸如「下」、「下方」、「下部」、「上邊」、「上部」及諸如此類)來闡述一個元件或構件與另一(些)元件或構件之關係，如圖中所圖解說明。除圖中所繪示之定向以外，該等空間相對術語亦意欲囊括裝置在使用或操作中之不同定向。亦可以其他方式使設備定向(旋轉90度或處於其他定向)且可相應地以類似方式解釋本文中所使用之空間相對描述符。 在本發明實施例中，提供一3D半導體裝置以累積複數個半導體組件。該等半導體組件被垂直堆疊以便減小半導體裝置所需之面積。半導體裝置中之該等半導體組件藉由至少一個貫穿導電柱與彼此電通信，其中該導電柱沿著經堆疊組件之厚度向上延伸。該導電柱可延伸得實質上高於半導體組件之一堆疊高度。該堆疊高度可包含每一組件之各別厚度及放置於半導體組件之間或半導體組件下方/上方之其他黏合材料或絕緣材料之厚度。透過該高導電柱提供用以製造一3D半導體裝置之一較有效方法。 在圖1中，圖解說明具有複數個半導體組件之一半導體裝置100。半導體裝置100包含一第一組件102及一第二組件104。在某些實施例中，第一組件102可係一系統單晶片(SoC)，且SoC係將一電腦或其他電子系統之所有組件整合至一單個晶片中之一積體電路(IC)。在某些實施例中，第二組件104可係一記憶體裝置(諸如快閃記憶體或動態隨機存取記憶體(DRAM))，且DRAM係將資料之每一位元儲存於一積體電路內之一單獨電容器中的一種類型之隨機存取記憶體。第一組件102與第二組件104可沿著每一組件之厚度垂直堆疊。在某些實施例中，垂直方向被定義為沿著第一組件102之一主動表面102a之一法線方向延伸之方向。在某些實施例中，經堆疊組件可具有如圖1中之一垂直高度H1。主動表面102a被定義為包含主要接點(諸如接墊、RDL、UBM等)、經組態以與第一組件102外部之其他組件或導電跡線連接的表面。 在本發明實施例中，第一組件102與第二組件104可係背側對背側堆疊(背對背堆疊)，且第一組件102具有背向第二組件104之一主動表面104a所面向之方向的主動表面102a。類似於主動表面102a，主動表面104a被定義為包含主要接點(諸如接墊、RDL、UBM等)、經組態以與第二組件104外部之其他組件或導電跡線連接之表面。在某些實施例中，一黏合劑可放置於第一組件102與第二組件104之間以防止一相對移動。 在本發明實施例中，第一組件102之一側壁102b及第二組件104之一側壁104b係由一中層模塑料103環繞。在某些實施例中，中層模塑料103之一第一表面103a與第一組件102之頂部表面102a實質上共面。在某些實施例中，一介電質106位於第一組件102之主動表面102a及中層模塑料103之第一表面103a上方。在某些實施例中，另一介電質108位於第二組件104之主動表面104a及中層模塑料103之一第二表面103c上方。中層模塑料103夾在介電質106與介電質108之間。在某些實施例中，介電質106及介電質108包含一材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗焊劑(SR)、ABF膜及諸如此類。 半導體裝置100進一步包含位於經堆疊組件外部且延伸穿過如圖1中之中層模塑料103的一導電柱132。在某些實施例中，導電柱132係圍繞靠近第一組件102與第二組件104之經堆疊組件之一區放置。在某些實施例中，導電柱132毗鄰包含第一組件102及第二組件104之經堆疊組件。在某些實施例中，導電柱132具有一高度H2，且高度H2大於第一組件102與第二組件104之經堆疊組件之高度H1。在某些實施例中，高度H2可大於250 μm。在某些實施例中，高度H2可大於300 μm。 在某些實施例中，導電柱132自一端形成並沿著平行於經堆疊組件之厚度之方向繼續向上延伸。導電柱132通體僅包含一個晶種層。舉例而言，如圖1中所展示，在每一導電柱132中僅觀察到一個晶種層132b，其中晶種層132b靠近導電跡線之第二部分107b。在某些實施例中，晶種層位於每一導電柱132之另一端。即使導電柱132之高度大於250 μm或者甚至大於300 μm，導電柱132亦以一單個鍍覆操作不間斷地生長，本發明實施例中將在稍後對此做出闡釋。因此，在導電柱132之唯一一端中觀察到唯一一個晶種層。 在某些實施例中，存在一個以上導電柱132，且導電柱132經組態以環繞用於累積第一組件102與第二組件104之經堆疊組件之一區。在某些實施例中，導電柱132經組態以作為介電質106與介電質108之間的一支撐。在某些實施例中，導電柱132可係一TIV (整合式扇出型貫穿通路)。在某些實施例中，導電柱132可包含銅、鋁、鎢、鎳、銲料、金、銀、鈀、鉑、鈦或其合金。 在某些實施例中，導電柱132呈具有各種剖面形狀(諸如圓形形狀、四邊形形狀、矩形、方形、多邊形形狀或諸如此類)之一圓柱形狀。在某些實施例中，導電柱132之一寬度Wt 可小於285 μm。在某些實施例中，毗鄰導電柱132之間的一間隔Ws 大於約2300 μm。在某些實施例中，導電柱132與第二組件104之側壁104b之間的一間隔Wd 大於約150 μm。 在某些實施例中，一累積百分比被定義為一物質之一體積比一特定空間的一比率。在某些實施例中，第一組件102與第二組件104之經堆疊組件比兩個毗鄰導電柱132之間的空間的一累積百分比係約65％至95％。在某些實施例中，累積百分比係約75％至85％。在某些實施例中，第一組件102之一側壁102b與第二組件104之一側壁104b實質上共面。在某些實施例中，第一組件102之一寬度與第二組件104之一寬度實質上相同。在某些實施例中，導電柱132實質上平行於第一組件102之側壁102b或第二組件104之側壁104b。 介電質106及介電質108內部之導電結構包含導電結構之數個部分。在某些實施例中，導電跡線之一第一部分107a形成於介電質106中以將第一組件102電連接至導電柱132或一導體115。第一部分107a位於經堆疊組件之一側上方，或位於第一組件102之該主動表面102a上方。第一部分107a經組態以扇出第一組件102之導電墊。在某些實施例中，導電跡線之第一部分107a可延伸至介電質106之一第一表面106a。第一表面106a係半導體裝置100之一外部表面之一部分。在某些實施例中，一接墊114形成於第一表面106a上以便接納導體115。接墊114亦電連接至導電跡線之第一部分107a。在某些實施例中，接墊114係一凸塊下金屬(UBM)墊，該凸塊下金屬(UBM)墊係用於接納導體115之一可焊接表面。在某些實施例中，接墊114包含金、銀、銅、鎳、鎢、鋁、鈀及/或其合金。在經堆疊組件之另一側上，導電跡線之一第二部分107b形成於介電質108中以將第二組件104電連接至導電柱132。導電跡線之第二部分107b位於經堆疊組件之另一側上方，或位於第二組件104之該主動表面104a上方。第二部分107b經組態以扇出第二組件104之導電墊。在某些實施例中，導電跡線之第二部分107b可延伸至介電質108中以便連接至一熱耗散墊111。在某些實施例中，導電跡線之第一部分107a及導電跡線之第二部分107b分別係整合式半導體封裝之一RDL (重佈層)、PPI (鈍化後互連件)或互連通路。 導電跡線之第一部分107a與第二部分107b由經堆疊組件實體分離且由導電柱132電連接。第一組件102與第二組件104係透過導電跡線之第一部分107a、導電柱132及導電跡線之第二部分107b電連接。在某些實施例中，第一組件102與第二組件104共同執行各種功能，諸如無線訊號傳輸、處理、照明等。 在某些實施例中，一熱耗散墊111視情況放置於介電質108中。導電跡線之第二部分107b將熱耗散墊111連接至導電柱132及第二組件104。來自第一組件102及第二組件104之熱量可透過導電跡線之第一部分107a、導電跡線之第二部分107b與導電柱132之一路徑而藉由熱耗散墊111耗散。 圖2係一半導體裝置300之一實施例。半導體裝置300包含類似於圖1中之半導體100之一結構，因此以相同數字標號指示之元件之細節在本文中不再重複。在某些實施例中，第一組件102之一寬度可小於第二組件104之一寬度。在某些實施例中，第一組件102之寬度可比第二組件104之寬度小100 μm。在某些實施例中，第一組件102之一中心線與第二組件104之一中心線係共線的。在某些實施例中，一距離W1 可被定義為第一組件102之側壁102b與第二組件104之側壁104b之間的一距離。在某些實施例中，距離W1 可大於約50 μm。在某些實施例中，距離W1 可係約50 μm至100 μm。 圖3係一半導體裝置500之一實施例。半導體裝置500包含類似於圖2中之半導體300之一結構，因此以相同數字標號指示之元件之細節在本文中不再重複。在某些實施例中，一底膠110放置於第二組件104與介電質108之間。主動表面104a被底膠110部分地覆蓋。在某些實施例中，底膠110可經組態為一應力消除劑。在某些實施例中，底膠110可包含環氧樹脂、矽石及金屬顆粒。在某些實施例中，底膠110可藉由各種操作來放置，諸如注射。 圖4係一半導體裝置700之一實施例。半導體裝置700包含類似於圖2中之半導體300之一結構，因此以相同數字標號指示之元件之細節在本文中不再重複。在本發明實施例中，半導體裝置700進一步包含第三組件105。在某些實施例中，第三組件105垂直堆疊於第二組件104上且毗鄰第一組件102。在某些實施例中，第一組件102及第三組件105以一間隔W2 橫向放置。在某些實施例中，間隔W2 可大於約100 μm。在某些實施例中，第一組件102之一側壁102b與第二組件104之側壁104b的一寬度W3 可大於50 μm。在某些實施例中，存在兩個以上組件放置於第二組件104上方。類似於第二組件104上方之第一組件102及第三組件105。第一組件102及第三組件105被橫向配置於虛擬表面(與主動表面104a相對之表面)上方。在某些實施例中，第一組件102與第三組件105可係不同類型之組件。在某些實施例中，第二組件104之一寬度實質上等於或大於第一組件102之一寬度與第三組件105之一寬度的一和。 圖5A至圖5D包含製造圖2中之第一組件102與第二組件104之經堆疊組件之一方法之操作。該方法包含若干個操作(201、202、203及204)。在操作201中，提供數個第一組件102，如在圖5A中。在操作202中，提供一晶圓級封裝101，如在圖5B中。在某些實施例中，晶圓級封裝101包含數個第二組件104。在某些實施例中，晶圓級封裝101具有放置於其一主動表面101a上之數個凸塊。將晶圓級封裝101倒置過來且與主動表面101a相對的晶圓級封裝101之一底部表面101b面向上以用於堆疊圖5A中之第一組件102。在操作203中，將圖5A中之第一組件102拾放於晶圓級封裝101之底部表面101b上，如在圖5C中。以一間隔W4 安置第一組件102。在某些實施例中，間隔W4 可大於100 μm。在某些實施例中，可將第二組件104單粒化為圖5A中之第一組件102，而第一組件102呈一晶圓級形式。將第二組件104拾放於第一組件102上。在操作204中，將晶圓級封裝101沿著間隔W4 單粒化以形成第一組件102與第二組件104之數個經堆疊組件，如在圖5D中。在某些實施例中，藉由一機械刀片或雷射刀片將晶圓級封裝101單粒化。 圖6A至圖6F包含製造圖2中之一半導體裝置300之一方法之操作。該方法包含若干個操作(401、402、403、404、405及406)。在操作401中，提供一基板400以作為一載體或支撐。在基板400上方放置介電質108、熱耗散墊111及導電跡線之第二部分107b，如在圖6A中。在某些實施例中，導電跡線之第二部分107b自熱耗散墊111向上延伸至介電質108之一頂部表面108b。稍後，在導電跡線之第二部分107b之一暴露部分上沈積一晶種層132b。在晶種層132b上形成導電柱132且其自介電質108之頂部表面108b進一步向上延伸。在一晶圓級製程中，導電柱132形成為一預定圖案，如在圖6A中。以一最佳化間隔配置某些鄰近導電柱132以便使某些電子組件放置於其之間。 在操作402中，在介電質108之頂部表面108b上及導電柱132之間放置包含圖5D中之第一組件102及第二組件104之經堆疊組件，如在圖6B中。在某些實施例中，第二組件104之頂部表面104a放置於介電質108之頂部表面108b上。在某些實施例中，第二組件104電連接至導電跡線之第二部分107b。 在操作403中，在頂部表面108b上方放置一中層模塑料103且其填充導電柱132與第一組件102和第二組件104之經堆疊組件之間的間隙，如在圖6C中。模塑料可過填充以覆蓋導電柱132及第一組件102與第二組件104之經堆疊組件。引入一移除或平坦化操作以移除中層模塑料103之一部分以便暴露導電柱132之頂部表面132a及第一組件102之頂部表面102a，使得無中層模塑料103存留於導電柱132及第一組件102上。圖6C係展示移除操作之後的結構之一實施例。在某些實施例中，藉由諸如蝕刻或研磨等之一操作同時移除中層模塑料103、導電柱132及第一組件102之頂部部分以便使其共面。 在操作404中，在中層模塑料103、導電柱132及第二組件104上方放置一介電質106，如在圖6D中。在某些實施例中，中層模塑料103包含一聚合材料，諸如環氧樹脂、聚醯亞胺、聚苯并㗁唑(PBO)、抗焊劑(SR)、ABF膜及諸如此類。在某些實施例中，一凹陷部分106b形成於導電柱132之頂部表面132a及第一組件102之頂部表面102a上邊，如在圖6D中。在某些實施例中，藉由光微影移除頂部表面132a及頂部表面102a上邊之介電質106之部分。 放置導電跡線之一 第一部分107a，如在圖6D中。在某些實施例中，導電跡線之第一部分107a係藉由電鍍或濺鍍放置於介電質106上。在某些實施例中，介電質106及導電跡線之第一部分107a可包含至少一個層且被依序放置成層，如在圖6D中。 在某些實施例中，介電質106放置於導電跡線之第一部分107a上且覆蓋半導體裝置之頂部。在某些實施例中，形成一通路106c並放置一接墊114，如在圖6D中。在某些實施例中，藉由移除介電質106在導電跡線之第一部分107a上邊之部分形成通路106c。在某些實施例中，介電質106之一部分係藉由光微影移除以通路106c。在某些實施例中，通路106c呈一楔形組態。 在某些實施例中，在導電跡線之第一部分107a之一區段107a-l及介電質106上邊形成接墊114。在某些實施例中，接墊114填充通路106c且自介電質106之頂部表面106a延伸至導電跡線之第一部分107a之區段107a-l，使得接墊114與導電跡線之第一部分107a電連接。在某些實施例中，接墊114係一凸塊下金屬(UBM)墊，該凸塊下金屬墊係用於接納一凸塊且電連接接墊114與第一組件102外部之電路的一可焊接表面。 在操作405中，在接墊114上放置一凸塊115，如在圖6E中。在某些實施例中，凸塊115係一銲料凸塊、銲球及銲料膏或諸如此類。在某些實施例中，凸塊115經組態以與另一晶粒、另一基板或另一半導體封裝上之一墊附接。在某些實施例中，凸塊115係一導電凸塊或一導電接頭。在某些實施例中，第一組件102透過導電跡線之第一部分107a及接墊114與凸塊115電連接。 在操作406中，自半導體裝置移除圖6E中之基板400，如在圖6F中。在某些實施例中，自基板400拆卸半導體裝置以用於後續操作。 將圖6E中所展示之結構倒置並附接至圖6F之底部處之另一基板120。基板120可係一封裝基板、板(例如，一印刷電路板(PCB))、一晶圓、一晶粒、一中介層基板或其他適合基板。透過各種導電附接點將凸塊結構耦合至基板120。舉例而言，在基板120上形成一導電區122並將其圖案化。導電區122係一接點墊或一導電跡線之一部分，其由一遮罩層124呈現。在一項實施例中，遮罩層124係在基板120上形成並被圖案化以暴露導電區122之一抗焊劑層。遮罩層124具有一遮罩開口，該開口提供用於形成焊接接頭之一窗口。舉例而言，可在導電區122上提供包含錫、鉛、銀、銅、鎳、鉍之合金或其組合之一銲料層。可透過接墊114與導電區122之間的一接頭銲料結構126將半導體裝置耦合至基板120。一例示性耦合製程包含一助焊劑施塗、晶片安置、熔融焊接接頭之回銲及/或助焊劑殘餘物清洗。半導體基板102、接頭銲料結構126及其他基板120可稱作一封裝總成，或在本發明實施例中稱作一覆晶封裝總成。 在某些實施例中，半導體裝置藉由一封裝凸塊與另一封裝接合以變成一堆疊式封裝(PoP)。在某些實施例中，半導體裝置透過封裝凸塊與另一封裝電連接。在某些實施例中，半導體裝置之數個導電部件與另一封裝之數個封裝墊透過數個封裝凸塊對應地接合以變成一PoP。 圖7A至圖7G包含製造圖1中之一半導體裝置100之一方法之操作。該方法包含若干個操作(601、602、603、604、605、606及607)。在操作601中，提供圖6A中之一半成品半導體裝置，如在圖7A中。在操作602中，在介電質108之一頂部表面108b上放置銲料膏，如在圖7B中。在操作603中，在導電柱132之間***第二組件104並藉由銲料膏將其電連接至導電跡線之第二部分107b，如在圖7C中。在某些實施例中，某些凸塊放置於第二組件104之一頂部表面104a上並連接至銲料膏以將第二組件104電連接至導電跡線之第二部分107b。在操作604中，在第二組件104之一底部表面104b上堆疊一第一組件102，如在圖7D中。 在操作605中，在頂部表面108b上方放置中層模塑料103且其填充導電柱132與第一組件102和第二組件104之經堆疊組件之間的間隙，如在圖7E中。引入一研磨操作以移除多餘模塑料以便暴露導電柱132之頂部表面132a及第一組件102之頂部表面102a。如圖7E中所展示，形成一平坦表面且暴露導電柱132及第一組件102之接點以便接納放置於其上之其他導電結構。在操作606中，形成一介電質106、導電跡線之一第一部分107a及一接墊114，如在圖7F中。在操作607中，放置一凸塊且將半導體裝置連接至另一基板，如在圖7G中。 在某些實施例中，一半導體裝置包含經垂直堆疊以具有一垂直高度之複數個半導體晶粒及環繞該等經堆疊半導體晶粒之一介電質。該半導體裝置進一步具有位於該等經堆疊半導體晶粒外部且延伸穿過介電質之一導電柱。在該半導體裝置中，該導電柱之一高度大於該垂直高度。 在某些實施例中，製造一半導體裝置之一方法包含：提供一基板並在該基板上方放置一導電柱，其中該導電柱之一高度大於約250 μm。該方法進一步包含：在該基板上方且毗鄰該導電柱垂直堆疊複數個半導體晶粒，放置一介電質以環繞該導電柱及該複數個半導體晶粒，並透過該導電柱電連接該複數個半導體晶粒。 在某些實施例中，製造一半導體裝置之一方法包含：垂直堆疊複數個半導體晶粒，提供一基板並在該基板上方放置一導電柱，其中該導電柱之一高度大於約250 μm。該方法進一步包含：毗鄰該導電柱安置該複數個半導體晶粒，放置一介電質以環繞該導電柱及該複數個半導體晶粒，並透過該導電柱電連接該複數個半導體晶粒。 前述內容概述數項實施例之特徵，使得熟習此項技術者可較好地理解本發明實施例之態樣。熟習此項技術者應瞭解，其可容易地將本發明實施例用作用於設計或修改其他程序及結構之一基礎以實現相同目的及/或達成本文中所引入之實施例之相同優勢。熟習此項技術者亦應意識到，此等等效構造並不脫離本發明實施例之精神及範疇，且應意識到其可在不脫離本發明實施例之精神及範疇之情況下在本文中作出各種改變、替代及更改。
100‧‧‧半導體裝置/半導體101‧‧‧晶圓級封裝101a‧‧‧主動表面101b‧‧‧底部表面102‧‧‧第一組件102a‧‧‧主動表面/頂部表面102b‧‧‧側壁103‧‧‧中層模塑料103a‧‧‧第一表面103c‧‧‧第二表面104‧‧‧第二組件104a‧‧‧主動表面/頂部表面104b‧‧‧側壁/底部表面105‧‧‧第三組件106‧‧‧介電質106a‧‧‧第一表面/頂部表面106b‧‧‧凹陷部分106c‧‧‧通路107a‧‧‧第一部分107a-1‧‧‧區段107b‧‧‧第二部分108‧‧‧介電質108b‧‧‧頂部表面110‧‧‧底膠111‧‧‧熱耗散墊114‧‧‧接墊115‧‧‧導體/凸塊120‧‧‧基板122‧‧‧導電區124‧‧‧遮罩層126‧‧‧接頭銲料結構132‧‧‧導電柱132a‧‧‧頂部表面132b‧‧‧晶種層201‧‧‧操作202‧‧‧操作203‧‧‧操作204‧‧‧操作300‧‧‧半導體裝置/半導體400‧‧‧基板401‧‧‧操作402‧‧‧操作403‧‧‧操作404‧‧‧操作405‧‧‧操作406‧‧‧操作500‧‧‧半導體裝置601‧‧‧操作602‧‧‧操作603‧‧‧操作604‧‧‧操作605‧‧‧操作606‧‧‧操作607‧‧‧操作700‧‧‧半導體裝置H1‧‧‧垂直高度/高度H2‧‧‧高度W1‧‧‧距離W2‧‧‧間隔W3‧‧‧寬度W4‧‧‧間隔Wd‧‧‧間隔Ws‧‧‧間隔Wt‧‧‧寬度
當搭配附圖閱讀時，依據以下詳細說明最佳地理解本發明實施例之態樣。應注意，根據行業中之標準實踐，各種構件未按比例繪製。實際上，為論述之清晰起見，可任意地增大或減小各種構件之尺寸。 圖1係根據某些實施例之一半導體裝置之一示意圖。 圖2係根據某些實施例之一半導體裝置之一示意圖。 圖3係根據某些實施例之一半導體裝置之一示意圖。 圖4係根據某些實施例之一半導體裝置之一示意圖。 圖5A至圖5D係製造根據某些實施例之一經堆疊組件之一方法之流程圖。 圖6A至圖6F係製造根據某些實施例之一半導體裝置之一方法之流程圖。 圖7A至圖7G係製造根據某些實施例之一半導體裝置之一方法之流程圖。
100‧‧‧半導體裝置/半導體
102‧‧‧第一組件
102a‧‧‧主動表面/頂部表面
102b‧‧‧側壁
103‧‧‧中層模塑料
103a‧‧‧第一表面
103c‧‧‧第二表面
104‧‧‧第二組件
104a‧‧‧主動表面/頂部表面
104b‧‧‧側壁/底部表面
106‧‧‧介電質
106a‧‧‧第一表面/頂部表面
107a‧‧‧第一部分
107b‧‧‧第二部分
108‧‧‧介電質
111‧‧‧熱耗散墊
114‧‧‧接墊
115‧‧‧導體/凸塊
132‧‧‧導電柱
132b‧‧‧晶種層
H1‧‧‧垂直高度/高度
H2‧‧‧高度
Wd‧‧‧間隔
Ws‧‧‧間隔
Wt‧‧‧寬度

Claims (10)

  1. 一種半導體裝置，其包括：複數個半導體晶粒，其經垂直堆疊以具有一垂直高度；一介電質，其環繞該等經堆疊半導體晶粒；及一導電柱，其位於該等經堆疊半導體晶粒外部且延伸穿過該介電質；其中該導電柱之一高度大於該垂直高度，該複數個半導體晶粒包含一第一組件及一第二組件，且該第一組件與該第二組件係背側對背側垂直地堆疊，該第一組件之主動表面與該第二組件之主動表面分別面對該介電質之相對的一第一側與一第二側，該第一組件之主動表面與該介電質之該第一側的距離小於該第二組件之主動表面與該介電質之該第二側的距離，且該第一組件之一寬度小於該第二組件之一寬度。
  2. 如請求項1之半導體裝置，其中該導電柱之該高度大於約250um。
  3. 如請求項1之半導體裝置，其中該導電柱之一寬度小於約285um。
  4. 如請求項1之半導體裝置，其中該第一組件之該寬度與該第二組件之該寬度之間的一差大於約100um。
  5. 如請求項1之半導體裝置，其進一步包括一第三組件，其中該第三組件垂直地堆疊於該第二組件上且毗鄰於該第一組件。
  6. 如請求項5之半導體裝置，其中該第二組件之一寬度大於該第一組件之一寬度與該第三組件之一寬度的一和。
  7. 如請求項1之半導體裝置，其中該半導體裝置進一步包括一熱耗散墊，該熱耗散墊電連接至該複數個半導體晶粒且經組態以自該複數個半導體晶粒耗散一熱量。
  8. 如請求項1之半導體裝置，其進一步包括複數個導電柱，其中該複數個該導電柱環繞該複數個半導體晶粒。
  9. 一種製造一半導體裝置之方法，其包括：提供一基板；在該基板上方安置一導電柱，其中該導電柱之一高度大於約250um；在該基板上方且毗鄰於該導電柱而垂直地堆疊複數個半導體晶粒；安置一介電質以環繞該導電柱及該複數個半導體晶粒；及透過該導電柱電連接該複數個半導體晶粒。
  10. 一種製造一半導體裝置之方法，其包括：垂直地堆疊複數個半導體晶粒；提供一基板； 在該基板上方安置一導電柱，其中該導電柱之一高度大於約250um；毗鄰於該導電柱而放置該複數個半導體晶粒；及安置一介電質以環繞該導電柱及該複數個半導體晶粒；及透過該導電柱電連接該複數個半導體晶粒。
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