TWI601385B

TWI601385B - Delay circuits

Info

Publication number: TWI601385B
Application number: TW105123175A
Authority: TW
Inventors: 莊勝智; 吳韋忠; 陳斯祺
Original assignee: 世界先進積體電路股份有限公司
Priority date: 2016-07-22
Filing date: 2016-07-22
Publication date: 2017-10-01
Also published as: TW201810945A

Description

延遲電路 Delay circuit

本發明係有關於一種延遲電路，特別是有關於一種延遲電路，其根據延遲控制信號的上升與下降斜率來決定延遲時間。 The present invention relates to a delay circuit, and more particularly to a delay circuit that determines the delay time based on the rising and falling slopes of the delay control signal.

延遲電路是一種可將輸入信號延遲一特定時間後成為輸出信號的電路。因此，將一信號輸入延遲電路後，其所輸出的延遲信號與輸入信號之間即可產生該特定時間的延遲。近來，隨著製程技術越來越先進，系統電路的操作速度變的越來越快，整合在同一晶片內的電路也越來越多。因此，每個電路之間的時脈同步變得相當重要。尤其是在高速的系統中，時脈偏移(clock skew)將是一個決定系統性能優劣的重要因素。而延遲電路則廣泛地應用在消除時脈偏移。在現有的延遲電路中，藉由增加電容與電阻元件的數量，或者藉由增加反向器的數量來達成目標延遲時間。然而，元件的增加卻導致整體電路的面積變大。 A delay circuit is a circuit that delays an input signal to an output signal after a certain period of time. Therefore, after a signal is input to the delay circuit, a delay of the specific time can be generated between the delayed signal outputted from the input signal and the input signal. Recently, as process technology has become more advanced, the operating speed of system circuits has become faster and faster, and circuits integrated in the same wafer have become more and more. Therefore, the clock synchronization between each circuit becomes quite important. Especially in high-speed systems, clock skew will be an important factor in determining system performance. Delay circuits are widely used to eliminate clock skew. In existing delay circuits, the target delay time is achieved by increasing the number of capacitors and resistive elements, or by increasing the number of inverters. However, an increase in components leads to an increase in the area of the overall circuit.

本發明提供一種延遲電路，其包括電壓產生電路以及信號產生電路。電壓產生電路接收輸入信號，且產生第一控制電壓以及第二控制電壓。信號產生電路受控於第一控制電壓以及第二控制電壓，以產生輸出信號。第一控制電壓決定輸出信號的下降緣相對於輸入信號的下降緣的第一延遲時間。第二控制電壓決定輸出信號的上升緣相對於輸入信號的上升緣的第二延遲時間。 The present invention provides a delay circuit including a voltage generating circuit and a signal generating circuit. The voltage generating circuit receives the input signal and generates a first control voltage and a second control voltage. The signal generation circuit is controlled by the first control voltage and the second control voltage to generate an output signal. The first control voltage determines the loss The first delay time of the falling edge of the outgoing signal relative to the falling edge of the input signal. The second control voltage determines a second delay time of the rising edge of the output signal relative to the rising edge of the input signal.

本發明又提供一種延遲電路，其包括第一P型電晶體、第一N型電晶體、第二P型電晶體、第二N型電晶體、以及反向器。第一P型電晶體具有耦接第一低操作電壓的閘極、接收輸入信號的源極、以及耦接第一節點的汲極。第一N型電晶體具有耦接第一高操作電壓的閘極、接收輸入信號的汲極、以及耦接第二節點的源極。第二P型電晶體具有耦接第一節點的閘極、耦接第二高操作電壓的源極、以及耦接第三節點的汲極。第二N型電晶體具有耦接第二節點的閘極、耦接第三節點的汲極、以及耦接第二低操作電壓的源極。反向器耦接第三節點，且產生延遲於輸入信號的輸出信號。第一P型電晶體與第一N型電晶體同時地導通。 The present invention further provides a delay circuit including a first P-type transistor, a first N-type transistor, a second P-type transistor, a second N-type transistor, and an inverter. The first P-type transistor has a gate coupled to the first low operating voltage, a source receiving the input signal, and a drain coupled to the first node. The first N-type transistor has a gate coupled to the first high operating voltage, a drain receiving the input signal, and a source coupled to the second node. The second P-type transistor has a gate coupled to the first node, a source coupled to the second high operating voltage, and a drain coupled to the third node. The second N-type transistor has a gate coupled to the second node, a drain coupled to the third node, and a source coupled to the second low operating voltage. The inverter is coupled to the third node and generates an output signal delayed by the input signal. The first P-type transistor is turned on simultaneously with the first N-type transistor.

1‧‧‧延遲電路 1‧‧‧Delay circuit

10‧‧‧電壓產生電路 10‧‧‧Voltage generation circuit

11‧‧‧信號產生電路 11‧‧‧Signal generation circuit

20、22‧‧‧PMOS電晶體 20, 22‧‧‧ PMOS transistor

21、23‧‧‧NMOS電晶體 21, 23‧‧‧ NMOS transistor

100‧‧‧升壓元件 100‧‧‧Boost components

101‧‧‧降壓元件 101‧‧‧Reducing components

110‧‧‧PMOS電晶體 110‧‧‧ PMOS transistor

111‧‧‧NMOS電晶體 111‧‧‧NMOS transistor

112‧‧‧反向器 112‧‧‧ reverser

DT30‧‧‧上升延遲時間 DT30‧‧‧Rise delay time

DT31‧‧‧下降延遲時間 DT31‧‧‧Down delay time

IN‧‧‧輸入信號 IN‧‧‧ input signal

N10、N11、N12、N20‧‧‧節點 N10, N11, N12, N20‧‧‧ nodes

OUT‧‧‧輸出信號 OUT‧‧‧ output signal

S12‧‧‧延遲控制信號 S12‧‧‧ Delay control signal

V11、V12‧‧‧控制電壓 V11, V12‧‧‧ control voltage

VDD、VDD40、VSS、VSS40‧‧‧操作電壓 VDD, VDD40, VSS, VSS40‧‧‧ Operating voltage

第1圖表示根據本發明一實施例的延遲電路。 Figure 1 shows a delay circuit in accordance with an embodiment of the present invention.

第2圖表示根據本發明另一實施例的延遲電路。 Fig. 2 shows a delay circuit in accordance with another embodiment of the present invention.

第3圖表示根據本發明的延遲電路的主要信號的波形。 Figure 3 shows the waveform of the main signal of the delay circuit according to the present invention.

第4圖表示根據本發明另一實施例的延遲電路。 Figure 4 shows a delay circuit in accordance with another embodiment of the present invention.

為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。 The above described objects, features and advantages of the present invention will become more apparent from the description of the appended claims.

第1圖是表示根據本發明一實施例的延遲電路。參閱第1圖，延遲電路1接收輸入信號IN，且產生延遲於輸入信號IN的輸出信號OUT。在此實施例中，輸入信號IN為具有至少一脈波的信號。換句話說，輸入信號IN的位準在一高位準與一低位準之間切換，且延遲於輸入信號IN的輸出信號OUT的位準也在一高位準與一低位準之間切換。延遲電路1包括電壓產生電路10以及信號產生電路11。信號產生電路11包括P型金氧半(P-type metal-oxide-semiconductor，PMOS)電晶體110、N型金氧半(N-type metal-oxide-semiconductor，NMOS)電晶體111、以及反向器112。PMOS電晶體110的閘極耦接電壓產生器10於節點N10，其源極耦接操作電壓VDD，且其汲極耦接節點N12。NMOS電晶體111的閘極耦接電壓產生器10於節點N11，其汲極耦接節點N12，且其源極耦接操作電壓VSS。在此實施例中，操作電壓VDD例如為1.8伏特(V)；而操作電壓VSS低於操作電壓VDD，例如0V或低於0V。反向器112耦接節點N12，且產生延遲電路1的輸出信號OUT。 Figure 1 is a diagram showing a delay circuit in accordance with an embodiment of the present invention. Referring to FIG. 1, the delay circuit 1 receives the input signal IN and generates an output signal OUT delayed by the input signal IN. In this embodiment, the input signal IN is a signal having at least one pulse wave. In other words, the level of the input signal IN is switched between a high level and a low level, and the level of the output signal OUT delayed by the input signal IN is also switched between a high level and a low level. The delay circuit 1 includes a voltage generating circuit 10 and a signal generating circuit 11. The signal generating circuit 11 includes a P-type metal-oxide-semiconductor (PMOS) transistor 110, an N-type metal-oxide-semiconductor (NMOS) transistor 111, and a reverse 112. The gate of the PMOS transistor 110 is coupled to the voltage generator 10 at the node N10, the source of which is coupled to the operating voltage VDD, and the drain of which is coupled to the node N12. The gate of the NMOS transistor 111 is coupled to the voltage generator 10 at the node N11, the drain of which is coupled to the node N12, and the source of which is coupled to the operating voltage VSS. In this embodiment, the operating voltage VDD is, for example, 1.8 volts (V); and the operating voltage VSS is lower than the operating voltage VDD, such as 0V or below 0V. The inverter 112 is coupled to the node N12 and generates an output signal OUT of the delay circuit 1.

電壓產生電路10接收延遲電路1的輸入信號IN。電壓產生電路10產生控制電壓V10與V11，且將控制電壓V10與V11分別提供至節點N10與N11。當輸入信號IN的位準由低位準切換為高位準時，電壓產生電路10所產生的控制電壓V10使PMOS電晶體110關閉。同時地，當輸入信號IN的位準由低位準切換為高位準時，電壓產生電路10產生控制電壓V11至節點N11。在此實施例中，電壓產生電路10此時所產生控制電壓V11具有一高位準，但無法完全地導通NMOS電晶體111。因此，節點N12上的延遲控制信號S12的位準無法立刻由操作電壓VDD的位準下降至操作電壓VSS的位準，而是以一下降斜率來逐漸地下降至操作電壓VSS的位準。在此實施例中，上述的下降斜率是取決於控制電壓V11。詳細來說，上述的下降斜率是由當輸入信號IN的位準由低位準切換為高位準時電壓產生電路10所產生的控制電壓V11所決定的。反向器112耦接節點N12以接收延遲控制信號S12。根據上述，延遲控制信號S12的位準是逐漸地下降。因此，當延遲控制信號S12的位準下降至一臨界位準時，反向器112才會將輸出信號OUT切換為高位準。 The voltage generating circuit 10 receives the input signal IN of the delay circuit 1. The voltage generating circuit 10 generates control voltages V10 and V11, and supplies control voltages V10 and V11 to the nodes N10 and N11, respectively. When the level of the input signal IN is switched from the low level to the high level, the control voltage V10 generated by the voltage generating circuit 10 turns off the PMOS transistor 110. Simultaneously, when the level of the input signal IN is switched from the low level to the high level, the voltage generating circuit 10 generates the control voltage V11 to the node N11. In this embodiment, the voltage generating circuit 10 generates a high level of the control voltage V11 at this time, but cannot completely turn on the NMOS transistor 111. Therefore, the festival The level of the delay control signal S12 at the point N12 cannot be immediately lowered from the level of the operating voltage VDD to the level of the operating voltage VSS, but is gradually lowered to the level of the operating voltage VSS with a falling slope. In this embodiment, the above-described falling slope is dependent on the control voltage V11. In detail, the above-described falling slope is determined by the control voltage V11 generated by the voltage generating circuit 10 when the level of the input signal IN is switched from the low level to the high level. The inverter 112 is coupled to the node N12 to receive the delay control signal S12. According to the above, the level of the delay control signal S12 is gradually decreased. Therefore, when the level of the delay control signal S12 falls to a critical level, the inverter 112 switches the output signal OUT to a high level.

當輸入信號IN的位準由高位準切換為低位準時，電壓產生電路10所產生的控制電壓V11使NMOS電晶體111關閉。同時地，當輸入信號IN的位準由高位準切換為低位準時，電壓產生電路10產生控制電壓V10至節點N10。在此實施例中，電壓產生電路10此時所產生控制電壓V10具有一低位準，但無法完全地導通PMOS電晶體110。因此，節點N12上的延遲控制信號S12的位準無法立刻由操作電壓VSS的位準上升至操作電壓VDD的位準，而是以一上升斜率來逐漸地上升至操作電壓VDD的位準。在此實施例中，上述的上升斜率是取決於控制電壓V10。詳細來說，上述的上升斜率是由當輸入信號IN的位準由高位準切換為低位準時電壓產生電路10所產生的控制電壓V10所決定的。反向器112耦接節點N12以接收延遲控制信號S12。根據上述，延遲控制信號S12的位準是逐漸地上升。因此，當延遲控制信號S12的位準上升至一臨界位準時，反向器112才會將輸出信號OUT切換為低位準。 When the level of the input signal IN is switched from the high level to the low level, the control voltage V11 generated by the voltage generating circuit 10 turns off the NMOS transistor 111. Simultaneously, when the level of the input signal IN is switched from the high level to the low level, the voltage generating circuit 10 generates the control voltage V10 to the node N10. In this embodiment, the voltage generating circuit 10 generates a low level of the control voltage V10 at this time, but cannot completely turn on the PMOS transistor 110. Therefore, the level of the delay control signal S12 on the node N12 cannot be immediately raised from the level of the operating voltage VSS to the level of the operating voltage VDD, but gradually rises to the level of the operating voltage VDD with a rising slope. In this embodiment, the above-described rising slope is dependent on the control voltage V10. In detail, the above-described rising slope is determined by the control voltage V10 generated by the voltage generating circuit 10 when the level of the input signal IN is switched from the high level to the low level. The inverter 112 is coupled to the node N12 to receive the delay control signal S12. According to the above, the level of the delay control signal S12 is gradually increased. Therefore, when the level of the delay control signal S12 rises to a critical level, the inverter 112 switches the output signal OUT to a low level.

根據上述可得知，延遲控制信號S12是隨著輸入信號IN的位準切換而逐漸下降與上升，使得輸出信號OUT的上升緣延遲於輸入信號IN的上升緣，且輸出信號OUT的下降緣也延遲於輸入信號IN的下降緣。此外，延遲控制信號S12的下降斜率是取決於控制電壓V11，且其上升斜率是取決於控制電壓V10。因此，輸出信號OUT的上升緣相對於輸入信號IN的上升緣的上升延遲時間是由控制電壓V11所決定，且輸出信號OUT的下降緣相對於輸入信號IN的下降緣的下降延遲時間則是由控制電壓V10所決定。與習知的延遲電路比較起來，本案的延遲電路1不須透過增加電容與電阻元件的數量或者藉由增加反向器的數量來達成目標延遲時間。根據本案延遲電路1的操作，僅需改變控制電壓V10與V11的大小來改變延遲控制信號S12的下降斜率與上升斜率，藉此改變輸出信號OUT相對於輸入信號IN的上升延遲時間與下降延遲時間。在一實施例中，上升延遲時間等於下降延遲時間。 As can be seen from the above, the delay control signal S12 gradually decreases and rises as the input signal IN switches, so that the rising edge of the output signal OUT is delayed by the rising edge of the input signal IN, and the falling edge of the output signal OUT is also Delayed by the falling edge of the input signal IN. Further, the falling slope of the delay control signal S12 is dependent on the control voltage V11, and its rising slope is dependent on the control voltage V10. Therefore, the rising delay time of the rising edge of the output signal OUT with respect to the rising edge of the input signal IN is determined by the control voltage V11, and the falling delay time of the falling edge of the output signal OUT with respect to the falling edge of the input signal IN is Control voltage V10 is determined. Compared with the conventional delay circuit, the delay circuit 1 of the present invention does not need to increase the number of capacitors and resistance elements or increase the number of inverters to achieve the target delay time. According to the operation of the delay circuit 1 of the present invention, only the magnitudes of the control voltages V10 and V11 need to be changed to change the falling slope and the rising slope of the delay control signal S12, thereby changing the rising delay time and the falling delay time of the output signal OUT with respect to the input signal IN. . In an embodiment, the rise delay time is equal to the fall delay time.

第2圖是表示根據本發明另一實施例的延遲電路。在第1與2圖中，相同的元件係以相同的符號來標示。第2圖的實施例將進一步敘述電壓產生電路10與反向器112的可能實施方式。參閱第2圖，電壓產生電路10包括升壓元件100以及降壓元件101。降壓元件101接收操作電壓VDD。當輸入信號IN的位準由低位準切換為高位準時，降壓元件101產生小於操作電壓VDD的控制電壓V11至節點N11，用於導通NMOS電晶體111。升壓元件100接收操作電壓VSS。當輸入信號IN的位準由高位準切換為低位準時，升壓單元100產生大於操作電壓VSS 的控制電壓V10至節點N10，用以導通PMOS電晶體110。 Fig. 2 is a diagram showing a delay circuit according to another embodiment of the present invention. In the first and second figures, the same elements are denoted by the same reference numerals. A possible implementation of voltage generating circuit 10 and inverter 112 will be further described in the embodiment of FIG. Referring to FIG. 2, the voltage generating circuit 10 includes a boosting element 100 and a step-down element 101. The buck element 101 receives the operating voltage VDD. When the level of the input signal IN is switched from the low level to the high level, the step-down element 101 generates a control voltage V11 that is smaller than the operating voltage VDD to the node N11 for turning on the NMOS transistor 111. The boosting element 100 receives the operating voltage VSS. When the level of the input signal IN is switched from the high level to the low level, the boosting unit 100 generates a voltage greater than the operating voltage VSS. The control voltage V10 to the node N10 is used to turn on the PMOS transistor 110.

在一實施例中，升壓元件100係以PMOS電晶體20來實施，且下降元件101係以NMOS電晶體21來實施。PMOS電晶體20的閘極耦接操作電壓VSS，其源極接收輸入信號IN，且其汲極耦接節點N10。NMOS電晶體21的閘極耦接電壓VDD，其汲極接收輸入信號IN，且其源極耦接節點N11。根據升壓元件100與降壓元件101的電路架構可知，當延遲電路1被供電時，PMOS電晶體20與NMOS電晶體21都處於常導通的狀態。換句話說，PMOS電晶體20與NMOS電晶體21同時地導通。 In one embodiment, boosting element 100 is implemented with PMOS transistor 20 and falling element 101 is implemented with NMOS transistor 21. The gate of the PMOS transistor 20 is coupled to the operating voltage VSS, the source thereof receives the input signal IN, and the drain thereof is coupled to the node N10. The gate of the NMOS transistor 21 is coupled to the voltage VDD, the drain thereof receives the input signal IN, and the source thereof is coupled to the node N11. According to the circuit architecture of the boosting element 100 and the step-down element 101, when the delay circuit 1 is powered, both the PMOS transistor 20 and the NMOS transistor 21 are in a normally-on state. In other words, the PMOS transistor 20 is turned on simultaneously with the NMOS transistor 21.

參閱第2圖，反向器112包括PMOS電晶體22以及NMOS電晶體23。PMOS電晶體22的閘極耦接節點N12，其源極耦接操作電壓VDD，且其汲極耦接節點N20。NMOS電晶體23閘極耦接節點N12，其汲極耦接節點N20，且其源極耦接操作電壓VSS。以下將說明第2圖實施例中的延遲電路的操作。 Referring to FIG. 2, the inverter 112 includes a PMOS transistor 22 and an NMOS transistor 23. The gate of the PMOS transistor 22 is coupled to the node N12, the source of which is coupled to the operating voltage VDD, and the drain of which is coupled to the node N20. The gate of the NMOS transistor 23 is coupled to the node N12, the drain of the node is coupled to the node N20, and the source thereof is coupled to the operating voltage VSS. The operation of the delay circuit in the embodiment of Fig. 2 will be explained below.

參閱第2與3圖，當輸入信號IN的位準由操作電壓VSS的位準切換為操作電壓VDD的位準時，控制電壓V10等於操作電壓VDD，使得PMOS電晶體110關閉。同時地，當輸入信號IN的位準由操作電壓VSS的位準切換為操作電壓VDD的位準時，控制電壓V11等於操作電壓VDD減去NMOS電晶體21的臨界電壓V_TH(V11=VDD-V_TH)。由於NMOS電晶體111的閘極上的電壓(即控制電壓V11)小於操作電壓VDD，因此NMOS電晶體111無法完全地導通。如此一來，節點N12上的延遲控制信號S12的位準無法立刻由操作電壓VDD的位準下降至操作電壓VSS的位準，而是以一下降斜率來逐漸地下降至操作電壓VSS的位準。根據此實施例，上述的下降斜率是由當輸入信號IN的位準由操作電壓VSS的位準切換為操作電壓VDD的位準時所產生的控制電壓V11所決定的。當延遲控制信號S12的位準下降至一臨界位準時，PMOS電晶體22導通，使得節點N20上的輸出信號的位準由操作電壓VSS的位準切換為操作電壓VDD的位準。 Referring to FIGS. 2 and 3, when the level of the input signal IN is switched from the level of the operating voltage VSS to the level of the operating voltage VDD, the control voltage V10 is equal to the operating voltage VDD, so that the PMOS transistor 110 is turned off. Simultaneously, when the level of the input signal IN is switched from the level of the operating voltage VSS to the level of the operating voltage VDD, the control voltage V11 is equal to the operating voltage VDD minus the threshold voltage V _{TH of the} NMOS transistor 21 (V11=VDD-V). _TH ). Since the voltage on the gate of the NMOS transistor 111 (ie, the control voltage V11) is smaller than the operating voltage VDD, the NMOS transistor 111 cannot be completely turned on. As a result, the level of the delay control signal S12 on the node N12 cannot be immediately lowered from the level of the operating voltage VDD to the level of the operating voltage VSS, but is gradually lowered to the level of the operating voltage VSS with a falling slope. . According to this embodiment, the above-described falling slope is determined by the control voltage V11 generated when the level of the input signal IN is switched from the level of the operating voltage VSS to the level of the operating voltage VDD. When the level of the delay control signal S12 falls to a critical level, the PMOS transistor 22 is turned on, so that the level of the output signal on the node N20 is switched from the level of the operating voltage VSS to the level of the operating voltage VDD.

再次參閱第2與3圖，當輸入信號IN的位準由操作電壓VDD的位準切換為操作電壓VSS的位準時，控制電壓V11等於操作電壓VSS，使得NMOS電晶體111關閉。同時地，當輸入信號IN的位準由操作電壓VDD的位準切換為操作電壓VSS的位準時，控制電壓V10等於操作電壓VSS加上PMOS電晶體20的臨界值V_TH(V10=VSS+V_TH)。由於PMOS電晶體110的閘極上的電壓(即控制電壓V10)大於操作電壓VSS，因此PMOS電晶體110無法完全地導通。如此一來，節點N12上的延遲控制信號S12的位準無法立刻由操作電壓VSS的位準上升至操作電壓VDD的位準，而是以一上升斜率來逐漸地上升至操作電壓VDD的位準。根據此實施例，上述的上升斜率是由當輸入信號IN的位準由操作電壓VDD的位準切換為操作電壓VSS的位準時所產生的控制電壓V10所決定的。當延遲控制信號S12的位準上升至一臨界位準時，NMOS電晶體23導通，使得節點N20上的輸出信號的位準OUT由操作電壓VDD的位準切換為操作電壓VSS的位準。 Referring again to FIGS. 2 and 3, when the level of the input signal IN is switched from the level of the operating voltage VDD to the level of the operating voltage VSS, the control voltage V11 is equal to the operating voltage VSS, so that the NMOS transistor 111 is turned off. Simultaneously, when the level of the input signal IN is switched from the level of the operating voltage VDD to the level of the operating voltage VSS, the control voltage V10 is equal to the operating voltage VSS plus the threshold value V _{TH of the} PMOS transistor 20 (V10=VSS+V _TH ). Since the voltage on the gate of the PMOS transistor 110 (ie, the control voltage V10) is greater than the operating voltage VSS, the PMOS transistor 110 cannot be fully turned on. As a result, the level of the delay control signal S12 on the node N12 cannot immediately rise from the level of the operating voltage VSS to the level of the operating voltage VDD, but gradually rises to the level of the operating voltage VDD with a rising slope. . According to this embodiment, the above-described rising slope is determined by the control voltage V10 generated when the level of the input signal IN is switched from the level of the operating voltage VDD to the level of the operating voltage VSS. When the level of the delay control signal S12 rises to a critical level, the NMOS transistor 23 is turned on, so that the level OUT of the output signal on the node N20 is switched from the level of the operating voltage VDD to the level of the operating voltage VSS.

根據上述可得知，延遲控制信號S12是隨著輸入信號IN的位準切換而逐漸下降與上升，使得輸出信號OUT的上升緣延遲於輸入信號IN的上升緣，且輸出信號OUT的下降緣也延遲於輸入信號IN的下降緣。此外，延遲控制信號S12的下降斜率是取決於控制電壓V11，且其上升斜率是取決於控制電壓V10。因此，輸出信號OUT的上升緣相對於輸入信號IN的上升緣的上升延遲時間DT30(顯示於第3圖)是由控制電壓V11所決定，且輸出信號OUT的下降緣相對於輸入信號IN的下降緣的下降延遲時間DT31(顯示於第3圖)則是由控制電壓V10所決定。與習知的延遲電路比較起來，本案的延遲電路1不須透過增加電容與電阻元件的數量或者藉由增加反向器的數量來達成目標延遲時間。根據本案延遲電路1的操作，僅需改變控制電壓V10與V11的大小來改變延遲控制信號S12的下降斜率與上升斜率，藉此改變輸出信號OUT相對於輸入信號IN的上升延遲時間DT30與下降延遲時間DT31。在一實施例中，上升延遲時間DT30等於下降延遲時間DT31。 As can be seen from the above, the delay control signal S12 gradually decreases and rises as the input signal IN switches, so that the rising edge of the output signal OUT is delayed by the rising edge of the input signal IN, and the falling edge of the output signal OUT is also Delayed by the falling edge of the input signal IN. In addition, the delay of the delay control signal S12 The rate is dependent on the control voltage V11, and its rising slope is dependent on the control voltage V10. Therefore, the rising delay time DT30 (shown in FIG. 3) of the rising edge of the output signal OUT with respect to the rising edge of the input signal IN is determined by the control voltage V11, and the falling edge of the output signal OUT is decreased with respect to the input signal IN. The falling delay time DT31 of the edge (shown in Fig. 3) is determined by the control voltage V10. Compared with the conventional delay circuit, the delay circuit 1 of the present invention does not need to increase the number of capacitors and resistance elements or increase the number of inverters to achieve the target delay time. According to the operation of the delay circuit 1 of the present invention, it is only necessary to change the magnitudes of the control voltages V10 and V11 to change the falling slope and the rising slope of the delay control signal S12, thereby changing the rising delay time DT30 and the falling delay of the output signal OUT with respect to the input signal IN. Time DT31. In an embodiment, the rise delay time DT30 is equal to the fall delay time DT31.

在一實施例中，升壓元件100所耦接操作電壓不同於操作電壓VSS，以及/或降壓元件101所耦接操作電壓不同於操作電壓VDD。參閱第4圖，升壓元件1005中PMOS電晶體20的閘極可耦接操作電壓VSS40，而降壓元件101中NMOS電晶體21的閘極可耦接電壓VDD40。在此實施例中，操作電壓VSS40大於或等於操作電壓VSS，且操作電壓VDD40小於或等於操作電壓VDD。第4圖實施例的延遲電路的操作參照上述關於第2圖實施例的敘述，在此省略說明。 In an embodiment, the boosting element 100 is coupled to the operating voltage different from the operating voltage VSS, and/or the bucking element 101 is coupled to the operating voltage different from the operating voltage VDD. Referring to FIG. 4, the gate of the PMOS transistor 20 in the boosting component 1005 can be coupled to the operating voltage VSS40, and the gate of the NMOS transistor 21 in the bucking component 101 can be coupled to the voltage VDD40. In this embodiment, the operating voltage VSS40 is greater than or equal to the operating voltage VSS, and the operating voltage VDD40 is less than or equal to the operating voltage VDD. The operation of the delay circuit of the embodiment of Fig. 4 is referred to the above description of the embodiment of Fig. 2, and the description thereof is omitted here.

本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。 The present invention has been disclosed in the above preferred embodiments, and is not intended to limit the scope of the present invention. Any one of ordinary skill in the art can make a few changes without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

1‧‧‧延遲電路 1‧‧‧Delay circuit

10‧‧‧電壓產生電路 10‧‧‧Voltage generation circuit

11‧‧‧信號產生電路 11‧‧‧Signal generation circuit

20、22‧‧‧PMOS電晶體 20, 22‧‧‧ PMOS transistor

21、23‧‧‧NMOS電晶體 21, 23‧‧‧ NMOS transistor

100‧‧‧升壓元件 100‧‧‧Boost components

101‧‧‧降壓元件 101‧‧‧Reducing components

110‧‧‧PMOS電晶體 110‧‧‧ PMOS transistor

111‧‧‧NMOS電晶體 111‧‧‧NMOS transistor

112‧‧‧反向器 112‧‧‧ reverser

IN‧‧‧輸入信號 IN‧‧‧ input signal

N10、N11、N12、N20‧‧‧節點 N10, N11, N12, N20‧‧‧ nodes

OUT‧‧‧輸出信號 OUT‧‧‧ output signal

S12‧‧‧延遲控制信號 S12‧‧‧ Delay control signal

V11、V12‧‧‧控制電壓 V11, V12‧‧‧ control voltage

VDD、VSS‧‧‧操作電壓 VDD, VSS‧‧‧ operating voltage

Claims

一種延遲電路，包括：一電壓產生電路，接收一輸入信號，且產生一第一控制電壓以及一第二控制電壓；以及一信號產生電路，受控於該第一控制電壓以及該第二控制電壓，以產生一輸出信號；其中，該第一控制電壓決定該輸出信號的下降緣相對於該輸入信號的下降緣的一第一延遲時間，且該第二控制電壓決定該輸出信號的上升緣相對於該輸入信號的上升緣的一第二延遲時間；其中，該電壓產生電路包括：一升壓元件，接收一第一操作電壓，其中，當該輸入信號具有一第一位準時，該升壓元件於一第一節點上產生大於該第一操作電壓的該第一控制電壓；以及一降壓元件，接收一第二操作電壓，其中，當該輸入信號具有一第二位準時，該降壓元件於一第二節點上產生小於該第二操作電壓的該第二控制電壓；其中，該第一位準低於該第二位準，且該第一操作電壓小於該第二操作電壓。 A delay circuit includes: a voltage generating circuit that receives an input signal and generates a first control voltage and a second control voltage; and a signal generating circuit controlled by the first control voltage and the second control voltage And generating an output signal; wherein the first control voltage determines a first delay time of the falling edge of the output signal relative to a falling edge of the input signal, and the second control voltage determines a rising edge of the output signal relative to a second delay time of the rising edge of the input signal; wherein the voltage generating circuit comprises: a boosting component, receiving a first operating voltage, wherein the boosting when the input signal has a first level The component generates the first control voltage greater than the first operating voltage on a first node; and a buck component receives a second operating voltage, wherein the buck is applied when the input signal has a second level The component generates the second control voltage that is less than the second operating voltage on a second node; wherein the first level is lower than the second level, and the Operating voltage less than the second operating voltage.

如申請專利範圍第1項所述之延遲電路，其中，該升壓元件包括一P型電晶體，其具有耦接該第一操作電壓的閘極、接收該輸入信號的源極、以及耦接該第一節點的汲極；其中，該降壓元件包括一N型電晶體，其具有耦接該第二操作電壓的閘極、接收該輸入信號的汲極、以及耦接該第二節點的源極；其中，該第一控制電壓產生於該第一節點，且該第二控制電壓產生於該第二節點；以及其中，該第一操作電壓小於該第二操作電壓。 The delay circuit of claim 1, wherein the boosting element comprises a P-type transistor having a gate coupled to the first operating voltage, a source receiving the input signal, and a coupling The bungee of the first node; The buck device includes an N-type transistor having a gate coupled to the second operating voltage, a drain receiving the input signal, and a source coupled to the second node; wherein the first A control voltage is generated at the first node, and the second control voltage is generated at the second node; and wherein the first operating voltage is less than the second operating voltage.

如申請專利範圍第2項所述之延遲電路，其中，該P型電晶體與該N型電晶體同時地導通。 The delay circuit of claim 2, wherein the P-type transistor is simultaneously turned on with the N-type transistor.

如申請專利範圍第3項所述之延遲電路，其中，當延遲電路被供電時，該P型電晶體與該N型電晶體都處於常導通的狀態。 The delay circuit of claim 3, wherein the P-type transistor and the N-type transistor are in a normally-on state when the delay circuit is powered.

如申請專利範圍第1項所述之延遲電路，其中，該信號產生電路包括：一P型電晶體，具有接收該第一控制電壓的閘極、耦接一第三操作電壓的源極、以及耦接一第一節點的汲極；以及一N型電晶體，具有接收該第二控制電壓的閘極、耦接該第一節點的汲極、以及耦接一第四操作電壓的源極；其中，該第三操作電壓大於該第四操作電壓；以及其中，一延遲控制信號產生於該第一節點。 The delay circuit of claim 1, wherein the signal generating circuit comprises: a P-type transistor having a gate receiving the first control voltage, a source coupled to a third operating voltage, and An anode coupled to a first node; and an N-type transistor having a gate receiving the second control voltage, a drain coupled to the first node, and a source coupled to a fourth operating voltage; Wherein the third operating voltage is greater than the fourth operating voltage; and wherein a delay control signal is generated at the first node.

如申請專利範圍第5項所述之延遲電路，其中，該延遲控制信號由該第四操作電壓的位準上升時的上升斜率取決於該第一控制電壓；以及其中，該延遲控制信號由該第三操作電壓的位準下降時的下降斜率取決於該第二控制電壓。 The delay circuit of claim 5, wherein a rising slope of the delay control signal when the level of the fourth operating voltage rises is dependent on the first control voltage; and wherein the delay control signal is The falling slope when the level of the third operating voltage drops is dependent on the second control voltage.

如申請專利範圍第5項所述之延遲電路包括一反向器，接收該延遲控制信號，並根據該延遲控制信號來產生該輸出信號。 The delay circuit of claim 5 includes an inverter that receives the delay control signal and generates the output signal based on the delay control signal.

如申請專利範圍第5項所述之延遲電路，其中，該第二操作電壓小於或等於該第三操作電壓。 The delay circuit of claim 5, wherein the second operating voltage is less than or equal to the third operating voltage.

如申請專利範圍第5項所述之延遲電路，其中，該第一操作電壓大於或等於該第四操作電壓。 The delay circuit of claim 5, wherein the first operating voltage is greater than or equal to the fourth operating voltage.

如申請專利範圍第1項所述之延遲電路，其中，該第一延遲時間等於該第二延遲時間。 The delay circuit of claim 1, wherein the first delay time is equal to the second delay time.

一種延遲電路，包括：一第一P型電晶體，具有耦接一第一低操作電壓的閘極、接收一輸入信號的源極、以及耦接一第一節點的汲極；一第一N型電晶體，具有耦接一第一高操作電壓的閘極、接收該輸入信號的汲極、以及耦接一第二節點的源極，其中，該第一高操作電壓大於該第一低操作電壓；一第二P型電晶體，具有耦接該第一節點的閘極、耦接一第二高操作電壓的源極、以及耦接一第三節點的汲極；一第二N型電晶體，具有耦接該第二節點的閘極、耦接該第三節點的汲極、以及耦接一第二低操作電壓的源極，其中，該第二高操作電壓大於該第二低操作電壓；以及一反向器，耦接該第三節點，且產生延遲於該輸入信號的一輸出信號；其中，該第一P型電晶體與該第一N型電晶體同時地導通。 A delay circuit includes: a first P-type transistor having a gate coupled to a first low operating voltage, a source receiving an input signal, and a drain coupled to a first node; a first N a type of transistor having a gate coupled to a first high operating voltage, a drain receiving the input signal, and a source coupled to a second node, wherein the first high operating voltage is greater than the first low operation a second P-type transistor having a gate coupled to the first node, a source coupled to a second high operating voltage, and a drain coupled to a third node; a second N-type a crystal having a gate coupled to the second node, a drain coupled to the third node, and a source coupled to a second low operating voltage, wherein the second high operating voltage is greater than the second low operating And an inverter coupled to the third node and generating an output signal delayed by the input signal; wherein the first P-type transistor is simultaneously turned on with the first N-type transistor.

如申請專利範圍第11項所述之延遲電路，其中，當延遲電路 1被供電時，該第一P型電晶體與該第一N型電晶體都處於常導通的狀態。 The delay circuit of claim 11, wherein the delay circuit When the power is supplied, the first P-type transistor and the first N-type transistor are in a normally-on state.

如申請專利範圍第11項所述之延遲電路，其中，該第一節點上的電壓決定該輸出信號的下降緣相對於該輸入信號的下降緣的一第一延遲時間，且該第二節點上的電壓決定該輸出信號的上升緣相對於該輸入信號的上升緣的一第二延遲時間。 The delay circuit of claim 11, wherein the voltage on the first node determines a first delay time of a falling edge of the output signal relative to a falling edge of the input signal, and the second node is The voltage determines a second delay time of the rising edge of the output signal relative to the rising edge of the input signal.

如申請專利範圍第13項所述之延遲電路，其中，該第一延遲時間等於該第二延遲時間。 The delay circuit of claim 13, wherein the first delay time is equal to the second delay time.

如申請專利範圍第11項所述之延遲電路，其中，該第一低操作電壓大於或等於該第二低操作電壓。 The delay circuit of claim 11, wherein the first low operating voltage is greater than or equal to the second low operating voltage.

如申請專利範圍第11項所述之延遲電路，其中，該第一高操作電壓小於或等於該第二高操作電壓。 The delay circuit of claim 11, wherein the first high operating voltage is less than or equal to the second high operating voltage.

如申請專利範圍第11項所述之延遲電路，其中，該反向器包括：一第三P型電晶體，具有耦接該第三節點的閘極、耦接該第二高操作電壓的源極、以及耦接一第四節點的汲極；以及一第三N型電晶體，具有耦接該第三節點的閘極、耦接該第四節點的汲極、以及耦接該第二低操作電壓的源極；其中，該輸出信號產生於該第四節點。 The delay circuit of claim 11, wherein the inverter comprises: a third P-type transistor having a gate coupled to the third node and a source coupled to the second high operating voltage a pole and a drain connected to a fourth node; and a third N-type transistor having a gate coupled to the third node, a drain coupled to the fourth node, and a second low coupled a source of operating voltage; wherein the output signal is generated at the fourth node.