TWI732558B - Delay-locked loop device and operation method thereof - Google Patents

Delay-locked loop device and operation method thereof Download PDF

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TWI732558B
TWI732558B TW109116414A TW109116414A TWI732558B TW I732558 B TWI732558 B TW I732558B TW 109116414 A TW109116414 A TW 109116414A TW 109116414 A TW109116414 A TW 109116414A TW I732558 B TWI732558 B TW I732558B
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delay
clock
time
loop device
time point
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TW202144948A (en
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奥野晋也
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華邦電子股份有限公司
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Abstract

A delay-locked loop (DLL) device and an operation method for the DLL device are provided. The DLL device includes a delay line, a replica circuit, a phase detector, and a delay controller. The delay line to delays the input clock to provide a delayed clock in response to a delay code. The replica circuit generates a feedback clock based on the delayed clock. The phase detector compares the input clock and the feedback clock to generate a delay control signal. The delay controller generates a delay code at a first time point according to the delay control signal based on a control clock, and delays a replica delay time length to provide the delayed code to the delay line at a second time point. The delay line adjusts the input clock at the second time point. The period of the control clock is adjusted to be larger than the replica delay time length.

Description

延遲鎖相迴路裝置及其操作方法Delay lock loop device and its operation method

本發明是有關於一種延遲鎖相迴路裝置以及延遲鎖相迴路裝置的操作方法，且特別是有關於一種可適用於任意輸入時脈的週期的延遲鎖相迴路裝置以及延遲鎖相迴路裝置的操作方法。The present invention relates to a delay lock loop device and an operation method of the delay lock loop device, and more particularly to a delay lock loop device applicable to the period of any input clock and the operation of the delay lock loop device method.

一般來說，延遲鎖相迴路（delay-locked loop，DLL）會被設定在一預設週期內將所接收的輸入時脈調整為所期望的延遲時脈。然而，在輸入時脈具有較小的週期的情況下，DLL會頻繁地發生過度偏移（over shift），進而使延遲時脈發生延遲不足或延遲過多的情況。在輸入時脈具有較大的週期的情況下，DLL可改善過度偏移，但會使DLL無法在預設週期內將所接收的輸入時脈調整為所期望的延遲時脈。Generally speaking, a delay-locked loop (DLL) is set to adjust the received input clock to a desired delay clock within a preset period. However, when the input clock has a small period, the DLL will frequently over shift (over shift), which in turn causes insufficient or excessive delay of the delayed clock. In the case that the input clock has a relatively large period, the DLL can improve the excessive offset, but it will prevent the DLL from adjusting the received input clock to the expected delay clock within the preset period.

因此，設計出適用於任意輸入時脈的週期的延遲鎖相迴路裝置是本領域技術人員努力研究的課題之一。Therefore, designing a delay lock loop device suitable for the period of any input clock is one of the subjects that those skilled in the art are working hard to study.

本發明提供一種可適用於任意輸入時脈的週期的延遲鎖相迴路裝置以及延遲鎖相迴路裝置的操作方法。The invention provides a delay lock loop device applicable to the period of any input clock and an operation method of the delay lock loop device.

本發明的延遲鎖相迴路裝置包括延遲線、複本電路、相位檢測器以及延遲控制器。延遲線經配置以接收輸入時脈，並反應於多位元的延遲碼對輸入時脈進行延遲，藉以提供延遲時脈。複本電路耦接於延遲線。複本電路經配置以接收延遲時脈，並依據延遲時脈產生回饋時脈。相位檢測器耦接於複本電路。相位檢測器經配置以接收輸入時脈以及回饋時脈，並比較輸入時脈以及回饋時脈以產生延遲控制訊號。延遲控制器耦接於相位檢測器以及延遲線。延遲控制器經配置以基於控制時脈依據延遲控制訊號在第一時間點產生延遲碼，延遲複本延遲時間長度以在第二時間點將延遲碼提供到延遲線，並使延遲線在第二時間點對輸入時脈的時序進行調整。控制時脈的週期被調整為大於複本延遲時間長度。The delay lock loop device of the present invention includes a delay line, a replica circuit, a phase detector and a delay controller. The delay line is configured to receive the input clock, and respond to the multi-bit delay code to delay the input clock, thereby providing a delayed clock. The replica circuit is coupled to the delay line. The replica circuit is configured to receive the delayed clock and generate a feedback clock based on the delayed clock. The phase detector is coupled to the replica circuit. The phase detector is configured to receive the input clock and the feedback clock, and compare the input clock and the feedback clock to generate a delay control signal. The delay controller is coupled to the phase detector and the delay line. The delay controller is configured to generate a delay code at the first time point according to the delay control signal based on the control clock, delay the copy delay time length to provide the delay code to the delay line at the second time point, and make the delay line at the second time point Adjust the timing of the input clock. The period of the control clock is adjusted to be greater than the length of the copy delay time.

本發明的操作方法適用於延遲鎖相迴路裝置。操作方法包括：接收輸入時脈，並反應於多位元的延遲碼對輸入時脈進行延遲，藉以提供延遲時脈；依據延遲時脈產生回饋時脈；比較輸入時脈以及回饋時脈以產生延遲控制訊號；以及基於控制時脈依據延遲控制訊號在第一時間點產生延遲碼，延遲複本延遲時間長度以在第二時間點提供延遲碼，並在第二時間點對輸入時脈的時序進行調整，其中控制時脈的週期被調整為大於複本延遲時間長度。The operation method of the present invention is suitable for a delay phase locked loop device. The operation method includes: receiving the input clock and delaying the input clock in response to a multi-bit delay code to provide a delayed clock; generating a feedback clock based on the delayed clock; comparing the input clock and the feedback clock to generate Delay the control signal; and generate a delay code at the first time point according to the delay control signal based on the control clock, delay the copy delay time to provide the delay code at the second time point, and perform the timing of the input clock at the second time point Adjustment, where the period of the control clock is adjusted to be greater than the length of the copy delay time.

基於上述，控制時脈的週期被調整為大於複本延遲時間長度，延遲鎖相迴路裝置以及操作方法能夠基於控制時脈提供延遲碼，使得延遲碼在複本延遲時間長度後對輸入時脈的相位進行調整。如此一來，本發明的延遲鎖相迴路裝置以及操作方法能夠適用於任意輸入時脈的週期。Based on the above, the period of the control clock is adjusted to be greater than the length of the copy delay time, the delay lock loop device and the operation method can provide a delay code based on the control clock, so that the delay code performs the phase of the input clock after the copy delay time. Adjustment. In this way, the delay lock loop device and operation method of the present invention can be applied to any input clock cycle.

為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

本發明的部份實施例接下來將會配合附圖來詳細描述，以下的描述所引用的元件符號，當不同附圖出現相同的元件符號將視為相同或相似的元件。這些實施例只是本發明的一部份，並未揭示所有本發明的可實施方式。更確切的說，這些實施例只是本發明的專利申請範圍中的裝置的範例。Part of the embodiments of the present invention will be described in detail in conjunction with the accompanying drawings. The reference symbols in the following description will be regarded as the same or similar elements when the same symbol appears in different drawings. These embodiments are only a part of the present invention, and do not disclose all the possible implementation modes of the present invention. More precisely, these embodiments are only examples of devices within the scope of the patent application of the present invention.

請參考圖1，圖1是依據本發明第一實施例所繪示的延遲鎖相迴路裝置的裝置示意圖。延遲鎖相迴路裝置100包括延遲線110、複本（replica）電路120、相位檢測器130以及延遲控制器140。延遲線110接收輸入時脈I_CLK，並反應於多位元的延遲碼DCD對輸入時脈I_CLK進行延遲，藉以提供延遲時脈D_CLK。複本電路120耦接於延遲線110。複本電路120接收來自於延遲線110的延遲時脈D_CLK，並依據延遲時脈D_CLK產生回饋時脈FB_CLK。相位檢測器130耦接於複本電路120。相位檢測器130接收輸入時脈I_CLK以及回饋時脈FB_CLK，並比較輸入時脈I_CLK以及回饋時脈FB_CLK以產生延遲控制訊號DCS。Please refer to FIG. 1, which is a schematic diagram of the delay lock loop device according to the first embodiment of the present invention. The delay lock loop device 100 includes a delay line 110, a replica circuit 120, a phase detector 130 and a delay controller 140. The delay line 110 receives the input clock I_CLK, and responds to the multi-bit delay code DCD to delay the input clock I_CLK to provide the delayed clock D_CLK. The replica circuit 120 is coupled to the delay line 110. The replica circuit 120 receives the delayed clock D_CLK from the delay line 110, and generates a feedback clock FB_CLK according to the delayed clock D_CLK. The phase detector 130 is coupled to the replica circuit 120. The phase detector 130 receives the input clock I_CLK and the feedback clock FB_CLK, and compares the input clock I_CLK and the feedback clock FB_CLK to generate a delay control signal DCS.

延遲控制器140耦接於相位檢測器130以及延遲線110。延遲控制器140基於控制時脈CTRL_CLK依據延遲控制訊號DCS在第一時間點產生延遲碼DCD。在本實施例中，延遲控制訊號DCS包括延遲指令UP、DN。延遲控制器140會依據延遲指令UP提高延遲碼DCD的數值。延遲線110會依據數值被提高的延遲碼DCD增加輸入時脈I_CLK的延遲。在另一方面，延遲控制器140會依據延遲指令DN降低延遲碼DCD的數值。延遲線110會依據數值被降低的延遲碼DCD減少輸入時脈I_CLK的延遲。延遲控制器140在第一時間點產生延遲碼DCD時，會延遲複本延遲時間長度RDT以在第二時間點將延遲碼DCD提供到延遲線110。因此，延遲線110會在第二時間點對輸入時脈I_CLK的時序進行調整。在本實施例中，控制時脈CTRL_CLK的週期被調整為大於複本延遲時間長度RDT並小於複本延遲時間長度RDT加總輸入時脈I_CLK的週期的時間長度。接下來，在第二時間點之後，延遲控制器140會基於控制時脈CTRL_CLK以提供另一延遲碼DCD。The delay controller 140 is coupled to the phase detector 130 and the delay line 110. The delay controller 140 generates a delay code DCD at the first time point based on the control clock CTRL_CLK according to the delay control signal DCS. In this embodiment, the delay control signal DCS includes delay commands UP and DN. The delay controller 140 increases the value of the delay code DCD according to the delay command UP. The delay line 110 increases the delay of the input clock I_CLK according to the delay code DCD whose value is increased. On the other hand, the delay controller 140 reduces the value of the delay code DCD according to the delay command DN. The delay line 110 reduces the delay of the input clock I_CLK according to the reduced delay code DCD. When the delay controller 140 generates the delay code DCD at the first time point, it delays the replica delay time length RDT to provide the delay code DCD to the delay line 110 at the second time point. Therefore, the delay line 110 adjusts the timing of the input clock I_CLK at the second time point. In this embodiment, the period of the control clock CTRL_CLK is adjusted to be greater than the replica delay time length RDT and less than the replica delay time length RDT plus the period of the input clock I_CLK. Next, after the second time point, the delay controller 140 will provide another delay code DCD based on the control clock CTRL_CLK.

值得一提的是，控制時脈CTRL_CLK的週期被調整為大於複本延遲時間長度RDT。也就是說，延遲鎖相迴路裝置100是追隨複本延遲時間長度RDT以調整控制時脈CTRL_CLK的週期，並且控制時脈CTRL_CLK的週期會略大於複本延遲時間長度RDT。延遲控制器140能夠在回饋時脈FB_CLK被提供之後隨即（即，在至少一個輸入時脈I_CLK週期的時間區間內）產生另一延遲碼DCD。舉例來說，控制時脈CTRL_CLK的週期被調整為大於複本延遲時間長度RDT並小於複本延遲時間長度RDT加總單一個輸入時脈I_CLK週期的時間長度。另舉例來說，控制時脈CTRL_CLK的週期被調整為大於複本延遲時間長度RDT並小於複本延遲時間長度RDT加總2個輸入時脈I_CLK週期的時間長度。因此，延遲控制器140能夠在回饋時脈FB_CLK被提供之後（即，在1個或2個輸入時脈I_CLK週期的時間區間內）隨即產生另一延遲碼DCD。因此在輸入時脈I_CLK具有較小的週期的情況下，延遲鎖相迴路裝置100並不會有過度偏移（over shift）的狀況。此外，在輸入時脈I_CLK具有較大的週期的情況下，延遲鎖相迴路裝置100是依據複本延遲時間長度RDT調整控制時脈CTRL_CLK的週期。因此，延遲鎖相迴路裝置100輸入時脈I_CLK調整為所期望的延遲時脈D_CLK的時間長度並不會被延長。如此一來，延遲鎖相迴路裝置100能夠適用於任意輸入時脈I_CLK的週期，並且能夠在所規定的預設週期內將所接收的輸入時脈I_CLK調整為所期望的延遲時脈D_CLK。It is worth mentioning that the period of the control clock CTRL_CLK is adjusted to be longer than the copy delay time RDT. In other words, the delay lock loop device 100 follows the replica delay time length RDT to adjust the period of the control clock CTRL_CLK, and the period of the control clock CTRL_CLK is slightly larger than the replica delay time length RDT. The delay controller 140 can generate another delay code DCD immediately after the feedback clock FB_CLK is provided (that is, within a time interval of at least one input clock I_CLK cycle). For example, the period of the control clock CTRL_CLK is adjusted to be greater than the replica delay time length RDT and less than the replica delay time length RDT plus the time length of a single input clock I_CLK cycle. For another example, the period of the control clock CTRL_CLK is adjusted to be greater than the replica delay time length RDT and less than the replica delay time length RDT plus the time length of the two input clock I_CLK cycles. Therefore, the delay controller 140 can generate another delay code DCD immediately after the feedback clock FB_CLK is provided (that is, within the time interval of one or two input clock I_CLK cycles). Therefore, when the input clock I_CLK has a relatively small period, the delay lock loop device 100 does not have an over shift condition. In addition, when the input clock I_CLK has a relatively large period, the delay lock loop device 100 adjusts the period of the control clock CTRL_CLK according to the replica delay time RDT. Therefore, the length of time for adjusting the input clock I_CLK of the delay lock loop device 100 to the expected delay clock D_CLK will not be extended. In this way, the delay lock loop device 100 can be applied to any period of the input clock I_CLK, and can adjust the received input clock I_CLK to the desired delayed clock D_CLK within the specified preset period.

舉例來說，請同時參考圖1及圖2A，圖2A是依據本發明一實施例應用於具有最小週期的輸入時脈的訊號時序圖。本實施例的訊號時序圖適用於延遲鎖相迴路裝置100。延遲控制器140會依據延遲指令UP提高延遲碼DCD的數值以增加輸入時脈I_CLK的延遲。在另一方面，延遲控制器140會依據延遲指令DN降低延遲碼DCD的數值以減少輸入時脈I_CLK的延遲。在本實施例中，延遲控制器140基於控制時脈CTRL_CLK依據延遲控制訊號DCS在第一時間點t1產生延遲碼DCD。在本實施例中，延遲控制器140會基於控制時脈CTRL_CLK的上升緣（rising edge）產生關連於延遲控制訊號DCS的延遲碼DCD。在一些實施例中，延遲控制器140會基於控制時脈CTRL_CLK的下降緣（falling edge）產生關連於延遲控制訊號DCS的延遲碼DCD。延遲線110會在第二時間點t2對輸入時脈I_CLK的時序進行調整。第二時間點t2相對於第一時間點t1具有複本延遲時間長度RDT的延遲。在本實施例中，控制時脈CTRL_CLK的週期被調整為大於複本延遲時間長度RDT。因此，延遲控制器140會基於控制時脈CTRL_CLK在第二時間點t2以後的第三時間點t3產生另一延遲碼DCD。第三時間點t3與第一時間點t1之間的時間長度實質上等於控制時脈CTRL_CLK的週期。For example, please refer to FIG. 1 and FIG. 2A at the same time. FIG. 2A is a signal timing diagram applied to an input clock with a minimum period according to an embodiment of the present invention. The signal timing diagram of this embodiment is applicable to the delay lock loop device 100. The delay controller 140 increases the value of the delay code DCD according to the delay command UP to increase the delay of the input clock I_CLK. On the other hand, the delay controller 140 reduces the value of the delay code DCD according to the delay command DN to reduce the delay of the input clock I_CLK. In this embodiment, the delay controller 140 generates the delay code DCD at the first time point t1 based on the control clock CTRL_CLK according to the delay control signal DCS. In this embodiment, the delay controller 140 generates the delay code DCD related to the delay control signal DCS based on the rising edge of the control clock CTRL_CLK. In some embodiments, the delay controller 140 generates a delay code DCD related to the delay control signal DCS based on the falling edge of the control clock CTRL_CLK. The delay line 110 adjusts the timing of the input clock I_CLK at the second time point t2. The second time point t2 has a delay of the replica delay time length RDT relative to the first time point t1. In this embodiment, the period of the control clock CTRL_CLK is adjusted to be greater than the replica delay time length RDT. Therefore, the delay controller 140 generates another delay code DCD based on the control clock CTRL_CLK at a third time point t3 after the second time point t2. The length of time between the third time point t3 and the first time point t1 is substantially equal to the period of the control clock CTRL_CLK.

在本實施例中，控制時脈CTRL_CLK的週期是取決於複本延遲時間長度RDT。因此，延遲控制器140能夠在回饋時脈FB_CLK被提供之後在單一個輸入時脈I_CLK的週期或單一個回饋時脈FB_CLK的週期（輸入時脈I_CLK的週期實質上等於回饋時脈FB_CLK的週期）的時間區間內產生另一延遲碼DCD。因此，因此在輸入時脈I_CLK具有最小的週期的情況下，延遲鎖相迴路裝置100並不會有過度偏移的狀況。In this embodiment, the period of the control clock CTRL_CLK depends on the copy delay time RDT. Therefore, the delay controller 140 can perform a single input clock I_CLK cycle or a single feedback clock FB_CLK cycle after the feedback clock FB_CLK is provided (the cycle of the input clock I_CLK is substantially equal to the cycle of the feedback clock FB_CLK) Another delay code DCD is generated within the time interval. Therefore, when the input clock I_CLK has the smallest period, the delay lock loop device 100 will not experience excessive deviation.

舉例來說，請同時參考圖1、圖2A及圖2B，圖2B是依據本發明一實施例應用於具有最大週期的輸入時脈的訊號時序圖。圖2B的訊號時序圖也適用於延遲鎖相迴路裝置100。在本實施例中，圖2A的複本延遲時間長度RDT相同於圖2B的複本延遲時間長度RDT。因此在本實施例中，圖2B的控制時脈CTRL_CLK的週期可以是等於圖2A所示的控制時脈CTRL_CLK的週期。亦即，因此在輸入時脈I_CLK具有最大的週期的情況下，延遲鎖相迴路裝置100是依據複本延遲時間長度RDT調整控制時脈CTRL_CLK的週期。因此，延遲鎖相迴路裝置100輸入時脈I_CLK調整為所期望的延遲時脈D_CLK的時間長度並不會被延長。For example, please refer to FIG. 1, FIG. 2A and FIG. 2B at the same time. FIG. 2B is a signal timing diagram applied to an input clock with a maximum period according to an embodiment of the present invention. The signal timing diagram of FIG. 2B is also applicable to the delay lock loop device 100. In this embodiment, the replica delay time length RDT of FIG. 2A is the same as the replica delay time length RDT of FIG. 2B. Therefore, in this embodiment, the period of the control clock CTRL_CLK in FIG. 2B may be equal to the period of the control clock CTRL_CLK shown in FIG. 2A. That is, when the input clock I_CLK has the largest period, the delay lock loop device 100 adjusts the period of the control clock CTRL_CLK according to the replica delay time RDT. Therefore, the length of time for adjusting the input clock I_CLK of the delay lock loop device 100 to the expected delay clock D_CLK will not be extended.

請同時參考圖1、圖3A以及圖3B，圖3A是依據本發明一實施例應用於慢偏斜的訊號時序圖。圖3B是依據本發明一實施例應用於快偏斜的訊號時序圖。圖3A的訊號時序圖以及圖3B的訊號時序圖也適用於延遲鎖相迴路裝置100。在本實施例中，複本延遲時間長度RDT會依據延遲鎖相迴路裝置100的製程所產生的電晶體偏斜（skew）被調整。電晶體偏斜取決於電晶體中的臨界電壓值。舉例來說，基於延遲鎖相迴路裝置100的製程，當延遲鎖相迴路裝置100的電晶體具有較大的臨界電壓值時，這意謂著延遲鎖相迴路裝置100具有慢偏斜（slow skew）的狀況，這會使得延遲鎖相迴路裝置100具有較大的延遲。複本延遲時間長度RDT隨慢偏斜被增加，如圖3A所示。由於複本延遲時間長度RDT隨慢偏斜被增加，控制時脈CTRL_CLK的週期也會被增加。Please refer to FIG. 1, FIG. 3A and FIG. 3B at the same time. FIG. 3A is a signal timing diagram applied to slow skew according to an embodiment of the present invention. FIG. 3B is a signal timing diagram applied to fast skew according to an embodiment of the present invention. The signal timing diagram of FIG. 3A and the signal timing diagram of FIG. 3B are also applicable to the delay lock loop device 100. In this embodiment, the length of the replica delay time RDT is adjusted according to the skew of the transistor generated by the manufacturing process of the delay lock loop device 100. Transistor deflection depends on the critical voltage value in the transistor. For example, based on the manufacturing process of the delay lock loop device 100, when the transistor of the delay lock loop device 100 has a larger threshold voltage value, this means that the delay lock loop device 100 has a slow skew. ), which will cause the delay lock loop device 100 to have a larger delay. The length of the replica delay time RDT is increased with the slow skew, as shown in Figure 3A. Since the copy delay time length RDT is increased with the slow skew, the period of the control clock CTRL_CLK will also be increased.

另舉例來說，當延遲鎖相迴路裝置100的電晶體具有較小的臨界電壓值時，這意謂著延遲鎖相迴路裝置100具有快偏斜（fast skew）的狀況，這會使得延遲鎖相迴路裝置100具有較小的延遲。複本延遲時間長度RDT隨快偏斜被降低，如圖3B所示。由於複本延遲時間長度RDT隨快偏斜被降低，控制時脈CTRL_CLK的週期也會被降低。For another example, when the transistor of the delay lock loop device 100 has a small threshold voltage value, this means that the delay lock loop device 100 has a fast skew condition, which will cause the delay lock The loop device 100 has a small delay. The copy delay time length RDT is reduced with the fast skew, as shown in Fig. 3B. Since the copy delay time length RDT is reduced with the fast skew, the period of the control clock CTRL_CLK will also be reduced.

請參考圖4，圖4是依據本發明第二實施例所繪示的延遲鎖相迴路裝置的裝置示意圖。與第一實施例不同的是，延遲鎖相迴路裝置200還包括振盪器150。在本實施例中，振盪器150耦接於延遲控制器140。振盪器150提供控制時脈CTRL_CLK。在本實施例中，振盪器150會接收致能訊號ES。振盪器150依據致能訊號ES而被致能，進而提供控制時脈CTRL_CLK。Please refer to FIG. 4, which is a schematic diagram of a delay lock loop device according to a second embodiment of the present invention. The difference from the first embodiment is that the delay lock loop device 200 further includes an oscillator 150. In this embodiment, the oscillator 150 is coupled to the delay controller 140. The oscillator 150 provides the control clock CTRL_CLK. In this embodiment, the oscillator 150 receives the enable signal ES. The oscillator 150 is enabled according to the enable signal ES, and then provides a control clock CTRL_CLK.

請參考圖5，圖5是依據本發明第三實施例所繪示的延遲鎖相迴路裝置的裝置示意圖。與第二實施例不同的是，延遲鎖相迴路裝置300還包括致能訊號產生器160。在本實施例中，致能訊號產生器160耦接於振盪器150。致能訊號產生器160提供致能訊號ES。在本實施例中，致能訊號產生器160還會耦接至延遲線110、複本電路120、相位檢測器130以及延遲控制器140。致能訊號產生器160也會藉由致能訊號ES來致能延遲線110、複本電路120、相位檢測器130以及延遲控制器140。Please refer to FIG. 5. FIG. 5 is a schematic diagram of a delay lock loop device according to a third embodiment of the present invention. The difference from the second embodiment is that the delay lock loop device 300 further includes an enabling signal generator 160. In this embodiment, the enabling signal generator 160 is coupled to the oscillator 150. The enabling signal generator 160 provides the enabling signal ES. In this embodiment, the enabling signal generator 160 is also coupled to the delay line 110, the replica circuit 120, the phase detector 130, and the delay controller 140. The enabling signal generator 160 also enables the delay line 110, the replica circuit 120, the phase detector 130, and the delay controller 140 by the enabling signal ES.

請同時參考圖1以及圖6，圖6是依據本發明一實施例所繪示的操作方法流程圖。在步驟S110中，延遲線110會接收輸入時脈I_CLK，並反應於多位元的延遲碼DCD對輸入時脈I_CLK進行延遲，藉以提供延遲時脈D_CLK。在步驟S120中，複本電路120會依據延遲時脈D_CLK產生回饋時脈FB_CLK。在步驟S130中，相位檢測器130會比較輸入時脈I_CLK以及回饋時脈FB_CLK以產生延遲控制訊號DCS。在步驟S140中，基於控制時脈，延遲控制器140會依據延遲控制訊號DCS在第一時間點產生延遲碼DCD，延遲複本延遲時間長度以在第二時間點提供延遲碼DCD。並且延遲線110在第二時間點對輸入時脈I_CLK的時序進行調整。本實施例的步驟S110~S140的實施細節能夠至少在圖1至圖3B的多個實施例中獲致足夠的教示，因此恕不在此重述。Please refer to FIG. 1 and FIG. 6 at the same time. FIG. 6 is a flowchart of an operation method according to an embodiment of the present invention. In step S110, the delay line 110 receives the input clock I_CLK, and responds to the multi-bit delay code DCD to delay the input clock I_CLK to provide the delayed clock D_CLK. In step S120, the replica circuit 120 generates a feedback clock FB_CLK according to the delayed clock D_CLK. In step S130, the phase detector 130 compares the input clock I_CLK and the feedback clock FB_CLK to generate the delay control signal DCS. In step S140, based on the control clock, the delay controller 140 generates the delay code DCD at the first time point according to the delay control signal DCS, and delays the copy delay time to provide the delay code DCD at the second time point. And the delay line 110 adjusts the timing of the input clock I_CLK at the second time point. The implementation details of the steps S110 to S140 in this embodiment can be sufficiently taught in at least the multiple embodiments in FIG. 1 to FIG. 3B, and therefore, it will not be repeated here.

綜上所述，本發明控制時脈的週期被調整為大於複本延遲時間長度，延遲鎖相迴路裝置以及操作方法能夠基於控制時脈提供延遲碼，使得延遲碼在複本延遲時間長度後對輸入時脈的相位進行調整。如此一來，本發明的延遲鎖相迴路裝置以及操作方法能夠適用於任意輸入時脈的週期，並且能夠在所規定的預設週期內將所接收的輸入時脈調整為所期望的延遲時脈。In summary, the period of the control clock of the present invention is adjusted to be greater than the length of the copy delay time. The delay lock loop device and the operation method can provide a delay code based on the control clock, so that the delay code will affect the input time after the copy delay time. The phase of the pulse is adjusted. In this way, the delay lock loop device and operation method of the present invention can be applied to any input clock cycle, and the received input clock can be adjusted to a desired delay clock within a prescribed preset cycle .

雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the relevant technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The protection scope of the present invention shall be subject to those defined by the attached patent application scope.

100、200、300:延遲鎖相迴路裝置 110:延遲線 120:複本電路 130:相位檢測器 140:延遲控制器 150:振盪器 160:致能訊號產生器 D_CLK:延遲時脈 DCD:延遲碼 DCS:延遲控制訊號 DN、UP:延遲指令 ES:致能訊號 FB_CLK:回饋時脈 I_CLK:輸入時脈 RDT:複本延遲時間長度 S110~S140:步驟 t1:第一時間點 t2:第二時間點 t3:第三時間點 100, 200, 300: Delay lock loop device 110: Delay line 120: Replica circuit 130: Phase detector 140: Delay controller 150: Oscillator 160: Enabling signal generator D_CLK: Delayed clock DCD: Delay code DCS: Delay control signal DN, UP: Delay command ES: Enabling signal FB_CLK: feedback clock I_CLK: Input clock RDT: Replica delay time length S110~S140: steps t1: the first point in time t2: second time point t3: third time point

圖1是依據本發明第一實施例所繪示的延遲鎖相迴路裝置的裝置示意圖。 圖2A是依據本發明一實施例應用於具有最小週期的輸入時脈的訊號時序圖；圖2B是依據本發明一實施例應用於具有最大週期的輸入時脈的訊號時序圖。 圖3A是依據本發明一實施例應用於慢偏斜的訊號時序圖；圖3B是依據本發明一實施例應用於快偏斜的訊號時序圖。 圖4是依據本發明第二實施例所繪示的延遲鎖相迴路裝置的裝置示意圖。 圖5是依據本發明第三實施例所繪示的延遲鎖相迴路裝置的裝置示意圖。 圖6是依據本發明一實施例所繪示的操作方法流程圖。 FIG. 1 is a schematic diagram of the delay lock loop device according to the first embodiment of the present invention. 2A is a signal timing diagram applied to an input clock with a minimum period according to an embodiment of the present invention; FIG. 2B is a signal timing diagram applied to an input clock with a maximum period according to an embodiment of the present invention. 3A is a timing diagram of a signal applied to slow skew according to an embodiment of the present invention; FIG. 3B is a timing diagram of a signal applied to fast skew according to an embodiment of the present invention. FIG. 4 is a schematic diagram of the delay lock loop device according to the second embodiment of the present invention. FIG. 5 is a schematic diagram of the delay lock loop device according to the third embodiment of the present invention. Fig. 6 is a flowchart of an operation method according to an embodiment of the present invention.

100:延遲鎖相迴路裝置 100: Delay lock loop device

110:延遲線 110: Delay line

120:複本電路 120: Replica circuit

130:相位檢測器 130: Phase detector

140:延遲控制器 140: Delay controller

D_CLK:延遲時脈 D_CLK: Delayed clock

DCD:延遲碼 DCD: Delay code

DCS:延遲控制訊號 DCS: Delay control signal

FB_CLK:回饋時脈 FB_CLK: feedback clock

I_CLK:輸入時脈 I_CLK: Input clock

RDT:複本延遲時間長度 RDT: Replica delay time length

UP、DN:延遲指令 UP, DN: Delay command

Claims (13)

一種延遲鎖相迴路裝置，包括：一延遲線，經配置以接收一輸入時脈，並反應於多位元的一延遲碼對該輸入時脈進行延遲，藉以提供一延遲時脈；一複本電路，耦接於該延遲線，經配置以接收該延遲時脈，並依據該延遲時脈產生一回饋時脈；一相位檢測器，耦接於該複本電路，經配置以接收該輸入時脈以及該回饋時脈，並比較該輸入時脈以及該回饋時脈以產生一延遲控制訊號；以及一延遲控制器，耦接於該相位檢測器以及該延遲線，經配置以基於一控制時脈依據該延遲控制訊號在一第一時間點產生該延遲碼，延遲一複本延遲時間長度以在一第二時間點將該延遲碼提供到該延遲線，並使該延遲線在該第二時間點對該輸入時脈的時序進行調整，其中該複本延遲時間長度依據該延遲鎖相迴路裝置的製程所產生的一電晶體偏斜被調整，並且該控制時脈的週期被調整為大於該複本延遲時間長度。 A delay lock loop device includes: a delay line configured to receive an input clock, and a delay code that responds to multiple bits to delay the input clock, so as to provide a delay clock; a replica circuit , Coupled to the delay line, configured to receive the delayed clock, and generate a feedback clock according to the delayed clock; a phase detector, coupled to the replica circuit, configured to receive the input clock and The feedback clock, and compare the input clock and the feedback clock to generate a delay control signal; and a delay controller, coupled to the phase detector and the delay line, configured to be based on a control clock basis The delay control signal generates the delay code at a first time point, delays a duplicate delay time length to provide the delay code to the delay line at a second time point, and causes the delay line to respond to the delay code at the second time point. The timing of the input clock is adjusted, wherein the length of the replica delay time is adjusted according to a transistor skew generated by the process of the delay lock loop device, and the period of the control clock is adjusted to be greater than the length of the replica delay time . 如請求項1所述的延遲鎖相迴路裝置，其中基於該控制時脈，該延遲控制器在該第二時間點之後的一第三時間點提供另一延遲碼，其中該第三時間點與該第一時間點之間的時間長度實質上等於該控制時脈的週期。 The delay lock loop device according to claim 1, wherein based on the control clock, the delay controller provides another delay code at a third time point after the second time point, wherein the third time point and The length of time between the first time points is substantially equal to the period of the control clock. 如請求項1所述的延遲鎖相迴路裝置，其中該電晶體偏斜取決於電晶體中的臨界電壓值。 The delay lock loop device according to claim 1, wherein the deflection of the transistor depends on the threshold voltage value in the transistor. 如請求項3所述的延遲鎖相迴路裝置，其中該複本延遲時間長度依據該電晶體偏斜中的慢偏斜被增加，其中該複本延遲時間長度依據該電晶體偏斜中的快偏斜被降低。 The delay lock loop device according to claim 3, wherein the length of the replica delay time is increased according to the slow skew in the transistor skew, and wherein the length of the replica delay time depends on the fast skew in the transistor skew Was lowered. 如請求項1所述的延遲鎖相迴路裝置，還包括：一振盪器，耦接於該延遲控制器，經配置以提供該控制時脈。 The delay lock loop device according to claim 1, further comprising: an oscillator coupled to the delay controller and configured to provide the control clock. 如請求項5所述的延遲鎖相迴路裝置，其中該振盪器依據一致能訊號而被致能，藉以提供該控制時脈。 The delay lock loop device according to claim 5, wherein the oscillator is enabled according to an enable signal to provide the control clock. 如請求項6所述的延遲鎖相迴路裝置，還包括：一致能訊號產生器，耦接於該振盪器，經配置以提供該致能訊號。 The delay phase locked loop device according to claim 6, further comprising: an enabling signal generator, coupled to the oscillator, and configured to provide the enabling signal. 如請求項7所述的延遲鎖相迴路裝置，其中該致能訊號產生器還耦接至該延遲線、該複本電路、該相位檢測器以及該延遲控制器，並藉由該致能訊號致能該延遲線、該複本電路、該相位檢測器以及該延遲控制器。 The delay lock loop device according to claim 7, wherein the enabling signal generator is further coupled to the delay line, the replica circuit, the phase detector and the delay controller, and is activated by the enabling signal It can be the delay line, the replica circuit, the phase detector and the delay controller. 一種用於一延遲鎖相迴路裝置的操作方法，包括：接收一輸入時脈，並反應於多位元的一延遲碼對該輸入時脈進行延遲，藉以提供一延遲時脈；依據該延遲時脈產生一回饋時脈；比較該輸入時脈以及該回饋時脈以產生一延遲控制訊號；以及 基於一控制時脈依據該延遲控制訊號在一第一時間點產生該延遲碼，延遲一複本延遲時間長度以在一第二時間點提供該延遲碼，並在該第二時間點對該輸入時脈的時序進行調整，其中該複本延遲時間長度依據該延遲鎖相迴路裝置的製程所產生的一電晶體偏斜被調整，並且該控制時脈的週期被調整為大於該複本延遲時間長度。 An operating method for a delay locked loop device includes: receiving an input clock and delaying the input clock with a delay code of multiple bits to provide a delay clock; according to the delay time Generates a feedback clock; compares the input clock and the feedback clock to generate a delay control signal; and Based on a control clock, the delay code is generated at a first time point according to the delay control signal, a duplicate delay time length is delayed to provide the delay code at a second time point, and the input time is at the second time point. The timing of the pulse is adjusted, wherein the length of the replica delay time is adjusted according to a transistor deflection generated by the process of the delay lock loop device, and the period of the control clock is adjusted to be greater than the length of the replica delay time. 如請求項9所述的操作方法，還包括：在該第二時間點之後的一第三時間點提供另一延遲碼，其中該第三時間點與該第一時間點之間的時間長度實質上等於該控制時脈的週期。 The operation method according to claim 9, further comprising: providing another delay code at a third time point after the second time point, wherein the length of time between the third time point and the first time point is substantially Up is equal to the period of the control clock. 如請求項9所述的操作方法，其中該電晶體偏斜取決於電晶體中的臨界電壓值。 The operation method according to claim 9, wherein the deflection of the transistor depends on the threshold voltage value in the transistor. 如請求項11所述的操作方法，其中該複本延遲時間長度依據該電晶體偏斜中的慢偏斜被增加，其中該複本延遲時間長度依據該電晶體偏斜中的快偏斜被降低。 The operating method according to claim 11, wherein the length of the replica delay time is increased according to the slow skew in the transistor deflection, and wherein the length of the replica delay time is decreased according to the fast skew in the transistor deflection. 如請求項9所述的操作方法，還包括：依據一致能訊號提供該控制時脈。 The operation method according to claim 9, further comprising: providing the control clock according to the consistent energy signal.
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