TWI596734B - 半導體元件 - Google Patents

半導體元件 Download PDF

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Publication number
TWI596734B
TWI596734B TW105117997A TW105117997A TWI596734B TW I596734 B TWI596734 B TW I596734B TW 105117997 A TW105117997 A TW 105117997A TW 105117997 A TW105117997 A TW 105117997A TW I596734 B TWI596734 B TW I596734B
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TW
Taiwan
Prior art keywords
layer
disposed
semiconductor device
bump
wiring layer
Prior art date
Application number
TW105117997A
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English (en)
Other versions
TW201743424A (zh
Inventor
莊坤樹
Original Assignee
南茂科技股份有限公司
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Application filed by 南茂科技股份有限公司 filed Critical 南茂科技股份有限公司
Priority to TW105117997A priority Critical patent/TWI596734B/zh
Priority to CN201610650385.5A priority patent/CN107481986B/zh
Priority to US15/281,095 priority patent/US10068861B2/en
Application granted granted Critical
Publication of TWI596734B publication Critical patent/TWI596734B/zh
Publication of TW201743424A publication Critical patent/TW201743424A/zh

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Description

半導體元件
本發明是有關於一種積體電路，且特別是有關於一種半導體元件。
隨著科技日新月異，提高半導體元件的積集度且縮小關鍵尺寸已然逐漸成為一種趨勢。在此趨勢下，提供較充足的表面區域以承載較多的輸入/輸出（I/O）之晶圓級封裝結構的技術便隨之應運而生。此外，亦可於半導體晶片上形成重配置線路層（Redistribution layer，RDL），以將半導體晶片上的銲墊重新分配至任意位置。
一般而言，大多採用金屬銅來當作重配置線路層的主要材料。金屬銅不僅導電性以及導熱性良好，亦富延展性。相對地，金屬銅受熱後亦十分容易膨脹，尤其是當金屬銅使用在面積較大的地方（像是焊墊或是重配置線路層）時，金屬銅的膨脹現象將更加明顯，容易造成重配置線路層與其下方的保護層之間剝落（Peeling）、分層（de-lamination）或是破裂（crack）的現象，進而降低可靠度。
本發明提供一種具有凸起圖案的半導體元件，其可減少重配置線路層與其下方的保護層之間剝落、分層或是破裂的現象，進而提升可靠度。
本發明提供一種半導體元件，包括：基底、焊墊、保護層、多個凸起圖案、重配置線路層以及凸塊。焊墊配置於基底上。保護層配置於基底上。保護層具有第一開口，其暴露焊墊的部分表面。凸起圖案配置於保護層上。重配置線路層配置於凸起圖案上。重配置線路層自焊墊延伸至凸起圖案上。凸塊配置於凸起圖案上。
在本發明的一實施例中，所述重配置線路層具有凹凸表面。凹凸表面對應於凸起圖案。
在本發明的一實施例中，所述重配置線路層與焊墊直接接觸。
在本發明的一實施例中，所述半導體元件更包括絕緣層以及球底金屬層。絕緣層配置於重配置線路層上。絕緣層具有第二開口。第二開口暴露重配置線路層的表面且對應於凸起圖案。球底金屬層至少覆蓋第二開口的表面且配置於凸塊與重配置線路層之間。
在本發明的一實施例中，所述半導體元件更包括頂蓋層配置於凸塊上。
在本發明的一實施例中，所述凸塊的頂面具有凹凸表面。凹凸表面對應於凸起圖案。
在本發明的一實施例中，所述半導體元件更包括介電層配置於凸起圖案與保護層之間。
在本發明的一實施例中，各所述凸起圖案的形狀包括塊狀、條狀、環狀或其組合。
在本發明的一實施例中，所述凸塊的高度為凸起圖案的高度的4至14倍。
本發明提供另一種半導體元件，包括：基底、焊墊、保護層、圖案化介電層、重配置線路層以及凸塊。焊墊配置於基底上。保護層配置於基底上。保護層具有第一開口。第一開口暴露焊墊的部分表面。圖案化介電層配置於保護層上。圖案化介電層包括主體部與配置於主體部之上或主體部之中的多個凸起圖案。重配置線路層配置於圖案化介電層上。重配置線路層自焊墊延伸至凸起圖案上。凸塊配置於凸起圖案上。
在本發明的一實施例中，所述半導體元件更包括絕緣層以及球底金屬層。絕緣層配置於重配置線路層上。絕緣層具有第二開口。第二開口暴露重配置線路層的表面且對應於凸起圖案。球底金屬層至少覆蓋第二開口的表面且配置於凸塊與重配置線路層之間。
在本發明的一實施例中，所述重配置線路層具有凹凸表面。凹凸表面對應於凸起圖案。
基於上述，本發明藉由在凸塊下方形成由介電材料所構成的凸起圖案，使得凸塊與凸起圖案之間的金屬層（可例如是重配置線路層與球底金屬層）具有凹凸表面。因此，相較於習知的平坦表面，本實施例可改善所述金屬層的應力釋放並減少橫向的熱膨脹效應。也就是說，本實施例可降低所述金屬層及其下方的保護層之間剝落、分層或是破裂的現象，進而提升可靠度。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
參照本實施例之圖式以更全面地闡述本發明。然而，本發明亦可以各種不同的形式體現，而不應限於本文中所述之實施例。圖式中的層與區域的厚度會為了清楚起見而放大。相同或相似之標號表示相同或相似之元件，以下段落將不再一一贅述。
圖1A至圖1F是依照本發明之第一實施例的一種半導體元件的製造流程的剖面示意圖。圖2A至圖2B分別為圖1A之部分的上視示意圖。
請參照圖1A，本發明提供第一實施例之半導體元件10的製造流程，其步驟如下。首先，提供基底100。基底100的材料可例如是選自於由Si、Ge、SiGe、GaP、GaAs、SiC、SiGeC、InAs與InP所組成的群組中的至少一種材料。基底100也可以是覆矽絕緣（SOI）基底。
接著，形成焊墊102於基底100的主動面S上。在一實施例中，焊墊102的材料包括金屬材料。所述金屬材料可例如是銅、鋁、金、銀、鎳、鈀或其組合。保護層104的形成方法可例如是物理氣相沈積法。
之後，形成保護層104於基底100上。保護層104具有第一開口105。第一開口105暴露焊墊102的部分表面。在一實施例中，保護層104的材料可例如是氧化矽、氮化矽、磷矽玻璃（PSG）或其組合。保護層104的形成方法可例如是藉由網版印刷、塗佈或是直接將乾膜型態的保護材料層貼附在基底100上。之後，再對所述保護材料層進行微影與蝕刻製程，以圖案化所述保護材料層。
然後，形成多個凸起圖案106於保護層104上。如圖1A所示，凸起圖案106配置於焊墊102以外的保護層104上。在一實施例中，凸起圖案106的材料包括介電材料，所述介電材料可例如是聚醯亞胺（Polyimide，PI）、聚苯噁唑（polybezoxazole，PBO）、苯環丁烯（Benzocyclobutene，BCB）或其組合。凸起圖案106的形成方法可例如是藉由塗佈或是化學氣相沈積法將凸起圖案材料層形成在基底100上。之後，再對所述凸起圖案材料層（未繪示）進行微影與蝕刻製程，以圖案化所述凸起圖案材料層。
值得一提的是，從圖1A的部分P之上視圖來看，單一個凸起圖案106的形狀可例如是塊狀（如圖2A所示）、條狀（如圖2B所示）、環狀（未繪示）或其組合。多個凸起圖案106與保護層104則可形成網格狀圖案（如圖2A所示）、柵狀圖案（如圖2B所示）、同心圓圖案（未繪示）或其組合。但本發明不以此為限，只要凸起圖案106自保護層104表面的垂直方向突出，凸起圖案106的單一個形狀以及凸起圖案106與保護層104所構成的圖案並不設限。
請參照圖1B，形成重配置線路層108於凸起圖案106上。重配置線路層108自焊墊102延伸至凸起圖案106上。而且，重配置線路層108與焊墊102直接接觸，以將銲墊102重新分配至任意位置，進而符合使用者或客戶的需求。另一方面來看，重配置線路層108覆蓋保護層104的表面、凸起圖案106的表面以及焊墊102的表面。由於重配置線路層108覆蓋凸起圖案106的表面，因此，重配置線路層108對應於凸起圖案106亦具有一凹凸表面107。於此，所述「對應」亦即凹凸表面107位於凸起圖案106上，以下相關內容便不再贅述。在一實施例中，重配置線路層108的材料包括金屬材料，所述金屬材料可例如是銅或其他導電性、導熱性以及延展性佳的金屬材料。重配置線路層108的的形成方法可例如是物理氣相沈積法。
值得注意的是，由於對應於凸起圖案106的重配置線路層108具有凹凸表面107，因此，相較於平坦表面，本實施例可改善重配置線路層108的應力釋放並減少橫向的熱膨脹效應。也就是說，本實施例可降低重配置線路層108及其下方的保護層104之間剝落、分層或是破裂的現象，進而提升可靠度。
請參照圖1C，形成絕緣層110於重配置線路層108上。絕緣層110具有第二開口111。第二開口111暴露重配置線路層108的表面且對應於凸起圖案106。在一實施例中，絕緣層110的材料包括介電材料，所述介電材料可例如是聚醯亞胺、氧化矽、氮化矽或其組合。絕緣層110的形成方法可例如是化學氣相沈積法。
請參照圖1D，形成球底金屬層112於凸起圖案106上。球底金屬層112不僅覆蓋第二開口111的表面，還延伸至絕緣層110的部分表面。雖然圖1D所繪示的球底金屬層112為單層結構。但本發明不以此為限，在其他實施例中，球底金屬層112亦可例如是雙層結構或是多層結構。在一實施例中，球底金屬層112可例如是鎳層、鈦層、鈦鎢層、鈀層、金層、銀層或其組合的任意層結構。球底金屬層112的形成方法可例如是物理氣相沈積法。
請參照圖1E，形成圖案化光阻層114於絕緣層110上。圖案化光阻層114具有第三開口115。第三開口115暴露球底金屬層112的表面且對應於凸起圖案106。在一實施例中，圖案化光阻層114的材料可例如是正型光阻或負型光阻，其形成方法可例如是旋轉塗佈法。
接著，於第二開口111與第三開口115中形成凸塊116。由於凸塊116對應於凸起圖案106，因此，凸塊116亦具有一凹凸表面117對應於凸起圖案106。在一實施例中，凸塊116的材料包括金屬材料，所述金屬材料可例如是金、銅或其他導電性、導熱性以及延展性佳的金屬材料。凸塊116的形成方法可例如是電鍍、化學鍍或其他適合方法。雖然圖1E所繪示的凸塊116的凹凸表面117與圖案化光阻層114的頂面實質上共平面。但本發明不以此為限，在其他實施例中，凸塊116的凹凸表面117亦可高於或低於圖案化光阻層114的頂面。
請參照圖1F，形成頂蓋層118於凸塊116的凹凸表面117上。接著，移除圖案化光阻層114，並加熱迴焊。頂蓋層118的材料可例如是錫、錫銀合金、金錫合金，其熔點小於凸塊116的熔點，因此，適用於接合至其他載體。在一實施例中，凸塊116的高度H1為凸起圖案的高度H2的4至14倍，但本發明不以此為限。
圖3是依照本發明之第二實施例的一種半導體元件的剖面示意圖。
請參照圖3，基本上，第二實施例之半導體元件20與第一實施例之半導體元件10相似。上述兩者不同之處在於：第二實施例之半導體元件20的凸塊216具有一平坦表面217，形成平坦化表面217的方式可於形成凸塊216後再進一步利用研磨方式平坦化凸塊216表面。
圖4是依照本發明之第三實施例的一種半導體元件的剖面示意圖。
請參照圖4，基本上，第三實施例之半導體元件30與第一實施例之半導體元件10相似。上述兩者不同之處在於：第三實施例之半導體元件30更包括介電層305配置於凸起圖案106與保護層104之間。在一實施例中，介電層305的材料與凸起圖案106的材料相同，亦或不同。舉例來說，凸起圖案106與介電層305可皆為聚醯亞胺。另一方面，介電層305可為氧化矽；而凸起圖案106則可為聚醯亞胺。
圖5是依照本發明之第四實施例的一種半導體元件的剖面示意圖。
請參照圖5，基本上，第四實施例之半導體元件40與第三實施例之半導體元件30相似。上述兩者不同之處在於：第四實施例之半導體元件40具有圖案化介電層406配置於保護層104與重配置線路層108之間。具體來說，圖案化介電層406包括主體部406a與配置於主體部406a上的多個凸起圖案406b。在一實施例中，圖案化介電層406的材料包括介電材料，所述介電材料可例如是聚醯亞胺、聚苯噁唑、苯環丁烯或其組合。圖案化介電層406的的形成方法可例如是藉由塗佈或是化學氣相沈積法將介電層材料層（未繪示）形成在保護層104上。之後，再將圖案化罩幕層（未繪示）形成在所述介電層材料層上，其中所述圖案化罩幕層僅覆蓋或保護對應於凸起圖案406b的所述介電層材料層的區域上。接著，以所述圖案化罩幕層為罩幕，對所述介電層材料層進行蝕刻製程，以移除未被所述圖案化罩幕層覆蓋或保護的所述介電層材料層，藉此圖案化所述介電層材料層。需注意的是，在進行蝕刻製程時，可藉由控制蝕刻參數，使得圖案化介電層406未暴露其下方的保護層104的表面。此外，在本實施例中，亦可再進行另一道微影蝕刻製程，以移除焊墊102上的圖案化介電層406。
圖6A是依照本發明之第五實施例的一種半導體元件的剖面示意圖。圖6B是依照本發明之第六實施例的一種半導體元件的剖面示意圖。
請參照圖6A，基本上，第五實施例之半導體元件50與第四實施例之半導體元件40相似。上述兩者不同之處在於：第五實施例的圖案化介電層506之主體部506a上具有多個開口505，使得多個凸出圖案506b形成在開口505之間的主體部506a上。由於開口505與凸出圖案506b的表面形成一凹凸表面，因此，對應於開口505與凸出圖案506b上的重配置線路層108亦具有一凹凸表面。此凹凸表面可改善重配置線路層108的應力釋放並減少橫向的熱膨脹效應，進而提升可靠度。
在一實施例中，開口505可暴露出部分主體部506a的表面（如圖6A所示）。在另一實施例中，開口605亦可貫穿圖案化介電層606，以暴露出下方的保護層104的表面（如圖6B所示）。也就是說，第六實施例之半導體元件60的凸出圖案606b配置在主體部606a之中，而主體部606a包圍且環繞凸出圖案606b。由於開口605與凸出圖案606b的表面形成一凹凸表面，因此，對應於開口605與凸出圖案606b上的重配置線路層108亦具有一凹凸表面。
在一實施例中，圖案化介電層506、606的材料與形成方法與上述圖案化介電層406的材料與形成方法相似，其中形成方法的不同之處在於：將圖案化罩幕層（未繪示）形成在所述介電層材料層上時，第五實施例與第六實施例之所述圖案化罩幕層覆蓋或保護對應於開口505、605以外的所述介電層材料層的區域上。因此，在進行蝕刻製程之後，對應於開口505、605的所述介電層材料層的區域被移除，以形成具有多個開口505的圖案化介電層506或是具有多個開口605的圖案化介電層606。
綜上所述，本發明藉由在凸塊下方形成由介電材料所構成的凸起圖案，使得凸塊與凸起圖案之間的金屬層（可例如是重配置線路層與球底金屬層）具有凹凸表面。因此，相較於習知的平坦表面，本實施例可改善所述金屬層的應力釋放並減少橫向的熱膨脹效應。也就是說，本實施例可降低所述金屬層及其下方的保護層之間剝落、分層或是破裂的現象，進而提升可靠度。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20、30、40、50、60‧‧‧半導體元件
100‧‧‧基底
102‧‧‧焊墊
104‧‧‧保護層
105‧‧‧第一開口
106‧‧‧凸起圖案
107、117‧‧‧凹凸表面
108‧‧‧重配置線路層
110‧‧‧絕緣層
111‧‧‧第二開口
112‧‧‧球底金屬層
114‧‧‧圖案化光阻層
115‧‧‧第三開口
116、216‧‧‧凸塊
118‧‧‧頂蓋層
217‧‧‧平坦表面
305‧‧‧介電層
406、506、606‧‧‧圖案化介電層
406a、506a、606a‧‧‧主體部
406b、506b、606b‧‧‧凸起圖案
505、605‧‧‧開口
H1、H2‧‧‧高度
P‧‧‧部分
S‧‧‧主動面
圖1A至圖1F是依照本發明之第一實施例的一種半導體元件的製造流程的剖面示意圖。 圖2A至圖2B分別為圖1A之部分的上視示意圖。 圖3是依照本發明之第二實施例的一種半導體元件的剖面示意圖。 圖4是依照本發明之第三實施例的一種半導體元件的剖面示意圖。 圖5是依照本發明之第四實施例的一種半導體元件的剖面示意圖。 圖6A是依照本發明之第五實施例的一種半導體元件的剖面示意圖。 圖6B是依照本發明之第六實施例的一種半導體元件的剖面示意圖。
10‧‧‧半導體元件
100‧‧‧基底
102‧‧‧焊墊
104‧‧‧保護層
105‧‧‧第一開口
106‧‧‧凸起圖案
108‧‧‧重配置線路層
110‧‧‧絕緣層
112‧‧‧球底金屬層
116‧‧‧凸塊
117‧‧‧凹凸表面
118‧‧‧頂蓋層
H1、H2‧‧‧高度

Claims (10)

  1. 一種半導體元件，包括：一焊墊，配置於一基底上；一保護層，配置於該基底上，該保護層具有一第一開口，該第一開口暴露該焊墊的部分表面；多個凸起圖案，配置於該保護層上；一重配置線路層，配置於該些凸起圖案上，其中該重配置線路層自該焊墊延伸至該些凸起圖案上，且該重配置線路層具有一凹凸表面，該凹凸表面對應於該些凸起圖案；以及一凸塊，配置於該些凸起圖案上。
  2. 如申請專利範圍第1項所述的半導體元件，其中該重配置線路層與該焊墊直接接觸。
  3. 如申請專利範圍第1項所述的半導體元件，更包括：一絕緣層，配置於該重配置線路層上，其中該絕緣層具有一第二開口，該第二開口暴露該重配置線路層的表面且對應於該些凸起圖案；以及一球底金屬層，至少覆蓋該第二開口的表面，且配置於該凸塊與該重配置線路層之間。
  4. 如申請專利範圍第1項所述的半導體元件，更包括一頂蓋層配置於該凸塊上。
  5. 如申請專利範圍第1項所述的半導體元件，其中該凸塊的頂面具有一凹凸表面，該凹凸表面對應於該些凸起圖案。
  6. 如申請專利範圍第1項所述的半導體元件，更包括一介電層配置於該些凸起圖案與該保護層之間。
  7. 如申請專利範圍第1項所述的半導體元件，其中各該些凸起圖案的形狀包括塊狀、條狀、環狀或其組合。
  8. 如申請專利範圍第1項所述的半導體元件，其中該凸塊的高度為該些凸起圖案的高度的4至14倍。
  9. 一種半導體元件，包括：一焊墊，配置於一基底上；一保護層，配置於該基底上，該保護層具有一第一開口，該第一開口暴露該焊墊的部分表面；一圖案化介電層，配置於該保護層上，其中該圖案化介電層包括一主體部與配置於該主體部之上或該主體部之中的多個凸起圖案；一重配置線路層，配置於該圖案化介電層上，其中該重配置線路層自該焊墊延伸至該些凸起圖案上，且該重配置線路層具有一凹凸表面，該凹凸表面對應於該些凸起圖案；以及一凸塊，配置於該些凸起圖案上。
  10. 如申請專利範圍第9項所述的半導體元件，更包括：一絕緣層，配置於該重配置線路層上，其中該絕緣層具有一第二開口，該第二開口暴露該重配置線路層的表面且對應於該些凸起圖案；以及一球底金屬層，至少覆蓋該第二開口的表面，且配置於該凸塊與該重配置線路層之間。
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Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI678801B (zh) * 2018-06-01 2019-12-01 友達光電股份有限公司 顯示裝置
WO2020208539A1 (en) 2019-04-10 2020-10-15 Murata Manufacturing Co., Ltd. Electrical component with interconnection elements
CN111863787B (zh) * 2019-04-29 2022-05-24 群创光电股份有限公司 电子装置
US10957664B2 (en) * 2019-05-29 2021-03-23 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
US10825789B1 (en) 2019-08-26 2020-11-03 Nxp B.V. Underbump metallization dimension variation with improved reliability
CN111599792A (zh) * 2020-05-29 2020-08-28 苏州英嘉通半导体有限公司 一种晶圆级重新布线层结构及其制作方法
CN111554582B (zh) * 2020-06-11 2022-07-15 厦门通富微电子有限公司 一种芯片封装方法和芯片封装器件
KR20220056309A (ko) 2020-10-27 2022-05-06 삼성전자주식회사 반도체 패키지
CN113517249B (zh) * 2021-09-10 2021-12-21 甬矽电子(宁波)股份有限公司 凸块缓冲封装结构和凸块缓冲封装结构的制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200802646A (en) * 2006-02-20 2008-01-01 Nepes Corp Semiconductor chip having solder bump and method of frabricating the same
CN103295997A (zh) * 2012-03-01 2013-09-11 台湾积体电路制造股份有限公司 用于芯片尺寸封装的电连接件
US20140061900A1 (en) * 2012-08-30 2014-03-06 No Sun Park Semiconductor package with improved redistribution layer design and fabricating method thereof
TW201515125A (zh) * 2013-10-09 2015-04-16 Powertech Technology Inc 消弭銲料共平面差異之不等高柱狀凸塊結構

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100448344B1 (ko) * 2002-10-22 2004-09-13 삼성전자주식회사 웨이퍼 레벨 칩 스케일 패키지 제조 방법
TWI297205B (en) 2006-03-01 2008-05-21 Chipmos Technologies Inc Semiconductor element and manufaturing process thereof
TW200820406A (en) 2006-10-19 2008-05-01 Novatek Microelectronics Corp Chip structure and wafer structure
US8058726B1 (en) * 2008-05-07 2011-11-15 Amkor Technology, Inc. Semiconductor device having redistribution layer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200802646A (en) * 2006-02-20 2008-01-01 Nepes Corp Semiconductor chip having solder bump and method of frabricating the same
CN103295997A (zh) * 2012-03-01 2013-09-11 台湾积体电路制造股份有限公司 用于芯片尺寸封装的电连接件
US20140061900A1 (en) * 2012-08-30 2014-03-06 No Sun Park Semiconductor package with improved redistribution layer design and fabricating method thereof
TW201515125A (zh) * 2013-10-09 2015-04-16 Powertech Technology Inc 消弭銲料共平面差異之不等高柱狀凸塊結構

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