TWI586005B - 將發光裝置附著至支撐基板的方法 - Google Patents
將發光裝置附著至支撐基板的方法 Download PDFInfo
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- TWI586005B TWI586005B TW101119214A TW101119214A TWI586005B TW I586005 B TWI586005 B TW I586005B TW 101119214 A TW101119214 A TW 101119214A TW 101119214 A TW101119214 A TW 101119214A TW I586005 B TWI586005 B TW I586005B
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- Prior art keywords
- emitting device
- wafer
- light emitting
- semiconductor light
- metal
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- H01L27/15—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
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- H01L33/08—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body
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- H01L33/30—Materials of the light emitting region containing only elements of Group III and Group V of the Periodic Table
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- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Led Devices (AREA)
- Led Device Packages (AREA)
Description
本發明係關於一種用於將一半導體發光裝置附著至一支撐基板之晶圓規模製程。
半導體發光裝置(包含發光二極體(LED)、諧振腔發光二極體(RCLED)、垂直腔雷射二極體(VCSEL)及邊射型雷射)屬於目前可用之最高效光源。當前在製造能夠跨越可見光譜操作之高亮度發光裝置中所關注之材料系統包含III-V族半導體,尤其鎵、鋁、銦及氮之二元、三元及四元合金(亦稱為III族氮化物材料)。通常,III族氮化物發光裝置係透過藉由金屬-有機物化學汽相沈積(MOCVD)、分子束磊晶(MBE)或其他磊晶技術在一藍寶石、碳化矽、III族氮化物或其他適合基板上磊晶生長不同組合物及摻雜劑濃度之半導體層之一堆疊來製作。該堆疊通常包含形成於基板上方之摻雜有(例如)Si之一或多個n型層、形成於該(等)n型層上方之一作用區域中之一或多個發光層、及形成於該作用區域上方之摻雜有(例如)Mg之一或多個p型層。電觸點形成於該等n型區域及p型區域上。
圖10圖解說明在US 6,876,008中更詳細闡述之附著至一基台114之一發光二極體晶粒110。該基台頂部表面及底部表面上之可焊接表面之間的電連接形成於該基台內。其上安置有焊料球122-1及122-2之該基台頂部上之可焊接區係藉由該基台內之一導電路徑電連接至該基台底部上之可焊
接區域,該等可焊接區域附著至焊料接頭138。焊料接頭138將該基台底部上之可焊接區電連接至一板134。舉例而言,基台114可係具有數個不同區域之一矽/玻璃複合基台。矽區域114-2由形成該基台頂部表面與底部表面之間的導電路徑之金屬化物118-1及118-2環繞。諸如ESD保護電路之電路可形成於由金屬化物118-1及118-2環繞之矽區域114-2中,或其他矽區域114-3中。此等其他矽區域114-3亦可電接觸晶粒110或板134。玻璃區域114-1將不同矽區域電隔離。焊料接頭138可藉由係(舉例而言)一介電層或空氣之一絕緣區域135電隔離。
在圖10中所圖解說明之裝置中,包含金屬化物118-1及118-2之基台114係在將晶粒110附著至基台114之前與晶粒110分開形成。舉例而言,US 6,876,008解釋由用於諸多基台之位點組成之一矽晶圓經生長以包含諸如上文提及之ESD保護電路之任何所要電路。在晶圓中藉由習用遮蔽及蝕刻步驟形成孔。在晶圓上方且在孔中形成諸如一金屬之一導電層。然後可將該導電層圖案化。然後在晶圓上方且在孔中形成一玻璃層。移除玻璃層及晶圓之部分以曝露該導電層。然後可將晶圓底側上之導電層圖案化,且可添加額外導電層並將其圖案化。一旦將晶圓底側圖案化,個別LED晶粒110可藉由互連件122實體且電連接至基臺上之導電區域。換言之,在將LED 110切割為個別二極體之後附著至基台114。
本發明之一目的係提供一種用於將一半導體發光裝置附著至一支撐基板之晶圓規模製程。
根據本發明之實施例之一方法包含提供一半導體發光裝置晶圓,每一半導體發光裝置包含夾在一n型區域與一p型區域之間之一發光層。提供一支撐基板晶圓,每一支撐基板包含一主體。將該半導體發光裝置晶圓接合至該支撐基板晶圓。延伸穿過每一支撐基板之該主體之整個厚度形成通孔。
一晶圓規模製程可藉由允許習用地以一晶粒規模執行之某些處理步驟以一晶圓規模來執行而減小成本。
在本發明之實施例中,在一晶圓規模製程中將一半導體發光裝置接合至一基座。儘管在下文實例中該半導體發光裝置係發藍光或UV光之III族氮化物LED,但亦可使用除LED外的諸如雷射二極體及由諸如其他III-V族材料、III-族磷化物、III族砷化物、II-VI族材料、ZnO或基於Si之材料之其他材料系統製成之半導體發光裝置之半導體發光裝置。
圖1圖解說明一半導體發光裝置晶圓之一部分。圖1中圖解說明兩個裝置。為形成圖1中所圖解說明之結構,在一生長基板上方生長一半導體結構,該生長基板可係諸如藍寶石、SiC、Si、GaN或複合基板之任何適合基板10。該半導體結構包含夾在n型區域12與p型區域16之間之一發光或作用區域14。可首先生長一n型區域12,且n型區域12可包
含不同組合物及摻雜劑濃度之多個層,其包含(舉例而言)諸如緩衝層或成核層之準備層,及/或經設計以促進生長基板之移除的層(其可係n型或無意摻雜的),及經設計用於發光區域高效發光所期望之特定光學或電學特性之n型或甚至p型裝置層。一發光或作用區域14生長於n型區域12上方。適合發光區域之實例包含一單個厚或薄發光層,或包含藉由障壁層分離之多個薄或厚發光層之一多個量子井發光區域。然後一p型區域16可生長於發光區域14上方。如同n型區域12,p型區域16可包含不同組合物、厚度及摻雜劑濃度之多個層,其包含無意摻雜之層或n型層。裝置中所有半導體材料之總厚度在某些實施例中小於10 μm,且在某些實施例中小於6 μm。在某些實施例中,首先生長p型區域,後續接著作用區域,後續接著n型區域。在某些實施例中,可視情況在生長之後在200℃與800℃之間對半導體材料進行退火。
然後在p型區域16上形成金屬觸點。在圖1之裝置中,p觸點包含兩個金屬層18及20。可藉由例如蒸鍍或濺鍍來沈積金屬18,然後藉由包含例如蝕刻或剝離之標準光微影操作來圖案化。金屬18可係與諸如銀之p型III族氮化物材料形成一歐姆接觸之一反射性金屬。金屬18亦可係一過渡金屬及銀之一多層堆疊。舉例而言,該過渡金屬可係鎳。金屬18在某些實施例中係介於100 Å與2000 Å之間厚,在某些實施例中介於500 Å與1700 Å之間厚,且在某些實施例中介於1000 Å與1600 Å之間。可視情況在金屬18沈積之後
對該結構進行第二次退火。
可藉由例如蒸鍍或濺鍍將一選用第二p觸點金屬20沈積在p-觸點金屬18上方,然後藉由諸如蝕刻或剝離之標準光微影操作來圖案化。金屬20可係最低限度地與銀反應之任何導電材料,諸如鈦與鎢之一合金。可將此合金部分地、完全地或根本不氮化。另一選擇為,金屬20可係鉻、鉑或矽,或可係經最佳化以用於黏附至周圍層及用於阻擋金屬18之擴散之上述材料中之任一者的一多層堆疊。金屬20在某些實施例中可係介於1000 Å與10000 Å之間厚,在某些實施例中介於2000 Å與8000 Å之間,且在某些實施例中介於2000 Å與7000 Å之間厚。
然後藉由標準光微影操作將該結構圖案化,且藉由舉例而言其中使用化學反應性電漿來移除半導體材料之反應性離子蝕刻(RIE),或其中藉由一RF供電之磁場產生電漿之一RIE製程之感應耦合式電漿(ICP)蝕刻來蝕刻該結構。在某些實施例中,該圖案係藉由用於圖案化p觸點金屬20之光微影遮罩來決定。在此等實施例中,可在蝕刻p觸點金屬20之後在一單個操作中執行蝕刻。在某些區域中,移除p-型區域16之整個厚度及發光區域14之整個厚度,從而顯露n型區域12之一表面13。然後在裝置之間的區域11中蝕除n型區域12,從而顯露生長基板10,以使得III族氮化物材料自最終裝置之邊緣200縮進一距離202。舉例而言,可在某些實施例中使該III族氮化物材料自裝置之邊緣縮進介於1 μm與50 μm之間,在某些實施例中縮進小於20 μm,
在某些實施例中縮進小於10 μm,且在某些實施例中縮進小於6 μm。
舉例而言,可藉由電漿增強型化學汽相沈積(PECVD)、化學汽相沈積(CVD)或蒸鍍將一電介質22沈積於圖1中之結構上。電介質22為連接至n型及p型區域之金屬觸點提供電隔離。藉由標準光微影操作圖案化且藉由ICP蝕刻或RIE蝕刻電介質22以曝露區域13中之n型區域12且曝露區域24中之p觸點金屬20。亦可藉由剝離來圖案化電介質22。電介質22可係包含氮化矽、氧化矽及氧氮化矽之任何適合電介質。在某些實施例中,電介質22係經最佳化以反射入射在其上之光之一多層介電堆疊。電介質22在某些實施例中可係小於2 μm厚,在某些實施例中介於200 Å與5000 Å厚之間,且在某些實施例中介於500 Å與3200 Å厚之間。
圖1中展示兩個裝置以圖解說明本文中所述之該等裝置形成於一裝置晶圓上。為簡單起見,在圖2、圖3、圖4、圖5、圖6、圖7及圖8中僅展示一個裝置,但應瞭解彼等圖中所展示之結構係在一整個晶圓上重複的。
在圖2中,沈積在其接觸n型區域12區域中形成n觸點26之一金屬層27及一額外p觸點層32並將其圖案化。金屬27可係包含鋁之任何適合金屬或包含鋁、鈦鎢合金、銅及金之金屬之一多層堆疊。在金屬27係一多層堆疊之實施例中,第一金屬(亦即,毗鄰於n型區域12之金屬)可經選擇以形成至GaN之一歐姆接觸且係反射藍光及白光的。舉例而言,此一第一層可係鋁。最後的金屬可係適合於用以將裝
置附著至一基座之無論任何接合製程之一金屬。舉例而言,在某些實施例中,該接合製程係熱壓接合且該最後的金屬係金。可藉由包含(舉例而言)濺鍍、蒸鍍、電鍍或此等製程之一組合之任何適合製程來沈積金屬27。
儘管在圖2中所圖解說明之裝置中,n觸點26延伸於n型區域12之邊緣上方且接觸生長基板10,但在某些實施例中,n觸點26可自n型區域12之邊緣縮進以使得n觸點26不覆蓋n型區域12之邊緣。在此等實施例中,下文所述之聚合物層28可係較寬以使得其接觸未被n觸點26覆蓋之n型區域12之一部分。在某些實施例中,如展示一裝置之一部分之圖9中所圖解說明,將一反射性介電材料70沈積在n型區域12之邊緣周圍。舉例而言,反射性介電材料70可係與電介質22同時形成,或在單獨沈積及圖案化步驟中形成之一反射性介電堆疊。在任何情況下,n型區域12及n觸點26兩者皆自裝置之邊緣200縮進。
然後沈積一或多個聚合物層並將其圖案化。在毗鄰裝置之間沈積聚合物層28。聚合物層30將p觸點32與n觸點26分離。聚合物層28及30可係相同材料且可在相同操作中沈積並圖案化,但亦不需要如此。舉例而言,在圖4中所圖解說明之裝置中,聚合物層28及30以及接合層42可全部係在一單個步驟中沈積之相同材料。在此情況下,不需要將經沈積材料圖案化且可不需要平坦化。在某些實施例中,聚合物層28及30耐高溫。適合材料之實例包含基於苯并環丁烯之聚合物、基於聚醯亞胺之聚合物及環氧樹脂。在某些
實施例中,聚合物層28摻雜有諸如鈦氧化物之一散射組份或諸如碳黑之一吸光材料。在某些實施例中聚合物層28可係聚矽氧。舉例而言,可藉由化學機械拋光、機械拋光或快速切削來平坦化經沈積聚合物層28及30。
將圖2中所圖解說明之該等裝置之一晶圓相對於圖2中所圖解說明之定向翻轉且接合至一支撐基板晶圓。圖3、圖4及圖5中圖解說明半導體發光裝置33與支撐基板34之間之適合接合的三個實例。圖3、圖4及圖5中所圖解說明之支撐基板34包含一主體35。該主體在某些實施例中可係Si、GaAs或Ge,或任何其他適合材料。在某些實施例中,可將電子器件整合至支撐基板34。舉例而言,整合元件可包含用於靜電放電保護之電路元件或驅動電子器件。適合整合元件之實例包含二極體、電阻器及電容器。整合元件可藉由習用半導體處理技術而形成。
在圖3中所圖解說明之結構中,一選用電介質36生長於支撐基板34上。電介質36可係主體35之一熱生長之原生氧化物(例如矽之氧化物)、藉由PECVD或CVD沈積之一電介質(例如矽之氧化物、氮化物或氧氮化物),或任何其他適合電介質。舉例而言,一熱氧化物可係藉由在含有O2及/或H2O之一氣體氣氛中以800℃至1200℃加熱矽生長。PECVD氧化物可係在矽烷及N2O或O2或者原矽酸四乙酯及N2O或O2之一氣氛中在150℃至400℃之一溫度下生長。CVD氧化物可係在矽烷及N2O或O2或者原矽酸四乙酯及N2O或O2之一氣氛中在300℃至900℃之一溫度下生長。
一金屬38沈積於電介質36(若存在)上或主體35上。舉例而言,金屬38可係藉由濺鍍、電鍍、蒸鍍、此等技術之一組合或任何其他適合技術沈積之銅、金或任何其他適合金屬。金屬38亦可包括一多層金屬堆疊。在其中金屬38係一多層堆疊之實施例中,該堆疊之最後一個經沈積層可係適用於用以將裝置33附著至支撐基板34之無論任何接合技術之一金屬。在某些實施例中,該接合技術係熱壓接合且該最後一個經沈積層可係金。舉例而言,可透過一加性製程或一減性製程將金屬38圖案化。
沈積一電介質40並將其圖案化。電介質40在電連接至n型及p型半導體層之金屬層之間提供電隔離,因此電介質40必須與聚合物層30對準。電介質40可係適合用作一接合材料或膠之一聚合物或其他有機材料。舉例而言,電介質40可係一基於苯并環丁烯之聚合物、一基於聚醯亞胺之聚合物、一基於聚矽氧之聚合物、一環氧樹脂、該等材料之一組合、任何其他適當有機材料或一無機電介質。視情況,舉例而言,可藉由拋光、藉由化學機械拋光或藉由任何其他適合製程來平坦化支撐基板34之頂部表面(亦即,金屬38及電介質40之頂部表面)。
在圖4中所圖解說明之結構中,一單個介電接合層42形成於圖2中所圖解說明之結構之頂部表面(亦即,金屬層26及32以及聚合物層28及30之頂部表面)上方。另一選擇為,電介質42可形成於支撐基板34之主體35上。電介質42可係適合用作一接合材料或膠之一聚合物或其他有機材
料。電介質42可係一基於苯并環丁烯之聚合物、一基於聚醯亞胺之聚合物、一環氧樹脂、一基於聚矽氧之聚合物或任何其他適當有機材料。電介質42可係與聚合物層28及30相同之材料,但不需要如此。舉例而言,電介質42可藉由旋塗而形成,且舉例而言可在沈積之後藉由化學-機械拋光、機械拋光或快速切削而平坦化。在電介質42係與聚合物層28及30相同之材料之實施例中,該裝置可在共沈積之後(舉例而言)在一單個步驟中藉由化學機械拋光而平坦化。在某些實施例中,不需要電介質42之平坦化。電介質42可在金屬層26及32上方係介於100 Å與1 μm之間厚,且跨越整個晶圓係平坦。
在圖5中所圖解說明之裝置中,接合層44及46分別形成於主體35及裝置33兩者上。形成於裝置33上之接合層46可係一電介質,諸如,(舉例而言)藉由PECVD在低溫下沈積之矽之氧化物、氮化矽或氧氮化矽。舉例而言,PECVD氧化物可係在矽烷及N2O或O2或者原矽酸四乙酯及N2O或O2之一氣氛中在150℃至400℃之一溫度下生長。在某些實施例中,電介質46可係介於100 Å與1 μm之間厚。形成於支撐基板34上之接合層44可係一電介質,諸如矽之氧化物、氮化矽或氧氮化矽。矽之氧化物可係一矽支撐基板上之一熱生長之氧化物、(舉例而言)藉由CVD在高溫下沈積或(舉例而言)藉由PECVD在低溫下沈積。在某些實施例中,電介質44可係介於100 Å與1 μm之間厚。舉例而言,一熱氧化物可係藉由在含有O2及/或H2O之一氣體氣氛中以800℃
至1200℃加熱矽生長。PECVD氧化物可係在矽烷及N2O或O2或者原矽酸四乙酯及N2O或O2之一氣氛中在150℃至400℃之一溫度下沈積。CVD氧化物可係在矽烷及N2O或O2或者原矽酸四乙酯及N2O或O2之一氣氛中在300℃至900℃之一溫度下沈積。
藉由舉例而言圖3、圖4及圖5中所圖解說明之接合結構中之一者將裝置33之一晶圓接合至支撐基板34之一晶圓。接合可係在某些實施例中在介於50℃與500℃之間且在某些實施例中介於100℃與250℃之間的一溫度下執行。在某些實施例中,可在小於5 MPa之一施加壓縮壓力下執行接合。在某些實施例中,在將生長基板10接合至支撐基板34之晶圓之後,可藉由(舉例而言)蝕刻或雷射剝離自裝置33移除生長基板。在其中移除生長基板10之實施例中,支撐基板34提供對裝置33之機械支撐,此乃因不具有生長基板之該裝置通常係如此薄以至於其不係機械上自支撐的。舉例而言,圖2中所圖解說明之不具有基板之該裝置的總厚度係不大於7 μm,且在某些實施例中不大於25 μm。可藉由諸如光電化學蝕刻之任何適合製程將藉由移除生長基板10而曝露之半導體材料圖案化或粗糙化以(舉例而言)增強光抽取。在某些實施例中,生長基板10保留為該最終裝置之部分。在某些實施例中,舉例而言,該生長基板可藉由鋸割或蝕刻成形。在接合至裝置33之前或之後,可將支撐基板34之主體35薄化至在某些實施例中介於50 μm與250 μm之間,且在某些實施例中介於80 μm與120 μm之間之一
厚度。舉例而言,薄化可藉由化學機械拋光或研磨及拋光執行。
如圖6、圖7及圖8中所圖解說明,在接合之後,在支撐基板中形成通孔且經接合結構經歷進一步處理。圖6圖解說明形成於圖3中所圖解說明之裝置中之通孔。圖7及圖8圖解說明形成於圖4中所圖解說明之裝置上之通孔以及金屬及介電層。可對圖3、圖4及圖5中所圖解說明之裝置中之任一者執行圖6、圖7及圖8中所圖解說明之處理。
如圖6中所圖解說明,穿過支撐基板34之主體35蝕刻通孔48。圖解說明兩個通孔,一個通孔顯露電連接至n型區域12之一金屬且一個通孔顯露電連接至p型區域16之一金屬。在圖6中所圖解說明之裝置(其包含圖3中圖解說明之接合)中,穿過主體35及選用電介質36蝕刻通孔48以顯露金屬層38。在圖4及圖5中所圖解說明之裝置中,穿過接合層42、44及46蝕刻通孔以顯露p金屬32及n金屬26。舉例而言,可藉由深反應性離子蝕刻、反應性離子蝕刻、濕式化學蝕刻或任何其他適合蝕刻技術蝕刻通孔48。在其中支撐基板34係Si之實施例中,適合蝕刻劑氣體包含(舉例而言)SF6且可在一通常稱為博施製程(Bosch Process)之一製程中使用(舉例而言)八氟環丁烷將蝕刻與在Si側壁上沈積一化學惰性鈍化層進行時間多工。在其中支撐基板34係GaAs之實施例中,適合蝕刻劑氣體包含(舉例而言)Cl2、HBr或Cl2與HBr之一混合物。在其中支撐基板34係Ge之實施例中,適合蝕刻劑氣體包含(舉例而言)Cl2、SCl4或Cl2與
SCl4之一混合物。在其中支撐基板34係GaAs或Ge之實施例中,亦可將蝕刻與在側壁上沈積一化學惰性鈍化層進行時間多工。通孔48之側壁可相對於主體35係垂直的或如圖6中所展示成某一角度。
如圖7中所圖解說明,然後將一電介質50沈積於主體35之表面上且通孔48中。舉例而言,電介質50可係(例如)藉由PECVD在低溫下沈積的矽之氧化物、矽之氮化物或矽之氧氮化物。舉例而言,PECVD氧化物可係在矽烷及N2O或O2或者原矽酸四乙酯及N2O或O2之一氣氛中在150℃至400℃之一溫度下沈積。在某些實施例中,電介質50可係介於100 Å與2 μm之間厚。隨後將電介質50圖案化以在通孔48頂部處曝露金屬層32及26。
沈積一金屬層然後將其圖案化以形成至p觸點及n觸點之電連接52及54。舉例而言,電連接52及54可係藉由電鍍、濺鍍或濺鍍及電鍍之一組合沈積之Cu。電連接52及54在某些實施例中可係介於1 μm與20 μm之間厚,且在某些實施例中介於6 μm與10 μm之間厚。在圖7中所展示之剖面圖上,通孔48未由電連接52及54完全填充。在某些實施例中,未由電介質50佔據之通孔48之部分可由電連接52及54完全填充。形成電連接52及54之金屬層可係(例如)藉由濺鍍或藉由濺鍍與電鍍之一組合沈積之包括Ti、TiW、Cu、Ni及Au之一多層金屬堆疊。
如圖8中所圖解說明,沈積一電介質55並將其圖案化以電隔離及/或保護電連接52及54。舉例而言,電介質55可
係一或多種基於苯丙環丁烯之聚合物或一或多種基於聚醯亞胺之聚合物。在其中通孔48尚未由形成電連接52及54之金屬層完全填充之實施例中,電介質55可經組態以大部分或完全填充通孔48,或可使通孔48未經填充。
視情況,接著沈積一額外金屬層以形成焊料連接56及58。該額外金屬可係適合作為電連接52及54與互連件60及62之間的一連接的任何金屬,在某些實施例中該等互連件係焊料凸塊。適合用於焊料連接56及58之結構之實例包含經濺鍍NiV或經電鍍Ni之一第一層然後接著經濺鍍或電鍍Au之一第二薄層;經濺鍍TiW之一第一層然後接著經濺鍍NiV或經電鍍Ni之一第二層然後接著經濺鍍或電鍍Au之一第三薄層;或經濺鍍或電鍍TiW之一第一層然後接著經電鍍Cu之一第二層然後接著經濺鍍或電鍍Au之一第三層。在某些實施例中,焊料連接56及58可具有介於1 μm與15 μm之間之一總厚度。
在某些實施例中,將一波長轉換層64安置在發光層14上方於由發光層發射之光之路徑中。波長轉換層64可與裝置間隔開,若已將生長基板10移除則可附著至n型區域12,或附著至生長基板10(若存在)。該波長轉換層包含經組態以吸收由發光層發射之光且發射一不同波長之光之一或多種波長轉換材料。該波長轉換材料可轉換由發光層發射且入射在該波長轉換層上之光之全部或僅一部分。由發光層發射之未經轉換光可係光之最終光譜之部分,儘管不需要為如此。常見組合之實例包含一發藍色光LED與一發黃色
光之波長轉換材料組合、一發藍色光LED與發綠色光及紅色光之波長轉換材料組合、一發UV光LED與發藍色光及黃色光之波長轉換材料組合,及一發UV光LED與發藍色光、綠色光及紅色光之波長轉換材料組合。可添加發射其他色彩之光之波長轉換材料以調節自該裝置發射之光之光譜。
舉例而言,波長轉換層64可係(舉例而言)藉由層壓沈積於晶圓上之存於一聚矽氧基質中之一磷光體粒子層。該波長轉換層厚度在某些實施例中可係介於10 μm與100 μm之間,在某些實施例中介於15 μm與50 μm之間,且在某些實施例中介於18 μm與30 μm之間。舉例而言,波長轉換層64可係藉由噴塗、電泳、包覆模製、模板印刷、絲網印刷或噴墨印刷、沉降、蒸鍍、濺鍍或任何其他適合技術沈積於裝置上方之存於一有機或無機囊封劑中之一粉末狀磷光體或量子點。舉例而言,波長轉換層64可係諸如藉由燒結形成之一固體陶瓷磷光體或一基於玻璃之磷光體之一預先形成自支撐層。此等自支撐層可不藉助一黏合劑直接接合至裝置或經由諸如一聚矽氧膠之一黏合劑接合。在某些實施例中,波長轉換層64可係包括直接沈積或接合至n型區域12之一第一高折射率間隔件材料及沈積於該間隔件材料頂部上之一磷光體層之一多層結構。適合磷光體之實例包含基於經摻雜釔鋁石榴石之磷光體、基於氮化物之磷光體及任何其他適合磷光體。
在某些實施例中,波長轉換層64係裝置中之唯一波長轉換材料。在某些實施例中,波長轉換層64與諸如其他磷光
體、量子點、半導體波長轉換元件或染料之其他波長轉換元件組合以產生白色光或其他色彩之單色光。
在某些實施例中,適合於將圖8中所展示之結構附著至諸如一印刷電路板之另一結構之選用互連件60及62形成於連接56及58上。互連件60及62通常係焊料凸塊但可使用任何適合互連件。舉例而言,焊料凸塊60及62可係錫、銀及銅之一合金(SAC焊料)或金及錫之一合金。舉例而言,可藉由包含電鍍之任何適合技術施加焊料。在電鍍之後,可隨後對該結構回銲以平滑該結構及焊料凸塊60及62之微結構。
然後可將接合至支撐基板34之裝置33之一晶圓切割為個別發光裝置晶片。如圖3、圖4、圖5、圖6、圖7及圖8中所圖解說明,由於將裝置33及支撐基板34一起切割,因此該支撐基板不比該裝置寬。舉例而言,單粒化可藉由習用鋸割、藉由使用193 nm、248 nm或355 nm光之雷射燒蝕或藉由水噴射切削來執行。舉例而言,單粒化亦可經由劃線及機械斷裂之一組合來執行,劃線係(舉例而言)藉由習用鋸割、藉由使用193 nm、248 nm或355 nm光之雷射燒蝕或藉由水噴射切削來執行。
由於上文所述裝置係在一晶圓規模上接合至支撐基板,本發明之實施例可提供優於其中將裝置逐個晶粒地接合至一支撐基板之習用方案之效率及成本減小。舉例而言,由於藉由在習用LED中通常在封裝級處執行之諸多處理操作之晶圓級LED處理之可能性,可提高效率,該等處理操作
包含生長基板移除、在生長基板移除之後半導體表面之粗糙化及形成一波長轉換層。
在一習用半導體垂直整合方案中,正整合之該等裝置經常標稱上係同一材料,或具有相似熱膨脹係數(CTE)之材料。因此,該等結構之晶圓接合可在升高溫下執行。在生長於藍寶石上且晶圓接合至一矽支撐基板晶圓之一III族氮化物裝置之情況下,藍寶石及矽之CTE係充分不同以致於在升高溫下之晶圓接合可導致將顯著應力鎖定至經接合結構中,從而導致在後續處理期間經接合結構之彎曲及斷裂。在某些上文所述實施例中,在低溫下將該等裝置接合至支撐基板,此可導致結構中之最小鎖定應力,此可改良良率。舉例而言,接合在某些實施例中在低於300℃下,且在某些實施例中在介於230℃與275℃或更低溫度之間執行。在使用基於聚矽氧之接合層之某些實施例中,接合可在低於150℃下執行。
在某些實施例中,由於支撐基板晶圓在接合時不包含特徵,可在不進行詳細對準之情形下將裝置晶圓接合至該支撐基板。舉例而言,裝置及支撐基板晶圓僅須藉由視覺對準而粗略地對準,而不需要兩個晶圓上之經圖案化特徵之精細對準。在接合之後,必須將通孔蝕刻遮罩對準至LED金屬化物,此可透過IR對準(其穿過經接合晶圓觀察)或背側對準(其將支撐基板晶圓側上之一遮罩與穿過諸如藍寶石之一透明生長基板所看到之LED圖案之一視圖對準)來執行。
在已詳細闡述本發明之後,熟習此項技術者應瞭解,在給出本發明揭示內容之情形下,可對本發明進行修改而不背離本文中所述之本發明概念之精神。因此,並不意欲將本發明範疇限定於所圖解說明及所闡述之特定實施例。
10‧‧‧基板/生長基板
11‧‧‧區域
12‧‧‧n型區域
13‧‧‧表面/區域
14‧‧‧作用區域/發光或作用區域/發光區域/發光層
16‧‧‧p型區域
18‧‧‧金屬層/金屬/p觸點金屬
20‧‧‧金屬層/第二p觸點金屬/p觸點金屬
22‧‧‧電介質
24‧‧‧區域
26‧‧‧n觸點/金屬層/n金屬
27‧‧‧金屬層/金屬
28‧‧‧聚合物層
30‧‧‧聚合物層
32‧‧‧p觸點層/p觸點/金屬層/p金屬
33‧‧‧半導體發光裝置/裝置
34‧‧‧支撐基板
35‧‧‧主體
36‧‧‧選用電介質/電介質
38‧‧‧金屬/金屬層
40‧‧‧電介質
42‧‧‧介電接合層/接合層/電介質
44‧‧‧接合層/電介質
46‧‧‧接合層/電介質
48‧‧‧通孔
50‧‧‧電介質
52‧‧‧電連接
54‧‧‧電連接
55‧‧‧電介質
56‧‧‧焊料連接/連接
58‧‧‧焊料連接/連接
60‧‧‧互連件/焊料凸塊
62‧‧‧互連件/焊料凸塊
70‧‧‧反射性介電材料
110‧‧‧發光二極體晶粒/晶粒/發光二極體晶片/發光二極體
114‧‧‧基台
114-1‧‧‧玻璃區域
114-2‧‧‧矽區域
114-3‧‧‧其他矽區域
118-1‧‧‧金屬化物
118-2‧‧‧金屬化物
122-1‧‧‧焊料球
122-2‧‧‧焊料球
134‧‧‧板
135‧‧‧絕緣區域
138‧‧‧焊料接頭
200‧‧‧邊緣
202‧‧‧距離
圖1圖解說明一半導體發光裝置晶圓之一部分。圖1中圖解說明兩個發光裝置。
圖2圖解說明在添加一或多個金屬層及一或多個聚合物層之後圖1中之裝置中之一者。
圖3圖解說明藉由一金屬接合接合至一支撐基板之一裝置。
圖4圖解說明藉由一單個聚合物層接合至一支撐基板之一裝置。
圖5圖解說明藉由形成於裝置及支撐基板上之介電層接合至一支撐基板之一裝置。
圖6圖解說明在支撐基板之主體中形成通孔之後的圖3之結構。
圖7圖解說明在形成通孔及經圖案化金屬及介電層之後的圖4之結構。
圖8圖解說明在形成額外經圖案化金屬及介電層且附著焊料凸塊及一波長轉換層之後的圖7之結構。
圖9圖解說明形成於一n型區域之邊緣上之一反射體。
圖10圖解說明包含安裝在一基台之一LED之一先前技術裝置。
10‧‧‧基板/生長基板
12‧‧‧n型區域
14‧‧‧作用區域/發光或作用區域/發光區域/發光層
16‧‧‧p型區域
18‧‧‧金屬層/金屬/p觸點金屬
20‧‧‧金屬層/第二p觸點金屬/p觸點金屬
22‧‧‧電介質
26‧‧‧n觸點/金屬層/n金屬
28‧‧‧聚合物層
30‧‧‧聚合物層
32‧‧‧p觸點層/p觸點/金屬層/p金屬
33‧‧‧半導體發光裝置/裝置
34‧‧‧支撐基板
35‧‧‧主體
36‧‧‧選用電介質/電介質
38‧‧‧金屬/金屬層
40‧‧‧電介質
Claims (15)
- 一種用於將一發光裝置附著(attach)至一支撐基板的方法,其包括:提供一半導體發光裝置晶圓,每一半導體發光裝置包括夾在一n型區域與一p型區域之間之一發光層;提供一支撐基板晶圓,每一支撐基板包括一主體(body);將該半導體發光裝置晶圓經由一接合層(bonding layer)而接合至該支撐基板晶圓;及在將該半導體發光裝置晶圓接合至該支撐基板晶圓之後,形成延伸穿過每一支撐基板之該主體之整個厚度及穿過該接合層之一整個厚度之複數個通孔(vias)。
- 如請求項1之方法,其中將該半導體發光裝置晶圓接合至該支撐基板晶圓包括經由至少一個接合層接合。
- 如請求項2之方法,其中該至少一個接合層包括藉由電介質區域分離之金屬區域,其中該等金屬區域及該等電介質區域形成於每一支撐基板之該主體之一頂部表面上。
- 如請求項2之方法,其中該至少一個接合層包括形成於該半導體發光裝置之晶圓上之一聚合物層。
- 如請求項2之方法,其中該至少一個接合層包括形成於該半導體發光裝置晶圓上之一有機黏合劑。
- 如請求項2之方法,其中該至少一個接合層包括形成於該半導體發光裝置晶圓上之一第一介電接合層及形成於 該支撐基板晶圓上之一第二介電接合層。
- 如請求項6之方法,其中該第一介電接合層及該第二介電接合層包括矽之氧化物。
- 如請求項1之方法,其中每一支撐基板主體包括Si、GaAs及Ge中之一者。
- 如請求項1之方法,其中該形成延伸穿過每一支撐基板之該主體之該整個厚度之複數個通孔包括穿過每一支撐基板之該主體之該整個厚度蝕刻該複數個通孔以顯露至少一個金屬區域。
- 如請求項9之方法,其中該金屬區域係形成於該支撐基板晶圓上之一金屬接合層。
- 如請求項9之方法,其中該金屬區域係形成於該半導體發光裝置晶圓上且電連接至該n型區域及該p型區域中之一者之一金屬觸點。
- 如請求項1之方法,其進一步包括在將該半導體發光裝置晶圓接合至該支撐基板晶圓之後將該半導體發光裝置晶圓切割為個別發光裝置晶片。
- 如請求項12之方法,其進一步包括在切割該半導體發光裝置晶圓之前自該半導體發光裝置晶圓移除一生長基板。
- 如請求項13之方法,其進一步包括將藉由移除該生長基板曝露之該半導體發光裝置晶圓之一表面粗糙化,其中粗糙化發生在切割該半導體發光裝置晶圓之前。
- 如請求項12之方法,其進一步包括在切割該半導體發光 裝置晶圓之前將一波長轉換層安置於該半導體發光裝置晶圓上。
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US9431581B2 (en) | 2016-08-30 |
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WO2012164431A1 (en) | 2012-12-06 |
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