TWI584380B - 半導體裝置的製造方法 - Google Patents

半導體裝置的製造方法 Download PDF

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TWI584380B
TWI584380B TW100148387A TW100148387A TWI584380B TW I584380 B TWI584380 B TW I584380B TW 100148387 A TW100148387 A TW 100148387A TW 100148387 A TW100148387 A TW 100148387A TW I584380 B TWI584380 B TW I584380B
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semiconductor layer
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奧列格 科隆丘克
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Soitec公司
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Description

半導體裝置的製造方法
本發明關於一種製造半導體結構之方法，以及一種包含半導體層及金屬層之半導體結構，特別是關於一種製造半導體結構之方法及一種半導體結構，其可減少漏電流、提升崩潰電壓特性，並增進半導體裝置之效能，特別是用於功率半導體裝置中之蕭基能障。
通常，蕭基二極體為金屬層形成於半導體層上。蕭基能障會在金屬與半導體之接合處形成。蕭基二極體或蕭基能障二極體廣泛地使用在射頻應用上，如用做混波器或檢波器二極體。因蕭基二極體與傳統之p-n接面二極體相具有順向壓降及快速切換等特性，而亦用於(例如)切換器或整流器等功率元件。另外，蕭基二極體具有低反向電壓及快速恢復等特性，其商業應用包括輻射偵測、成像元件與有線及無線通訊產品。然而，蕭基二極體通常具有高漏電流及低崩潰電壓之問題。
基於此點，本發明之目的為提供一種製造半導體裝置結構之方法並提供一種半導體裝置結構，其可減低漏電流，增進崩潰電壓特性以提高元件之效能。
本發明之目的可以一種製造半導體結構之方法達成，其中半導體結構包含半導體層以及金屬層，此方法包含以下步驟：a)提供一半導體層，其包含瑕疵及(或)差排；b)將一或多個該些瑕疵及(或)差排處之材料移除，並藉此在半導體層中形成複數個坑；c)將坑鈍化；以及d)在半導體層上形成金屬層。
發明人發現移除半導體材料中之瑕疵及(或)差排可減少金屬-半導體介面處之漏電流並提升崩潰電壓，而不會影響金屬層之品質。也就是說，因坑被鈍化，金屬層下及鈍化坑之材料不會有瑕疵及(或)差排，或是其瑕疵及(或)差排少於塊材，如此可提升元件之效能。
此處之「瑕疵」意指材料中任何貫穿式差排、環差排、積層缺陷或晶粒介面。
較佳地，鈍化步驟可包括以介電材料至少部分填充該些坑。以介電材料填充坑可減少金屬-半導體介面處之漏電流，如此可增進功率元件之效能。也就是說，因這些坑至少被部分填充介電材料，在金屬層下方及介電材料間之材料不會有瑕疵及(或)差排，或是其瑕疵及(或)差排少於塊材，如此可提升元件之效能。
較佳地，移除材料b)之步驟包含在一或多個瑕疵及(或)差排處擇優性蝕刻半導體層之表面以在半導體層形成一或多個坑。已存在表面瑕疵處之坑可在此時被加大。這些坑足夠大以使失序之材料被由表面移除為佳，如此使坑與半導體層內之瑕疵及(或)差排相交。此蝕刻可選擇性地或擇優性地移除具有瑕疵及(或)差排之區域並保留無瑕疵之區域。
較佳地，介電材料可為氧化矽、氮化矽或其混合物。介電材料可增進金屬層與半導體層間之介面在元件應用上之電性。
較佳地，介電材料可完全填滿在步驟b)被移除材料之區域。藉由完全填滿被蝕刻區，可得到實質上無瑕疵之表面層。此填充可以沉積、長晶或其他將介電材料置於層之表面上之方式進行以防止坑之表面開口並覆蓋任何坑壁之暴露部分，但遠離坑之表面的完整部分可暴露出來。
較佳地，此方法更包含在步驟c)後拋光半導體層之表面的步驟。如此可移除半導體層之表面上多餘的介電材料。在以介電材料填充蝕刻區域後，可將半導體裝置之表面拋光以使表面實質上沒有瑕疵及(或)差排。較佳地，此拋光步驟可包括光滑化之步驟以使半導體層之鈍化表面較光滑。
較佳地，半導體層可由GaN、矽、應變矽、鍺、SiGe或III-V族材料、III/N材料、二元或三元或四元合金，如GaN、InGaN、AlGaN、AlGaInN及其類似物組成。較佳地，金屬層可由Al、Au、Pt、鉻、鈀、鎢、鉬或其矽化物、多晶或非晶材料及合金或其組合。這些金屬使蕭基能障達到所需之電性，並使其具有對選用之半導體層材料所需之附著性。
較佳地，金屬層以物理氣相沉積(physical vapor deposition,PVD)、濺鍍或化學氣相沉積形成，以使金屬層對底下之半導體層具有所需之附著性。
本發明之另一目的可以一種半導體結構達成，此半導體結構包含一半導體層以及形成於其上之一金屬層，其中半導體層中具有至少部分被介電材料填充之複數個坑。因這些坑至少被部分填充，而在金屬層下方及介電材料間之材料不會有瑕疵及(或)差排，或是其瑕疵及(或)差排少於塊材，如此可提升元件之效能。
較佳地，金屬層形成在半導體層上，而坑延伸至半導體層與金屬層之介面。
在如此形成之元件中，金屬-半導體介面處之崩潰電壓特性可提升，而漏電流可減少。
較佳地，介電材料可為氧化矽、氮化矽或其混合物。介電材料可增進金屬層與半導體層間之介面在元件應用上之電性。
較佳地，介電材料可完全填滿在步驟b)被移除材料之區域。藉由完全填滿被蝕刻區，可得到實質上無瑕疵之表面層。
依本發明一較佳實施例，填充介電材料之坑可排列在第一層中之差排及(或)瑕疵上。如此一來，可避免瑕疵及(或)差排對崩潰電壓之不良影響。也就是說，因填充有介電材料之坑排列在瑕疵及(或)差排之上，因此在金屬層下方及介電材料間之材料不會有瑕疵及(或)差排，或是其瑕疵及(或)差排少於塊材，如此可提升元件之效能。
本發明之目的亦可以使用上述之半導體結構之元件達成。
第1a-1e圖繪示依本發明第一實施例之製造半導體結構的方法。
本發明特定之實施例之敘述可參照所附圖式以使其更易於了解。
第1a圖繪示起始半導體結構1之剖面圖。半導體結構1包含基板3以及半導體層5，其位於基板3上。其他層(如緩衝層等)可在基板3與半導體層5之間。
基板3可做為起始材料以半導體層磊晶成長，且基板3例如為SiC或藍寶石基板或其類似物。半導體層5為半導體材料製成，其以GaN為佳，但亦可為矽、應變矽、鍺、SiGe或其他III-V族材料、III/N材料、二元或三元合金或四元如GaN、InGaN、AlGaN、AlGaInN及其類似物。半導體層5可以磊晶成長製程形成於基板3上，或以其他可在基板3上形成之製程方法，如膜層轉換或其他類似技術。若使用膜層轉換，可先使用離子種類佈植，然後以Smart CutTM技術將半導體層5由塊材上分離出來，並接合至基材3。半導體層5亦可在轉換前以磊晶成長於種子基板上。
依本實施例之一變化，基板3亦可包含轉移層，如GaNOS基板，其對應於具有轉移之GaN層的藍寶石基板，其將做為種子層。此種基材可依所需性質(如導電或導熱性等)包含金屬或隔離層以做為轉移層與基板間之接合層。基板3亦可為模板基板，如具有GaN層成長於其上之藍寶石基板
在此實施例中，半導體層5以n型雜質或p型雜質摻雜。半導體層5可依應用之不同而進行高或低濃度之摻雜。
第1a圖中之半導體層5包括數個瑕疵及(或)差排11a-11c。在半導體層5中之瑕疵及(或)差排11a-11c可因與基板3或種子基板之材料的結晶及(或)物理性質不匹配而形成。
在本發明一實施例中，在基板3與半導體層5間附近之區域3a中發生數個瑕疵及(或)差排11b-11d，其例如因基板3與半導體層5之材料結晶及(或)物理性質不匹配而形成，而瑕疵11a可因環差排而形成。瑕疵及(或)差排11a-11d沿半導體層5之厚度方向延續並傳播至半導體層5之表面。瑕疵及(或)差排11a-11d通常會延伸至半導體層5之暴露表面13。暴露表面13為如GaN之III-N材料時，其表面瑕疵及(或)差排密度通常可高至1x107cm-2。如為Si或Ge材料或Si1-yGey合金(其中y>0.2)時，瑕疵密度小於1x106cm-2。此值受半導體層5之厚度的影響相當大，原因詳述於下。
本發明之主要用於一定之差排密度以下之情況，而差排密度為層厚度之函數。實際上，依層之厚度不同，形成之坑的大小或多或少會有影響，而所有的坑可覆蓋半導體之整個表面，如此需要將材料拋光以重新尋得半導體材料。
通常當層為厚500nm之GaN時，經蝕刻之坑的直徑為1μm。在此情況下材料之差排密度應為1x107/cm2，以使GaN材料出現於表面13而不需拋光至GaN層。若層厚度為100nm，則坑之直徑可為200nm而差排密度可提高至1x108/cm2。
瑕疵密度通常可以習知技術量測，量測之方法包含原子力顯微鏡、光學顯微鏡、掃瞄式電子顯微鏡以及穿透式電子顯微鏡。依本實施例，較佳之量測瑕疵密度之方法為以穿透式電子顯微鏡(transmission electron microscopy，TEM)量測。
此瑕疵及(或)差排11a-11d會減低半導體裝置結構1之效能，其(例如)影響崩潰電壓且更會對暴露表面13之品質產生不良影響，而其又對形成於其上之層之品質產生不良影響。
第1b圖繪示由半導體層5之表面13上開始移除材料之步驟。在一或多個瑕疵及(或)差排11a-11d處移除材料。材料可(例如)以選擇性或擇優性蝕刻移除，例如可使用HCl以蝕刻III-N與矽材料。此蝕刻在暴露表面13上形成複數個蝕刻區13a-13d。
依本發明一實施例，此材料移除之步驟應至少在瑕疵及(或)差排由暴露表面附近被移除後才進行。如此可使高電場區實質上不含有瑕疵及(或)差排。如此可得到具有較佳表現之半導體裝置，且將其崩潰電壓性質最佳化。
在區域13a-13d被蝕刻之暴露表面13接著被鈍化以進行後續之製程步驟。第1c圖繪示以介電層或介電材料15至少部分填充區域13a-13d之步驟。依一變化，此填充步驟僅部分填充。
填充坑時，先將介電層15沉積於暴露表面13上，以使區域13a-13c至少部分被介電材料15填充。介電材料之填充可以沉積進行，其可使用化學氣相沉積(chemical vapor deposition，CVD)、電漿增強化學氣相(plasma enhanced chemical vapor deposition，PECVD)、低壓化學氣相沉積(low pressure chemical vapor deposition，LPCVD)或長晶，或其他可將介電材料配置於半導體層5之暴露表面13上之方法，以防止坑之表面開口並覆蓋任何坑壁之暴露部分。在此實施例中，介電材料15可依應用方式選擇氧化矽、氮化矽或其組合。
在本發明之此實施例中，如第1c圖所示，介電材料15完全填滿區域13a-13c。另外，在此實施例中之介電材料15不僅完全填滿區域13a-13d，亦在半導體層5上形成厚度D之介電材料層15。厚度D可以任何習知技術測定，如以光學橢圓術(optical ellipsometry)及其類似方法量測。依本實施例，厚度D實質上至少與第1c圖中所繪示之坑的深度相同，其至少回到半導體層5之表面13之厚度。
第1d圖繪示拋光介電材料15之表面17之步驟。介電材料15以傳統方式拋光，如化學機械拋光(chemical mechanical polishing，CMP)。介電材料15經拋光以移除p型半導體層5上多餘之介電材料，並使區域13a-13d維持填滿介電材料15'之狀態。半導體裝置結構1之表面經拋光以使表面具有不含瑕疵及(或)差排及多餘之介電材料之區域。
多餘之介電材料與介電材料中配置於暴露表面13但未關閉坑之開口的部分相關。多餘之介電材料在拋光步驟中被移除。亦可在暴露表面13上進行表面光滑化製程。表面13最後產生之粗糙度在拋光步驟後、生成金屬層7之沉積前例如約為5x5微米中有數nm(若為III-N材料)或小於1nm(若為Si,SiGe材料)。
繪示於第1d圖中之半導體裝置結構1'與第1a圖中之半導體裝置結構1相較下，在第一及第二層間之介面具有較少之瑕疵及(或)差排，因其瑕疵及(或)差排由延伸至半導體層5之區域13a-13d中被移除。除此之外，半導體裝置結構1'具有較佳之表面電性品質，半導體層5之表面以介電材料15進行鈍化。
第1e圖繪示在無瑕疵之半導體層5上形成金屬層7之步驟，藉此可形成半導體-金屬接面。因具有鈍化坑，可減少在半導體層與金屬層間之介面區之漏電流，並提升崩潰電壓之特性，特別是在上述之介面附近。
依本發明，半導體結構包含蕭基能障二極體，其具有半導體層5以及金屬層7以形成半導體-金屬接面。在此蕭基二極體中，可減少漏電流，並藉此得到具有較佳高電場特性之元件。
較佳地，金屬層7可為Al、Au、Pt、鉻、鈀、鎢、鉬或其矽化物、多晶或非晶材料及合金，及其他具有適當之蕭基能障及適當之對半導體材料吸附性質之金屬或其組合。金屬層亦可為多晶或非晶材料。金屬層(例如)可以物理氣相沉積(physical vapor deposition,PVD)、濺鍍、化學氣相沉積(chemical vapor deposition,CVD)形成。
較佳地，基板3由半導體層5被移除或分離，使用後之基板3若不具後續步驟應有之性質，則可被回收。
各實施例中之各別特徵可獨立地與其他特徵彼此結合以得到更多本發明之實施例之變化。
本發明之實施例因在形成金屬層前將半導體層之表面上之瑕疵及(或)差排移除，而在在崩潰電壓上具有較佳之表現。另外，在金屬-半導體層間介面附近之漏電流亦減少。
1、1'．．．半導體結構
3．．．基板
3a．．．區域
5．．．半導體層
7．．．金屬層
11a-11c．．．瑕疵及(或)差排
13．．．暴露表面
13a-13d．．．區域
15．．．介電材料
17．．．表面
第1a-1e圖繪示依本發明第一實施例之製備半導體結構的方法，此半導體結構具有半導體層以及金屬層。
1'．．．半導體結構
3．．．基板
3a．．．區域
5．．．半導體層
7．．．金屬層

Claims (12)

  1. 一種製造半導體結構之方法，該半導體裝置結構包含一單晶半導體層以及一金屬層，該方法包含以下步驟：a)提供一單晶半導體層，其包含差排，其中該單晶半導體層係選自GaN、矽、應變矽、鍺、SiGe或III-V族材料、III/N材料、二元或三元或四元合金，如GaN、InGaN、AlGaN、AlGaInN及其類似物；b)將一或多個該些差排處之材料移除，並藉此在單晶半導體層中形成複數個坑；c)將坑鈍化；以及d)在單晶半導體層上及該些經鈍化的坑上直接形成金屬層，藉此形成半導體-金屬介面，其中該金屬層係選自Au、Pt、鉻、鈀、鎢、鉬或其矽化物、多晶或非晶材料及其合金或組合。
  2. 如申請專利範圍第1項之方法，其中鈍化步驟c)包括以介電材料至少部分填充該些坑之步驟。
  3. 如申請專利範圍第1或2項之方法，其中移除材料b)之步驟包含在一或多個該些差排處擇優性蝕刻該單晶半導體層之表面。
  4. 如申請專利範圍第2項之方法，其中該介電材料為氧化矽、氮化矽或其混合物。
  5. 如申請專利範圍第2項之方法，其中該介電材料完全填滿在步驟b)中形成之該些坑。
  6. 如申請專利範圍第1項之方法，其更包含在步驟c)後步驟d)前拋光該單晶半導體層的步驟e)。
  7. 如申請專利範圍第1項之方法，其中該金屬層以物理氣相沉積(physical vapor deposition,PVD)、濺鍍或化學氣相況積形成。
  8. 一種半導體結構，其包含一單晶半導體層以及形成於其上之一金屬層，其中該單晶半導體層中具有至少部分被介電材料填充之複數個坑，其排列在位於該單晶半導體層中之複數個差排上，其中該金屬層直接形成在該單晶半導體層及至少部分被介電材料填充之該些坑上，藉此形成一半導體-金屬介面，其中該單晶半導體層係選自GaN、矽、應變矽、鍺、SiGe或III-V族材料、III/N材料、二元或三元或四元合金，如GaN、InGaN、AlGaN、AlGaInN及其類似物，而該金屬層係選自Au、Pt、鉻、鈀、鎢、鉬或其矽化物、多晶或非 晶材料及其合金或組合。
  9. 如申請專利範圍第8項之半導體結構，其中該金屬層形成於該單晶半導體層上，且該些坑延伸至半導體層與金屬層之介面。
  10. 如申請專利範圍第8或9項之半導體結構，其中該介電材料為氧化矽、氮化矽或其混合物。
  11. 如申請專利範圍第8項之半導體結構，其中該些坑完全被介電材料填充。
  12. 一種使用申請專利範圍第8至11項中任一項之半導體結構之蕭基二極體。
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FR2969815A1 (fr) 2012-06-29
KR20140098769A (ko) 2014-08-08
KR20180091955A (ko) 2018-08-16
JP6064232B2 (ja) 2017-01-25
JP2015500572A (ja) 2015-01-05
DE112011106083T5 (de) 2014-12-31
WO2012089315A1 (en) 2012-07-05
SG11201403121YA (en) 2014-10-30
TW201234491A (en) 2012-08-16
FR2969815B1 (fr) 2013-11-22
CN104025268A (zh) 2014-09-03
US20140370695A1 (en) 2014-12-18
CN110189996A (zh) 2019-08-30

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